Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22942

1

T1

193

T3

12

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3873

1

T2

51

T8

35

T10

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20078

1

T1

192

T2

35

T3

12

auto[1]

6737

1

T1

1

T2

16

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	386	1			T1	1		T48	7		T50	2
values[0]	73	1			T12	8		T47	33		T279	16
values[1]	886	1			T2	16		T8	9		T10	9
values[2]	2900	1			T4	1		T8	35		T9	19
values[3]	812	1			T8	20		T11	1		T44	37
values[4]	727	1			T46	11		T135	23		T133	12
values[5]	794	1			T2	27		T13	27		T134	1
values[6]	662	1			T11	1		T33	27		T147	1
values[7]	793	1			T2	8		T7	21		T13	11
values[8]	684	1			T11	1		T44	1		T194	33
values[9]	1258	1			T14	15		T47	1		T49	24
minimum	16840	1			T1	192		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1184	1			T2	16		T8	44		T10	9
values[1]	2860	1			T4	1		T8	20		T9	19
values[2]	788	1			T44	37		T45	17		T133	12
values[3]	787	1			T2	27		T11	1		T13	27
values[4]	700	1			T11	1		T134	1		T161	4
values[5]	758	1			T2	8		T46	14		T49	27
values[6]	689	1			T7	21		T11	1		T13	11
values[7]	714	1			T14	7		T44	1		T49	13
values[8]	927	1			T14	8		T47	1		T49	11
values[9]	176	1			T27	8		T157	1		T217	21
minimum	17232	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	7		T12	6		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T2	9		T8	21		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T4	1		T8	11		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T194	1		T35	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T44	25		T45	17		T133	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T39	1		T190	13		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T28	14		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	12		T13	14		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	1		T134	1		T193	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T161	4		T171	1		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	1		T175	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	8		T46	14		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	10		T13	6		T194	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	1		T44	14		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T49	1		T217	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T44	1		T158	8		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T137	7		T163	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T47	1		T49	5		T57	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T217	12		T225	12		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T27	4		T157	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17099	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T44	1		T61	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T8	2		T12	2		T14	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	7		T8	14		T10	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T8	9		T9	17		T10	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T194	1		T35	12		T189	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	12		T37	8		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T190	14		T229	6		T218	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	2		T150	13		T276	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	15		T13	13		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T227	14		T213	13		T256	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T148	10		T229	7		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	4		T218	7		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T49	13		T33	15		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	11		T13	5		T194	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	11		T57	2		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	6		T49	12		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T242	8		T18	2		T220	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	7		T137	14		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	6		T57	12		T226	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T217	9		T225	13		T196	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T27	4		T241	2		T312	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T44	5		T61	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T1	1		T48	7		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T27	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T12	6		T170	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T47	20		T279	8		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	7		T14	1		T45	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	9		T10	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T4	1		T9	2		T10	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	21		T194	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	11		T11	1		T44	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T35	11		T190	13		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T133	12		T28	14		T35	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	11		T135	23		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	1		T193	2		T141	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	12		T13	14		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	12		T171	1		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	10		T13	6		T17	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	8		T44	14		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T194	16		T35	12		T217	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	1		T44	1		T158	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T14	2		T49	1		T137	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T47	1		T49	5		T57	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16720	1			T1	192		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T27	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T12	2		T170	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T47	13		T279	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	2		T14	9		T57	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	7		T10	8		T44	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T9	17		T10	9		T216	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	14		T194	1		T189	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	9		T44	12		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	12		T190	14		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T35	2		T177	7		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	11		T218	10		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T227	14		T213	13		T256	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	15		T13	13		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	4		T240	13		T257	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T33	15		T229	7		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	11		T13	5		T17	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	11		T49	13		T57	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T194	17		T35	11		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T140	9		T218	14		T242	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T14	13		T49	12		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T49	6		T57	12		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T8	3		T12	3		T14	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T2	8		T8	15		T10	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T4	1		T8	10		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T194	2		T35	13		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	13		T45	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T39	1		T190	15		T229	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T28	1		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	16		T13	14		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T134	1		T193	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	1		T171	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T147	1		T175	1		T39	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T46	1		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	12		T13	6		T194	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T44	12		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	7		T49	13		T217	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	1		T158	1		T242	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	8		T137	15		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T47	1		T49	7		T57	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T217	10		T225	14		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T27	6		T157	1		T241	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17219	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T44	6		T61	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	6		T12	5		T45	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T2	8		T8	20		T47	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T8	10		T10	12		T28	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	10		T197	8		T213	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T44	24		T45	16		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T190	12		T218	10		T202	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	13		T35	6		T141	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	11		T13	13		T46	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T184	10		T227	3		T213	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T161	3		T139	10		T197	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	2		T244	10		T218	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	7		T46	13		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	9		T13	5		T194	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	13		T57	8		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T217	10		T165	3		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T158	7		T18	3		T86	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T137	6		T163	7		T40	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	4		T57	9		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T217	11		T225	11		T196	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T27	2		T208	2		T314	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T1	1		T48	7		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T27	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T12	3		T170	14		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T47	14		T279	9		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	3		T14	10		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	8		T10	9		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T4	1		T9	19		T10	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	15		T194	2		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	10		T11	1		T44	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	13		T190	15		T229	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T133	1		T28	1		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	1		T135	2		T144	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T134	1		T193	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	16		T13	14		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T33	16		T171	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	12		T13	6		T17	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T44	12		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T194	18		T35	12		T217	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T44	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T14	15		T49	13		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T47	1		T49	7		T57	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16840	1			T1	192		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T27	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T12	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T47	19		T279	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	6		T45	6		T161	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	8		T47	15		T190	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T10	12		T28	10		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	20		T197	8		T213	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	10		T44	24		T45	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	10		T190	12		T202	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	11		T28	13		T35	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	10		T135	21		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	4		T184	10		T227	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	11		T13	13		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	2		T244	10		T215	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	11		T141	14		T165	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	9		T13	5		T17	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	7		T44	13		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T194	15		T35	11		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T158	7		T218	15		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	6		T163	7		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T49	4		T57	9		T208	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36