Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22956

1

T1

193

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3859

1

T2

16

T7

21

T8

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19976

1

T1

192

T2

43

T3

12

auto[1]

6839

1

T1

1

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	635	1			T1	1		T48	7		T50	2
values[0]	11	1			T45	7		T284	4		-	-
values[1]	934	1			T2	16		T8	9		T10	9
values[2]	2874	1			T4	1		T8	35		T9	19
values[3]	856	1			T8	20		T11	1		T44	37
values[4]	762	1			T13	27		T46	11		T135	23
values[5]	760	1			T2	27		T134	1		T161	4
values[6]	692	1			T11	1		T49	27		T33	27
values[7]	759	1			T2	8		T7	21		T11	1
values[8]	720	1			T44	1		T194	33		T35	23
values[9]	972	1			T14	15		T47	1		T49	24
minimum	16840	1			T1	192		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	931	1			T2	16		T8	35		T12	8
values[1]	2871	1			T4	1		T8	20		T9	19
values[2]	797	1			T44	37		T45	17		T133	12
values[3]	735	1			T11	1		T13	27		T46	11
values[4]	789	1			T2	27		T11	1		T134	1
values[5]	727	1			T2	8		T44	25		T46	14
values[6]	697	1			T7	21		T11	1		T13	11
values[7]	701	1			T44	1		T158	8		T217	13
values[8]	923	1			T14	15		T47	1		T49	24
values[9]	162	1			T27	8		T225	25		T208	18
minimum	17482	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	6		T14	1		T47	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	9		T8	21		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T4	1		T8	11		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T194	1		T35	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	1		T171	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T44	25		T45	17		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	1		T13	14		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T135	5		T28	14		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	12		T11	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T161	4		T193	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	8		T147	1		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T44	14		T46	14		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	6		T194	16		T33	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	10		T11	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	1		T217	11		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T158	8		T242	1		T18	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T14	1		T47	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	1		T49	5		T57	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T27	4		T225	12		T208	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T208	3		T84	1		T196	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17170	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T10	1		T44	1		T45	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	2		T14	9		T47	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	7		T8	14		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T8	9		T9	17		T10	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T194	1		T35	12		T189	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	8		T190	14		T198	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	12		T229	6		T218	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	13		T35	2		T150	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	11		T202	11		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	15		T240	13		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	10		T229	7		T227	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T218	7		T257	6		T215	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	11		T49	13		T33	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	5		T194	17		T33	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	11		T57	2		T17	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T217	2		T40	3		T191	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T242	8		T18	2		T220	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	6		T49	12		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	7		T49	6		T57	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T27	4		T225	13		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T196	4		T168	10		T307	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	2		T13	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T10	8		T44	5		T47	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T1	1		T48	7		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T84	1		T315	13		T196	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T284	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T45	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T8	7		T12	6		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	9		T10	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T4	1		T9	2		T10	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	21		T194	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	11		T11	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T44	25		T45	17		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	14		T46	11		T135	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T135	5		T133	12		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T134	1		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T161	4		T193	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T49	14		T33	12		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	8		T13	6		T33	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	10		T11	1		T44	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	1		T194	16		T217	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	12		T158	8		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T14	1		T47	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T49	5		T57	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16720	1			T1	192		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T27	4		T81	2		T214	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T196	4		T168	10		T252	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T284	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	2		T12	2		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	7		T10	8		T44	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T9	17		T10	9		T216	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	14		T194	1		T189	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	9		T37	8		T190	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	12		T35	12		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	13		T35	2		T198	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	11		T202	11		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	15		T213	13		T256	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T229	7		T227	23		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T240	13		T257	6		T215	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T49	13		T33	15		T39	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	5		T33	12		T217	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	11		T44	11		T57	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T194	17		T217	2		T40	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T35	11		T140	9		T218	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T14	6		T49	12		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	7		T49	6		T57	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	3		T14	10		T47	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	8		T8	15		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T4	1		T8	10		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T194	2		T35	13		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	9		T171	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T44	13		T45	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T13	14		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T135	1		T28	1		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	16		T11	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T161	1		T193	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	1		T147	1		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	12		T46	1		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	6		T194	18		T33	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	12		T11	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T44	1		T217	3		T40	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T158	1		T242	9		T18	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	7		T47	1		T49	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	8		T49	7		T57	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T27	6		T225	14		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T208	1		T84	1		T196	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17270	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T10	9		T44	6		T45	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	5		T47	15		T161	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	8		T8	20		T221	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T8	10		T10	12		T28	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	10		T197	8		T213	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T190	12		T220	14		T208	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T44	24		T45	16		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	13		T46	10		T135	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	4		T28	13		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	11		T141	4		T213	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T161	3		T184	10		T197	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	7		T141	2		T218	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T44	13		T46	13		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	5		T194	15		T33	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	9		T57	8		T17	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T217	10		T40	5		T165	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T158	7		T18	3		T86	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T137	6		T217	11		T232	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	4		T57	9		T163	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T27	2		T225	11		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T208	2		T196	11		T168	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T8	6		T39	8		T316	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T45	6		T47	19		T148	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T1	1		T48	7		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T84	1		T315	1		T196	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T284	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T45	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T8	3		T12	3		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	8		T10	9		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T4	1		T9	19		T10	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	15		T194	2		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	10		T11	1		T37	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T44	13		T45	1		T35	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	14		T46	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T135	1		T133	1		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	16		T134	1		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T161	1		T193	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T49	14		T33	16		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	1		T13	6		T33	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	12		T11	1		T44	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	1		T194	18		T217	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	12		T158	1		T140	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T14	7		T47	1		T49	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	8		T49	7		T57	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16840	1			T1	192		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T27	2		T208	14		T81	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T315	12		T196	11		T168	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T284	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T45	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	6		T12	5		T47	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	8		T47	19		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T10	12		T28	10		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	20		T197	8		T213	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	10		T190	12		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T44	24		T45	16		T35	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	13		T46	10		T135	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	4		T133	11		T28	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	11		T141	4		T251	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T161	3		T184	10		T197	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T141	2		T251	12		T165	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	13		T33	11		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	7		T13	5		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	9		T44	13		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T194	15		T217	10		T40	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	11		T158	7		T218	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T137	6		T217	11		T232	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	4		T57	9		T163	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36