Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23068

1

T1

193

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3747

1

T2

16

T8

55

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20749

1

T1

193

T2

8

T3

12

auto[1]

6066

1

T2

43

T4

1

T8

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	408	1			T14	10		T110	1		T28	11
values[0]	27	1			T242	9		T290	8		T317	4
values[1]	898	1			T10	9		T13	38		T14	8
values[2]	606	1			T35	23		T147	1		T210	14
values[3]	932	1			T11	1		T44	6		T161	10
values[4]	646	1			T2	16		T8	35		T11	1
values[5]	2745	1			T2	8		T4	1		T9	19
values[6]	650	1			T2	27		T7	21		T8	9
values[7]	910	1			T12	8		T49	27		T17	44
values[8]	717	1			T11	1		T50	1		T47	34
values[9]	1058	1			T8	20		T10	22		T14	7
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	810	1			T10	9		T13	38		T44	1
values[1]	760	1			T33	28		T35	23		T210	14
values[2]	788	1			T11	1		T134	1		T44	6
values[3]	2776	1			T2	16		T4	1		T8	35
values[4]	664	1			T2	8		T7	21		T46	25
values[5]	611	1			T2	27		T8	9		T45	7
values[6]	989	1			T12	8		T47	33		T49	27
values[7]	646	1			T11	1		T50	1		T47	1
values[8]	1082	1			T8	20		T10	22		T14	17
values[9]	209	1			T44	37		T138	33		T244	11
minimum	17480	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	1		T13	20		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T137	1		T139	11		T39	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T35	12		T210	14		T163	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T33	16		T145	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T161	10		T57	9		T163	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T134	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T4	1		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	9		T8	21		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	8		T7	10		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	14		T47	16		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	12		T8	7		T45	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T148	12		T19	1		T81	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T47	20		T49	14		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	6		T17	21		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	1		T50	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T57	6		T28	14		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T10	13		T14	2		T44	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	11		T49	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T44	25		T236	2		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T138	18		T244	11		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17182	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T135	18		T147	1		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	8		T13	18		T194	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T137	11		T39	11		T217	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	11		T217	9		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T33	12		T145	9		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T57	2		T39	4		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	5		T162	6		T243	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T9	17		T216	26		T248	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	7		T8	14		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	11		T49	6		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	12		T27	4		T191	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	15		T8	2		T57	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T148	10		T81	2		T268	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	13		T49	13		T35	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T12	2		T17	23		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	14		T35	2		T37	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T57	14		T198	12		T209	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T10	9		T14	15		T44	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	9		T49	12		T194	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T44	12		T166	17		T252	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T138	15		T249	4		T319	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T14	7		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T242	8		T61	2		T267	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T14	1		T110	1		T33	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	11		T193	1		T138	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T290	8		T317	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T242	1		T183	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T10	1		T13	20		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	18		T137	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	12		T147	1		T210	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	11		T217	1		T251	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T161	10		T57	9		T163	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	1		T44	1		T135	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T11	1		T171	1		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	9		T8	21		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T2	8		T4	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	16		T27	4		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	12		T7	10		T8	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	14		T191	1		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T49	14		T35	11		T232	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	6		T17	21		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T50	1		T47	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T57	6		T28	14		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	13		T14	1		T44	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T8	11		T49	1		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T14	9		T33	15		T189	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	15		T229	7		T151	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T242	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	8		T13	18		T14	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	11		T39	11		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	11		T246	11		T218	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T217	13		T177	7		T261	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T57	2		T217	9		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	5		T33	12		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T39	4		T209	1		T93	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	7		T8	14		T229	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T9	17		T49	6		T216	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T47	12		T27	4		T221	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	15		T7	11		T8	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T191	5		T148	10		T81	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	13		T35	12		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	2		T17	23		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	13		T137	14		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T57	14		T202	11		T198	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T10	9		T14	6		T44	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	9		T49	12		T194	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	9		T13	20		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	12		T139	1		T39	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T35	12		T210	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	13		T145	10		T217	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T161	1		T57	3		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T134	1		T44	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T4	1		T9	19		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	8		T8	15		T229	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	1		T7	12		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	1		T47	13		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	16		T8	3		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T148	11		T19	1		T81	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	14		T49	14		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T12	3		T17	26		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T50	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T57	15		T28	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T10	10		T14	17		T44	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	10		T49	13		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T44	13		T236	2		T166	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T138	16		T244	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17282	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T135	1		T147	1		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	18		T161	3		T141	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	10		T39	8		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T35	11		T210	13		T163	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T33	15		T251	9		T202	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T161	9		T57	8		T163	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T135	4		T158	7		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T45	16		T159	20		T234	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	8		T8	20		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	7		T7	9		T46	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	13		T47	15		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	11		T8	6		T45	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T148	11		T81	7		T214	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T47	19		T49	13		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	5		T17	18		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T137	6		T35	6		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T57	5		T28	13		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	12		T44	13		T33	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	10		T133	11		T194	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T44	24		T252	13		T206	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T138	17		T244	10		T319	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T214	11		T290	7		T320	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T135	17		T197	8		T267	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	10		T110	1		T33	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T28	1		T193	1		T138	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T290	1		T317	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T242	9		T183	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	9		T13	20		T14	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T135	1		T137	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T35	12		T147	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	1		T217	14		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T161	1		T57	3		T163	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	1		T44	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	1		T171	1		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	8		T8	15		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T2	1		T4	1		T9	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	13		T27	6		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	16		T7	12		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T191	6		T148	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T49	14		T35	13		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	3		T17	26		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T50	1		T47	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T57	15		T28	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T10	10		T14	7		T44	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	10		T49	13		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T33	11		T252	13		T321	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T28	10		T138	17		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T290	7		T317	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T183	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	18		T161	3		T141	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	17		T39	8		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	11		T210	13		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T139	10		T251	9		T165	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	9		T57	8		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T135	4		T33	15		T158	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T141	4		T93	15		T253	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	8		T8	20		T218	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T2	7		T45	16		T46	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	15		T27	2		T254	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	11		T7	9		T8	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	13		T148	11		T208	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	13		T35	10		T232	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	5		T17	18		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	19		T137	6		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T57	5		T28	13		T202	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T10	12		T44	37		T190	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T8	10		T133	11		T194	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36