Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23143

1

T1

193

T2

51

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3672

1

T8

35

T11

1

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20570

1

T1

193

T2

35

T3

12

auto[1]

6245

1

T2

16

T4

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	180	1			T110	1		T155	1		T147	1
values[0]	50	1			T229	7		T212	14		T265	12
values[1]	780	1			T7	21		T11	1		T13	11
values[2]	2848	1			T2	24		T4	1		T9	19
values[3]	752	1			T8	9		T49	11		T57	11
values[4]	572	1			T14	7		T134	1		T49	13
values[5]	854	1			T8	35		T46	11		T17	44
values[6]	731	1			T14	10		T44	1		T171	1
values[7]	874	1			T10	9		T11	1		T13	27
values[8]	746	1			T8	20		T12	8		T133	12
values[9]	1210	1			T2	27		T10	22		T11	1
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	758	1			T7	21		T11	1		T13	11
values[1]	2763	1			T2	24		T4	1		T9	19
values[2]	890	1			T8	9		T14	15		T134	1
values[3]	577	1			T46	11		T161	10		T137	21
values[4]	921	1			T8	35		T28	14		T33	28
values[5]	594	1			T14	10		T44	1		T193	1
values[6]	848	1			T10	9		T11	1		T12	8
values[7]	817	1			T8	20		T10	22		T47	1
values[8]	1055	1			T2	27		T11	1		T50	1
values[9]	125	1			T45	17		T147	1		T138	25
minimum	17467	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	10		T11	1		T13	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T44	1		T46	14		T135	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T2	17		T4	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T35	12		T146	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	7		T47	20		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	2		T134	1		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	11		T17	21		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T161	10		T137	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T28	14		T33	16		T184	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	21		T35	11		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	1		T193	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T171	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	1		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	6		T47	16		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	11		T10	13		T28	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	1		T133	12		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T2	12		T50	1		T44	39
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	1		T135	5		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T45	17		T147	1		T214	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T138	13		T165	19		T21	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17141	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T194	1		T146	1		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	11		T13	5		T190	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T44	5		T194	17		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T2	7		T9	17		T216	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	11		T229	7		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	2		T47	13		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	13		T49	6		T39	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	23		T217	2		T162	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T137	14		T138	15		T257	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T33	12		T227	9		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	14		T35	12		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T191	5		T218	7		T198	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	9		T218	24		T61	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	8		T13	13		T57	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	2		T47	12		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	9		T10	9		T35	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	11		T217	13		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	15		T44	23		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	8		T41	1		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T235	7		T182	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T138	12		T152	5		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T48	2		T57	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T194	1		T150	13		T283	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T110	1		T147	1		T243	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T155	1		T138	13		T41	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T229	1		T265	12		T250	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T212	1		T262	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	10		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T44	1		T135	18		T194	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T2	17		T4	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T46	14		T35	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	7		T57	9		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	5		T39	2		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	1		T137	1		T33	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T134	1		T161	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T46	11		T17	21		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	21		T35	11		T138	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	1		T218	8		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T171	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	1		T11	1		T13	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	16		T40	8		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	11		T35	7		T141	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	6		T133	12		T158	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T2	12		T10	13		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	1		T47	1		T135	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	14		T322	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T138	12		T41	1		T260	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T229	6		T250	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	11		T13	5		T57	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	5		T194	18		T213	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T2	7		T9	17		T47	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	7		T35	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	2		T57	2		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	6		T39	4		T229	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	12		T137	11		T33	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	6		T137	14		T225	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T17	23		T33	12		T217	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	14		T35	12		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T218	7		T198	10		T213	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	9		T218	24		T61	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	8		T13	13		T57	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	12		T40	3		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	9		T35	2		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	2		T39	11		T217	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	15		T10	9		T44	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T37	8		T148	10		T227	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	12		T11	1		T13	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	6		T46	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T2	9		T4	1		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	12		T146	1		T229	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T8	3		T47	14		T49	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	15		T134	1		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	1		T17	26		T217	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	1		T137	15		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T28	1		T33	13		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	15		T35	13		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	1		T193	1		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	10		T171	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	9		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	3		T47	13		T40	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	10		T10	10		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T47	1		T133	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T2	16		T50	1		T44	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	1		T135	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T45	1		T147	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	13		T165	1		T21	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17279	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T194	2		T146	1		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	9		T13	5		T161	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	13		T135	17		T194	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T2	15		T159	20		T234	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	11		T165	3		T208	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	6		T47	19		T57	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	4		T139	10		T225	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	10		T17	18		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T161	9		T137	6		T138	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T28	13		T33	15		T184	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	20		T35	10		T202	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T218	7		T208	2		T264	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T218	25		T254	22		T258	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	13		T57	5		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	5		T47	15		T40	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	10		T10	12		T28	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T133	11		T158	7		T39	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	11		T44	37		T45	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	4		T210	13		T163	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T45	16		T214	5		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	12		T165	18		T152	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T57	9		T22	4		T323	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T197	8		T150	15		T283	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T110	1		T147	1		T243	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T155	1		T138	13		T41	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T229	7		T265	1		T250	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T212	14		T262	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	12		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T44	6		T135	1		T194	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T2	9		T4	1		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	8		T46	1		T35	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	3		T57	3		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T49	7		T39	6		T229	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	13		T137	12		T33	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	7		T134	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T46	1		T17	26		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	15		T35	13		T138	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T44	1		T218	8		T198	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	10		T171	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T10	9		T11	1		T13	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	13		T40	6		T189	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	10		T35	3		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	3		T133	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T2	16		T10	10		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T11	1		T47	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T243	17		T322	5		T324	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T138	12		T41	1		T165	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T265	11		T250	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	9		T13	5		T161	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T135	17		T194	15		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T2	15		T47	19		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	13		T35	11		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	6		T57	8		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	4		T208	14		T93	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T33	11		T162	6		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T161	9		T137	6		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	10		T17	18		T28	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	20		T35	10		T138	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T218	7		T208	2		T213	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T218	25		T254	10		T267	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	13		T57	5		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	15		T40	5		T202	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	10		T35	6		T141	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	5		T133	11		T158	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T2	11		T10	12		T44	37
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T135	4		T210	13		T163	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36