Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22535

1

T1

193

T2

8

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

4280

1

T2

43

T7

21

T8

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20508

1

T1

193

T2

16

T3

12

auto[1]

6307

1

T2

35

T4

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	72	1			T14	10		T50	1		T33	28
values[0]	60	1			T135	5		T38	15		T311	1
values[1]	659	1			T47	61		T57	22		T138	25
values[2]	829	1			T2	27		T14	8		T134	1
values[3]	840	1			T2	8		T8	9		T110	1
values[4]	604	1			T10	22		T11	1		T12	8
values[5]	886	1			T7	21		T8	35		T44	25
values[6]	986	1			T11	1		T13	27		T44	37
values[7]	695	1			T8	20		T10	9		T161	10
values[8]	670	1			T13	11		T161	4		T135	18
values[9]	3296	1			T2	16		T4	1		T9	19
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	789	1			T47	33		T135	5		T57	33
values[1]	888	1			T2	35		T8	9		T14	8
values[2]	799	1			T46	11		T49	24		T35	9
values[3]	771	1			T7	21		T10	22		T11	1
values[4]	967	1			T8	35		T44	62		T47	1
values[5]	804	1			T8	20		T11	1		T13	27
values[6]	2767	1			T4	1		T9	19		T10	9
values[7]	575	1			T2	16		T13	11		T161	4
values[8]	1000	1			T11	1		T14	10		T50	1
values[9]	209	1			T193	1		T39	21		T190	1
minimum	17246	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T57	19		T138	13		T217	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T47	20		T135	5		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	8		T14	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T2	12		T8	7		T17	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	1		T147	1		T210	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T46	11		T49	5		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	13		T12	6		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T7	10		T11	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	21		T33	12		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T44	39		T47	1		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T224	1		T227	4		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	11		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T4	1		T9	2		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	10		T135	18		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T158	8		T193	1		T251	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	9		T13	6		T161	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T50	1		T137	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T11	1		T44	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T193	1		T231	1		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T39	10		T190	1		T293	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T47	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T57	14		T138	12		T217	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	13		T37	8		T190	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	7		T264	11		T238	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	15		T8	2		T17	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	12		T218	21		T61	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	6		T35	2		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	9		T12	2		T14	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	11		T44	5		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	14		T33	15		T241	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T44	23		T27	4		T190	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T227	14		T295	2		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	9		T13	13		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T9	17		T10	8		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T39	4		T41	1		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T240	13		T230	13		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	7		T13	5		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	9		T137	14		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T137	11		T194	1		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T231	6		T152	11		T325	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	11		T293	7		T326	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T47	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T14	1		T50	1		T33	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T202	8		T327	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T311	1		T328	7		T206	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T135	5		T38	1		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T57	10		T138	13		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	36		T141	5		T197	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	1		T134	1		T57	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	12		T49	5		T17	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	8		T110	1		T46	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T8	7		T46	11		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	13		T12	6		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T44	1		T194	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	21		T45	17		T33	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	10		T44	14		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T35	12		T162	7		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	1		T13	14		T44	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	1		T193	1		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	11		T161	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T158	8		T193	1		T251	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	6		T161	4		T135	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T4	1		T9	2		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T2	9		T11	1		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T14	9		T33	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T202	11		T327	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T328	2		T206	7		T329	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T38	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T57	12		T138	12		T217	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T47	25		T148	10		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	7		T57	2		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	15		T49	6		T17	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T218	21		T61	2		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	2		T144	11		T225	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	9		T12	2		T14	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T44	5		T194	17		T35	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	14		T33	15		T152	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	11		T44	11		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	11		T162	6		T295	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	13		T44	12		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	8		T229	6		T227	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	9		T39	4		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T240	13		T151	13		T326	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	5		T217	9		T213	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T9	17		T137	14		T216	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	7		T137	11		T194	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T57	16		T138	13		T217	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T47	14		T135	1		T37	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T14	8		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	16		T8	3		T17	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	13		T147	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T46	1		T49	7		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	10		T12	3		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	12		T11	1		T44	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	15		T33	16		T241	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T44	25		T47	1		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T224	1		T227	15		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	10		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T4	1		T9	19		T10	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T161	1		T135	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T158	1		T193	1		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	8		T13	6		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	10		T50	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T11	1		T44	1		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T193	1		T231	7		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T39	13		T190	1		T293	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T47	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	17		T138	12		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T47	19		T135	4		T141	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	7		T46	13		T197	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	11		T8	6		T17	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T210	13		T218	22		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	10		T49	4		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	12		T12	5		T45	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	9		T49	13		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	20		T33	11		T290	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	37		T27	2		T190	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T227	3		T86	6		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	10		T13	13		T138	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T35	11		T159	20		T234	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T161	9		T135	17		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T158	7		T251	12		T196	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	8		T13	5		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T137	6		T33	15		T208	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T28	23		T217	11		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T152	14		T283	3		T271	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T39	8		T293	15		T326	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T47	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T14	10		T50	1		T33	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T202	12		T327	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T311	1		T328	3		T206	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T135	1		T38	15		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T57	13		T138	13		T217	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T47	27		T141	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	8		T134	1		T57	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	16		T49	7		T17	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T110	1		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	3		T46	1		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	10		T12	3		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T44	6		T194	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	15		T45	1		T33	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	12		T44	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T35	12		T162	7		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T11	1		T13	14		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	9		T193	1		T229	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	10		T161	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T158	1		T193	1		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	6		T161	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T4	1		T9	19		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T2	8		T11	1		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T33	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T202	7		T327	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T328	6		T206	7		T329	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T135	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T57	9		T138	12		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	34		T141	4		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T57	8		T197	11		T254	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	11		T49	4		T17	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	7		T46	13		T210	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T8	6		T46	10		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	12		T12	5		T45	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T194	15		T35	16		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	20		T45	16		T33	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	9		T44	13		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T35	11		T162	6		T226	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	13		T44	24		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T227	3		T202	8		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	10		T161	9		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T158	7		T251	12		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	5		T161	3		T135	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T137	6		T159	20		T234	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	8		T28	23		T39	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36