Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22490

1

T1

193

T2

8

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

4325

1

T2

43

T7

21

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20507

1

T1

193

T2

16

T3

12

auto[1]

6308

1

T2

35

T4

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	370	1			T11	1		T28	11		T33	28
values[0]	24	1			T328	9		T206	15		-	-
values[1]	690	1			T47	61		T135	5		T57	22
values[2]	811	1			T2	27		T14	8		T134	1
values[3]	812	1			T2	8		T8	9		T110	1
values[4]	648	1			T10	22		T11	1		T12	8
values[5]	941	1			T7	21		T8	35		T44	25
values[6]	925	1			T11	1		T13	27		T44	37
values[7]	723	1			T8	20		T10	9		T161	10
values[8]	625	1			T13	11		T161	4		T135	18
values[9]	3028	1			T2	16		T4	1		T9	19
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	544	1			T47	33		T135	5		T57	11
values[1]	793	1			T2	35		T8	9		T14	8
values[2]	892	1			T110	1		T46	11		T49	24
values[3]	732	1			T7	21		T10	22		T11	1
values[4]	913	1			T8	35		T44	25		T47	1
values[5]	855	1			T11	1		T13	27		T44	37
values[6]	2812	1			T4	1		T8	20		T9	19
values[7]	618	1			T2	16		T13	11		T161	4
values[8]	913	1			T11	1		T14	10		T50	1
values[9]	247	1			T193	1		T141	15		T190	1
minimum	17496	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T57	9		T217	11		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	20		T135	5		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	8		T8	7		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	12		T17	21		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T110	1		T49	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T46	11		T49	5		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	13		T12	6		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	10		T11	1		T49	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T8	21		T33	12		T233	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T44	14		T47	1		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T224	1		T227	4		T295	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	1		T13	14		T44	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T4	1		T9	2		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	11		T135	18		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T161	4		T158	8		T251	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	9		T13	6		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T50	1		T137	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T11	1		T44	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T193	1		T231	1		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T141	15		T190	1		T165	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17169	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T47	16		T141	5		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T57	2		T217	2		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T47	13		T37	8		T190	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	2		T14	7		T264	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	15		T17	23		T189	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	12		T218	21		T61	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T49	6		T35	2		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	9		T12	2		T14	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	11		T49	13		T57	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	14		T33	15		T330	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T44	11		T27	4		T190	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T227	14		T295	2		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	13		T44	12		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T9	17		T10	8		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	9		T39	4		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T230	13		T151	13		T196	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	7		T13	5		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	9		T137	14		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T137	11		T194	1		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T231	6		T152	11		T93	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T293	7		T203	16		T331	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T48	2		T57	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T47	12		T38	14		T267	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T33	16		T226	1		T231	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T28	11		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T206	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T328	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	10		T138	13		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	36		T135	5		T141	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	1		T134	1		T46	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	12		T17	21		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	8		T8	7		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T46	11		T49	5		T163	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	13		T12	6		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T194	16		T35	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	21		T45	17		T33	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	10		T44	14		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T224	1		T295	1		T226	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	1		T13	14		T44	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T161	10		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	11		T147	1		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T161	4		T158	8		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	6		T135	18		T217	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1475	1			T4	1		T9	2		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	9		T44	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T33	12		T226	1		T231	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T140	9		T293	7		T326	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T206	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T328	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T57	12		T138	12		T217	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	25		T38	14		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	7		T57	2		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	15		T17	23		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T8	2		T218	21		T61	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T49	6		T225	13		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	9		T12	2		T14	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T194	17		T35	14		T144	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	14		T33	15		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	11		T44	11		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T295	2		T226	7		T215	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	13		T44	12		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	8		T35	11		T162	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	9		T39	4		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T230	13		T151	13		T326	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	5		T217	9		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T9	17		T14	9		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	7		T137	11		T194	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T57	3		T217	3		T148	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	14		T135	1		T37	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	1		T8	3		T14	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	16		T17	26		T189	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T110	1		T49	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T46	1		T49	7		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	10		T12	3		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	12		T11	1		T49	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	15		T33	16		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T44	12		T47	1		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T224	1		T227	15		T295	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	1		T13	14		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T4	1		T9	19		T10	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	10		T135	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T161	1		T158	1		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	8		T13	6		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	10		T50	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T11	1		T44	1		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T193	1		T231	7		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T141	1		T190	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17283	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T47	13		T141	1		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T57	8		T217	10		T196	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T47	19		T135	4		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	7		T8	6		T46	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	11		T17	18		T227	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T210	13		T218	22		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T46	10		T49	4		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	12		T12	5		T45	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	9		T49	13		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	20		T33	11		T233	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	13		T27	2		T163	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T227	3		T86	6		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	13		T44	24		T138	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T161	9		T35	11		T159	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	10		T135	17		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T161	3		T158	7		T251	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	8		T13	5		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T137	6		T33	15		T208	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	23		T39	8		T202	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T152	14		T93	15		T283	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T141	14		T165	3		T293	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T57	9		T138	12		T150	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T47	15		T141	4		T197	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T33	13		T226	2		T231	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	1		T28	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T206	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T328	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T57	13		T138	13		T217	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T47	27		T135	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	8		T134	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	16		T17	26		T37	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T8	3		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T46	1		T49	7		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	10		T12	3		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T194	18		T35	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	15		T45	1		T33	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	12		T44	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T224	1		T295	3		T226	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T11	1		T13	14		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	9		T161	1		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	10		T147	1		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T161	1		T158	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	6		T135	1		T217	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T4	1		T9	19		T14	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T2	8		T44	1		T137	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T33	15		T222	9		T283	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	10		T141	14		T165	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T206	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T328	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T57	9		T138	12		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	34		T135	4		T141	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	13		T57	8		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	11		T17	18		T190	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	7		T8	6		T210	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T46	10		T49	4		T163	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	12		T12	5		T45	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T194	15		T35	16		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	20		T45	16		T33	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	9		T44	13		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T226	9		T215	7		T214	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	13		T44	24		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T161	9		T35	11		T162	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	10		T148	11		T218	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T161	3		T158	7		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	5		T135	17		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T137	6		T159	20		T234	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	8		T28	13		T39	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36