Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	15		T11	1		T12	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	3		T11	1		T13	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T161	1		T137	12		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	8		T50	1		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T138	16		T217	3		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T193	1		T165	1		T220	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T35	3		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	16		T44	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	1		T33	13		T37	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	7		T45	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T44	13		T135	1		T194	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T2	9		T10	10		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T4	1		T9	19		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T47	13		T57	13		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	9		T134	1		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	6		T191	1		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	12		T47	1		T194	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	10		T49	7		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T49	14		T146	1		T218	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T237	1		T238	6		T93	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	2		T239	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	20		T12	5		T17	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	6		T13	13		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T161	9		T27	2		T40	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T45	6		T135	17		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T138	17		T217	10		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T165	18		T220	14		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	6		T217	11		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T46	13		T47	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T133	11		T33	15		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	16		T161	3		T33	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T44	24		T135	4		T194	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	15		T10	12		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T44	13		T159	20		T234	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T47	15		T57	9		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T163	7		T219	11		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T13	5		T41	1		T213	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	9		T28	10		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	10		T49	4		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T49	13		T218	10		T208	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T237	11		T93	15		T169	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T239	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T194	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T236	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	15		T12	3		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T110	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T49	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T8	3		T13	14		T14	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T137	12		T40	6		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T163	1		T139	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T138	16		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	16		T44	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T133	1		T33	13		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	7		T45	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	12		T135	1		T37	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	8		T10	10		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T44	13		T194	18		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T57	13		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T4	1		T9	19		T10	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	10		T13	6		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T7	12		T134	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T49	7		T193	1		T145	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	20		T12	5		T17	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	10		T210	13		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T161	9		T27	2		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	6		T13	13		T45	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	5		T197	8		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T163	9		T139	10		T165	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T138	17		T217	11		T141	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	11		T46	13		T47	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T133	11		T33	15		T35	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	16		T161	3		T57	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	13		T135	4		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	8		T10	12		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T44	24		T194	15		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	7		T57	9		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T159	20		T163	7		T234	33
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	10		T13	5		T47	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T7	9		T49	13		T28	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	4		T148	11		T86	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36