Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23084

1

T1

193

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3731

1

T2

16

T8

55

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20749

1

T1

193

T2

8

T3

12

auto[1]

6066

1

T2

43

T4

1

T8

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T20	1		T151	6		-	-
values[0]	58	1			T242	9		T152	26		T245	1
values[1]	837	1			T10	9		T13	38		T14	8
values[2]	737	1			T35	23		T147	1		T210	14
values[3]	805	1			T11	2		T44	6		T161	10
values[4]	639	1			T2	16		T8	35		T134	1
values[5]	2795	1			T4	1		T9	19		T136	1
values[6]	693	1			T2	35		T7	21		T8	9
values[7]	784	1			T12	8		T49	27		T17	44
values[8]	800	1			T50	1		T47	34		T57	20
values[9]	1442	1			T8	20		T10	22		T11	1
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1106	1			T10	9		T13	38		T14	8
values[1]	749	1			T33	28		T35	23		T210	14
values[2]	767	1			T2	16		T11	1		T134	1
values[3]	2805	1			T4	1		T8	35		T9	19
values[4]	647	1			T2	8		T7	21		T46	25
values[5]	601	1			T2	27		T8	9		T45	7
values[6]	966	1			T12	8		T47	33		T49	27
values[7]	633	1			T11	1		T50	1		T47	1
values[8]	1033	1			T8	20		T10	22		T44	25
values[9]	283	1			T14	17		T44	37		T138	33
minimum	17225	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T10	1		T13	20		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T135	18		T137	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T35	12		T210	14		T163	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T33	16		T145	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T161	10		T57	9		T163	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	9		T11	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T4	1		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	21		T229	1		T218	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	8		T7	10		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	14		T47	16		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	12		T8	7		T45	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T148	12		T19	1		T81	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T47	20		T49	14		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	6		T17	21		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T50	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T57	6		T28	14		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T10	13		T44	14		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T8	11		T49	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T14	2		T44	25		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T138	18		T40	8		T244	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17099	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	8		T13	18		T14	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T137	11		T39	11		T217	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	11		T217	9		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	12		T145	9		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T57	2		T39	4		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	7		T44	5		T162	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T9	17		T216	26		T248	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	14		T229	6		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	11		T49	6		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	12		T27	4		T191	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	15		T8	2		T57	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T148	10		T81	2		T86	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	13		T49	13		T35	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T12	2		T17	23		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	14		T35	2		T37	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T57	14		T198	12		T209	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T10	9		T44	11		T33	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	9		T49	12		T194	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T14	15		T44	12		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T138	15		T40	3		T249	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T48	2		T17	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T20	1		T151	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T152	15		T250	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T242	1		T245	1		T183	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	1		T13	20		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	18		T137	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T35	12		T147	1		T210	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T139	11		T217	1		T197	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T161	10		T57	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	1		T44	1		T135	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T193	1		T171	1		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	9		T8	21		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T4	1		T9	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	14		T27	4		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	20		T7	10		T8	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	16		T191	1		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	14		T232	16		T225	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	6		T17	21		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T50	1		T47	21		T35	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T57	6		T28	14		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T10	13		T11	1		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T8	11		T49	1		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T151	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T152	11		T250	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T242	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	8		T13	18		T14	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	11		T39	11		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T35	11		T246	11		T218	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T217	13		T177	7		T150	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	2		T217	9		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T44	5		T33	12		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T39	4		T209	1		T196	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	7		T8	14		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T9	17		T49	6		T216	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T27	4		T221	12		T230	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	15		T7	11		T8	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	12		T191	5		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	13		T225	13		T38	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	2		T17	23		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	13		T35	14		T37	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T57	14		T202	11		T198	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T10	9		T14	15		T44	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	9		T49	12		T194	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T10	9		T13	20		T14	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T135	1		T137	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T35	12		T210	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	13		T145	10		T217	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T161	1		T57	3		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	8		T11	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T4	1		T9	19		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	15		T229	7		T218	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T7	12		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	1		T47	13		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	16		T8	3		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T148	11		T19	1		T81	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	14		T49	14		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T12	3		T17	26		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T50	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T57	15		T28	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T10	10		T44	12		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	10		T49	13		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	17		T44	13		T189	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T138	16		T40	6		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17225	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	18		T161	3		T141	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	17		T139	10		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T35	11		T210	13		T163	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	15		T197	11		T251	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T161	9		T57	8		T163	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	8		T135	4		T158	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T45	16		T159	20		T234	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	20		T218	7		T86	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	7		T7	9		T46	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	13		T47	15		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	11		T8	6		T45	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T148	11		T81	7		T86	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T47	19		T49	13		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	5		T17	18		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T137	6		T35	6		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T57	5		T28	13		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	12		T44	13		T33	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	10		T133	11		T194	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T44	24		T252	13		T206	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T138	17		T40	5		T244	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T20	1		T151	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T152	12		T250	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	9		T245	1		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T10	9		T13	20		T14	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T135	1		T137	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T35	12		T147	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T139	1		T217	14		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T11	1		T161	1		T57	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T44	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T193	1		T171	1		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	8		T8	15		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T4	1		T9	19		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T27	6		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	17		T7	12		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	13		T191	6		T148	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	14		T232	1		T225	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	3		T17	26		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T50	1		T47	15		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T57	15		T28	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	449	1			T10	10		T11	1		T14	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T8	10		T49	13		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T152	14		T250	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T183	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	18		T161	3		T141	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	17		T39	8		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	11		T210	13		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T139	10		T197	11		T251	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	9		T57	8		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	4		T33	15		T202	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T196	13		T93	15		T253	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	8		T8	20		T158	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T45	16		T46	10		T49	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	13		T27	2		T254	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	18		T7	9		T8	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	15		T148	11		T208	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	13		T232	15		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	5		T17	18		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	19		T35	16		T213	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T57	5		T28	13		T202	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T10	12		T44	37		T137	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T8	10		T133	11		T194	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36