Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23206

1

T1

193

T2

51

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3609

1

T8

35

T11

1

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20523

1

T1

193

T2

35

T3

12

auto[1]

6292

1

T2

16

T4

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T110	1		T244	11		T255	5
values[0]	106	1			T229	7		T247	13		T256	14
values[1]	787	1			T7	21		T11	1		T13	11
values[2]	2749	1			T2	8		T4	1		T9	19
values[3]	793	1			T2	16		T8	9		T47	33
values[4]	555	1			T14	7		T134	1		T49	13
values[5]	878	1			T8	35		T46	11		T161	10
values[6]	742	1			T14	10		T44	1		T171	1
values[7]	799	1			T11	1		T13	27		T47	28
values[8]	847	1			T2	27		T8	20		T10	31
values[9]	1324	1			T11	1		T50	1		T44	62
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	965	1			T7	21		T11	1		T13	11
values[1]	2898	1			T2	24		T4	1		T9	19
values[2]	776	1			T8	9		T14	15		T134	1
values[3]	585	1			T46	11		T49	13		T161	10
values[4]	933	1			T8	35		T14	10		T28	14
values[5]	639	1			T44	1		T193	1		T171	1
values[6]	813	1			T10	9		T11	1		T13	27
values[7]	786	1			T8	20		T10	22		T12	8
values[8]	1024	1			T2	27		T11	1		T44	37
values[9]	162	1			T50	1		T135	5		T147	1
minimum	17234	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	10		T11	1		T13	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T44	1		T46	14		T135	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T2	17		T4	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T35	12		T146	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	7		T47	20		T57	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	2		T134	1		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	11		T49	1		T17	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T161	10		T137	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T28	14		T33	16		T184	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	21		T14	1		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	1		T193	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T171	1		T175	1		T218	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	16		T158	8		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	11		T10	13		T44	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	6		T47	1		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T2	12		T44	25		T45	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	1		T155	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T50	1		T147	1		T214	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T135	5		T210	14		T165	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	11		T13	5		T57	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T44	5		T194	18		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T2	7		T9	17		T216	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	11		T229	7		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	2		T47	13		T57	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	13		T49	6		T39	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	12		T17	23		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T137	14		T138	15		T257	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T33	12		T227	9		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	14		T14	9		T35	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T191	5		T218	7		T198	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T218	24		T61	2		T258	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	8		T13	13		T57	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	12		T189	6		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	9		T10	9		T44	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	2		T39	11		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	15		T44	12		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	8		T138	12		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T235	7		T259	8		T182	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T152	16		T260	2		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T48	2		T17	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T110	1		T244	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T229	1		T247	1		T168	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T256	1		T262	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	10		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T44	1		T46	14		T135	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T2	8		T4	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T35	12		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	9		T8	7		T47	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	5		T39	2		T197	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	1		T137	1		T33	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T134	1		T137	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T46	11		T17	21		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	21		T161	10		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	1		T140	1		T218	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T171	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	1		T13	14		T57	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	16		T158	8		T40	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	12		T8	11		T10	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	6		T133	12		T39	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T50	1		T44	39		T45	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T11	1		T47	1		T135	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T255	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T229	6		T247	12		T168	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T256	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	11		T13	5		T57	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	5		T194	18		T213	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T9	17		T57	2		T216	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	7		T35	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	7		T8	2		T47	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T49	6		T39	4		T229	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	12		T137	11		T33	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	6		T137	14		T225	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	23		T33	12		T217	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	14		T35	12		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T140	9		T218	7		T198	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	9		T218	24		T61	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	13		T57	14		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T47	12		T40	3		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	15		T8	9		T10	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	2		T39	11		T217	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T44	23		T49	13		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T37	8		T138	12		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	12		T11	1		T13	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T44	6		T46	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T2	9		T4	1		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	12		T146	1		T229	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	3		T47	14		T57	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	15		T134	1		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	1		T49	13		T17	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	1		T137	15		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T28	1		T33	13		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	15		T14	10		T35	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T44	1		T193	1		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T171	1		T175	1		T218	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	9		T11	1		T13	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	13		T158	1		T189	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	10		T10	10		T44	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	3		T47	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	16		T44	13		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	1		T155	1		T37	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T50	1		T147	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T135	1		T210	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	9		T13	5		T161	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	13		T135	17		T194	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T2	15		T159	20		T234	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	11		T165	3		T208	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	6		T47	19		T57	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	4		T139	10		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	10		T17	18		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T161	9		T137	6		T138	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T28	13		T33	15		T184	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	20		T35	10		T202	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T218	7		T208	2		T264	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T218	25		T254	22		T258	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	13		T57	5		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	15		T158	7		T202	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	10		T10	12		T44	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	5		T133	11		T39	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	11		T44	24		T45	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T138	12		T163	9		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T214	5		T235	2		T259	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T135	4		T210	13		T165	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T250	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T110	1		T244	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T255	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T229	7		T247	13		T168	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T256	14		T262	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	12		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	6		T46	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T4	1		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	8		T35	12		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	8		T8	3		T47	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T49	7		T39	6		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	13		T137	12		T33	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	7		T134	1		T137	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T46	1		T17	26		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	15		T161	1		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T44	1		T140	10		T218	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	10		T171	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	1		T13	14		T57	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	13		T158	1		T40	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	16		T8	10		T10	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	3		T133	1		T39	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T50	1		T44	25		T45	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T11	1		T47	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T244	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T168	16		T265	11		T266	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	9		T13	5		T161	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	13		T135	17		T194	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T2	7		T57	8		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	11		T251	12		T165	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	8		T8	6		T47	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	4		T197	11		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T33	11		T162	6		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T137	6		T139	10		T225	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T46	10		T17	18		T28	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	20		T161	9		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T218	7		T213	10		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T218	25		T254	10		T267	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	13		T57	5		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	15		T158	7		T40	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	11		T8	10		T10	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	5		T133	11		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T44	37		T45	22		T49	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T135	4		T210	13		T138	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36