Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22988

1

T1

193

T3

12

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3827

1

T2

51

T8

29

T10

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20554

1

T1

193

T2

16

T3

12

auto[1]

6261

1

T2

35

T4

1

T8

64

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	269	1			T194	2		T28	11		T146	1
values[0]	2	1			T236	2		-	-		-	-
values[1]	530	1			T8	35		T11	1		T12	8
values[2]	932	1			T8	9		T11	1		T13	27
values[3]	816	1			T137	12		T163	10		T139	11
values[4]	664	1			T2	27		T11	1		T44	1
values[5]	808	1			T14	7		T45	17		T161	4
values[6]	888	1			T2	16		T10	22		T44	37
values[7]	881	1			T2	8		T44	25		T57	22
values[8]	2863	1			T4	1		T9	19		T10	9
values[9]	944	1			T7	21		T8	20		T134	1
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	684	1			T8	44		T11	1		T12	8
values[1]	890	1			T14	8		T50	1		T45	7
values[2]	672	1			T193	1		T138	33		T217	13
values[3]	789	1			T2	27		T11	1		T44	1
values[4]	727	1			T14	7		T45	17		T161	4
values[5]	1004	1			T2	24		T10	22		T44	37
values[6]	3070	1			T4	1		T9	19		T136	1
values[7]	530	1			T10	9		T13	11		T134	1
values[8]	962	1			T7	21		T8	20		T47	1
values[9]	131	1			T146	1		T218	21		T242	9
minimum	17356	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	21		T11	1		T12	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	7		T13	14		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T161	10		T137	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	1		T50	1		T45	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T138	18		T217	11		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T193	1		T220	15		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T217	12		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	12		T44	1		T46	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	12		T33	16		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T45	17		T161	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T44	25		T135	5		T194	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	17		T10	13		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T4	1		T9	2		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T47	16		T57	10		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T134	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	6		T157	1		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T7	10		T47	1		T49	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	11		T49	5		T193	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T146	1		T218	11		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T237	12		T93	16		T169	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17131	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T11	1		T46	11		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T8	14		T12	2		T14	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	2		T13	13		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	11		T27	4		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	7		T240	13		T268	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	15		T217	2		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T220	12		T241	2		T213	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T217	9		T221	12		T226	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	15		T47	13		T57	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	12		T37	8		T81	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	6		T57	2		T33	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T44	12		T194	17		T35	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	7		T10	9		T217	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T9	17		T44	11		T216	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T47	12		T57	12		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	8		T44	5		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	5		T41	1		T213	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	11		T49	13		T194	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	9		T49	6		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T218	10		T242	8		T269	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T93	13		T169	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T189	6		T168	2		T239	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T194	1		T28	11		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T86	3		T226	1		T237	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	21		T12	6		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T110	1		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	1		T49	1		T161	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	7		T13	14		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T137	1		T217	11		T197	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T163	10		T139	11		T220	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T138	18		T217	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	12		T44	1		T46	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T133	12		T33	16		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	1		T45	17		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T44	25		T135	5		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	9		T10	13		T158	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T44	14		T194	16		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	8		T57	10		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1523	1			T4	1		T9	2		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	6		T47	16		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T7	10		T134	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	11		T49	5		T193	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T194	1		T242	8		T226	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T86	4		T226	1		T93	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	14		T12	2		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	11		T189	6		T61	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	12		T27	4		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	2		T13	13		T14	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	11		T217	2		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T220	12		T243	14		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T138	15		T217	9		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	15		T47	13		T57	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T33	12		T81	2		T226	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	6		T57	2		T33	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	12		T37	8		T190	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	7		T10	9		T217	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	11		T194	17		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T57	12		T198	12		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T9	17		T10	8		T44	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	5		T47	12		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T7	11		T49	13		T35	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	9		T49	6		T145	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	15		T11	1		T12	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	3		T13	14		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T161	1		T137	12		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	8		T50	1		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T138	16		T217	3		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T193	1		T220	13		T241	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T217	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	16		T44	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T133	1		T33	13		T37	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	7		T45	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T44	13		T135	1		T194	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T2	9		T10	10		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T4	1		T9	19		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T47	13		T57	13		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	9		T134	1		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	6		T157	1		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T7	12		T47	1		T49	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	10		T49	7		T193	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T146	1		T218	11		T242	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T237	1		T93	14		T169	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17249	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T11	1		T46	1		T189	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	20		T12	5		T17	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	6		T13	13		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T161	9		T27	2		T40	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	6		T135	17		T163	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T138	17		T217	10		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T220	14		T228	2		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T217	11		T141	14		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	11		T46	13		T47	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T133	11		T33	15		T81	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	16		T161	3		T57	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T44	24		T135	4		T194	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	15		T10	12		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T44	13		T159	20		T234	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T47	15		T57	9		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T163	7		T219	11		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T13	5		T41	1		T213	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T7	9		T49	13		T28	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	10		T49	4		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T218	10		T269	15		T270	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T237	11		T93	15		T169	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T168	16		T271	2		T272	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T46	10		T179	2		T273	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T194	2		T28	1		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T86	5		T226	2		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	15		T12	3		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T110	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T49	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T8	3		T13	14		T14	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T137	12		T217	3		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T163	1		T139	1		T220	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T138	16		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	16		T44	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T133	1		T33	13		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	7		T45	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	13		T135	1		T37	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	8		T10	10		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T44	12		T194	18		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	1		T57	13		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T4	1		T9	19		T10	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	6		T47	13		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T7	12		T134	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	10		T49	7		T193	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T28	10		T153	9		T274	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T86	2		T237	11		T93	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	20		T12	5		T17	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	10		T210	13		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T161	9		T27	2		T40	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	6		T13	13		T45	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T217	10		T197	8		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T163	9		T139	10		T220	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	17		T217	11		T141	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	11		T46	13		T47	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T133	11		T33	15		T81	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T45	16		T161	3		T57	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	24		T135	4		T190	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	8		T10	12		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	13		T194	15		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	7		T57	9		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T159	20		T163	7		T234	33
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	5		T47	15		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T7	9		T49	13		T35	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	10		T49	4		T41	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36