Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22845

1

T1

193

T3

12

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3970

1

T2

51

T7

21

T8

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20458

1

T1

193

T2

24

T3

12

auto[1]

6357

1

T2

27

T4

1

T8

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T171	1		T265	9		T275	9
values[0]	74	1			T227	20		T142	1		T195	1
values[1]	668	1			T14	7		T46	14		T135	5
values[2]	657	1			T2	8		T11	1		T45	7
values[3]	1001	1			T10	22		T11	2		T14	10
values[4]	2792	1			T4	1		T9	19		T12	8
values[5]	680	1			T7	21		T8	20		T10	9
values[6]	678	1			T49	27		T135	18		T137	12
values[7]	640	1			T8	9		T50	1		T44	38
values[8]	983	1			T2	27		T8	35		T44	6
values[9]	1405	1			T2	16		T44	25		T46	11
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	772	1			T11	1		T14	7		T46	14
values[1]	788	1			T2	8		T10	22		T45	7
values[2]	978	1			T11	2		T13	27		T14	10
values[3]	2758	1			T4	1		T7	21		T9	19
values[4]	781	1			T8	20		T10	9		T12	8
values[5]	636	1			T44	1		T135	18		T194	33
values[6]	793	1			T8	44		T50	1		T44	43
values[7]	783	1			T2	27		T57	20		T210	14
values[8]	1008	1			T44	25		T46	11		T47	61
values[9]	290	1			T2	16		T133	12		T146	1
minimum	17228	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	1		T161	4		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	1		T46	14		T135	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T189	1		T197	9		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	8		T10	13		T45	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T11	1		T194	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	1		T13	14		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T4	1		T9	2		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	10		T47	1		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	11		T10	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	6		T13	6		T45	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	11		T157	1		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	1		T135	18		T194	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	26		T158	8		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	28		T50	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T57	6		T217	1		T190	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	12		T210	14		T163	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T44	14		T46	11		T47	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T47	16		T57	9		T137	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T133	12		T242	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	9		T146	1		T225	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T204	3		T238	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	6		T190	14		T198	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T191	5		T227	9		T81	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T189	6		T148	10		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	9		T17	23		T33	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T194	1		T138	15		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	13		T14	9		T35	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T9	17		T14	7		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	11		T144	11		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	9		T10	8		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	2		T13	5		T27	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T35	12		T86	5		T226	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T194	17		T217	2		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T44	17		T218	10		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	16		T33	15		T37	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T57	14		T217	13		T190	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	15		T39	4		T40	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T44	11		T47	13		T49	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T47	12		T57	2		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T242	8		T238	12		T276	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T2	7		T225	13		T220	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T204	1		T238	5		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T171	1		T265	9		T275	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T277	19		T278	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T227	11		T142	1		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	1		T147	1		T190	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	14		T135	5		T28	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T161	4		T197	9		T218	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	8		T11	1		T45	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T11	1		T194	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	13		T11	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T4	1		T9	2		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	6		T13	14		T35	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	11		T10	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	10		T13	6		T45	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	14		T137	1		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	18		T194	16		T197	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	25		T175	1		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	7		T50	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T44	1		T57	6		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	12		T8	21		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T44	14		T46	11		T47	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T2	9		T47	16		T57	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T227	9		T168	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	6		T190	14		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	12		T191	5		T81	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T218	14		T151	28		T196	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	23		T33	12		T150	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T194	1		T138	15		T39	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	9		T14	9		T35	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T9	17		T49	12		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	2		T13	13		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	9		T10	8		T14	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	11		T13	5		T27	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	13		T137	11		T35	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T194	17		T221	9		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T44	12		T246	11		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	2		T33	15		T37	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	5		T57	14		T247	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	15		T8	14		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T44	11		T47	13		T49	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T2	7		T47	12		T57	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	7		T161	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T46	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T189	7		T197	1		T148	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	1		T10	10		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	1		T194	2		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	1		T13	14		T14	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T4	1		T9	19		T14	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	12		T47	1		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	10		T10	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	3		T13	6		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	13		T157	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T44	1		T135	1		T194	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	19		T158	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	18		T50	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T57	15		T217	14		T190	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	16		T210	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T44	12		T46	1		T47	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T47	13		T57	3		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T133	1		T242	9		T238	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T2	8		T146	1		T225	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T204	3		T238	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T161	3		T190	12		T18	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T46	13		T135	4		T28	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T197	8		T218	15		T208	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	7		T10	12		T45	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T28	10		T138	17		T163	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	13		T161	9		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1106	1			T57	9		T159	20		T234	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	9		T144	7		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	10		T49	13		T141	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	5		T13	5		T45	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	10		T244	10		T232	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	17		T194	15		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	24		T158	7		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	26		T33	11		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T57	5		T190	9		T251	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	11		T210	13		T163	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	13		T46	10		T47	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T47	15		T57	8		T137	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T133	11		T276	3		T279	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T2	8		T225	11		T220	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T204	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T171	1		T265	1		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T277	1		T278	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T227	10		T142	1		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	7		T147	1		T190	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T46	1		T135	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T161	1		T197	1		T218	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T11	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T11	1		T194	2		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	10		T11	1		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T4	1		T9	19		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	3		T13	14		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	10		T10	9		T14	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	12		T13	6		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	14		T137	12		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	1		T194	18		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	13		T175	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	3		T50	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T44	6		T57	15		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	16		T8	15		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T44	12		T46	1		T47	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T2	8		T47	13		T57	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T265	8		T275	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T277	18		T278	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T227	10		T168	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T190	12		T18	3		T165	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	13		T135	4		T28	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T161	3		T197	8		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	7		T45	6		T17	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T28	10		T138	17		T39	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	12		T161	9		T35	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T57	9		T159	20		T163	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	5		T13	13		T35	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	10		T141	14		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	9		T13	5		T45	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	13		T35	10		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	17		T194	15		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	24		T141	2		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	6		T33	11		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	5		T158	7		T233	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	11		T8	20		T137	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T44	13		T46	10		T47	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T2	8		T47	15		T57	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36