CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26815 | 1 | T1 | 193 | T2 | 51 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 22949 | 1 | T1 | 193 | T2 | 16 | T3 | 12 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3866 | 1 | T2 | 35 | T8 | 35 | T10 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20996 | 1 | T1 | 193 | T2 | 8 | T3 | 12 | ||||
auto[1] | 5819 | 1 | T2 | 43 | T4 | 1 | T8 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22520 | 1 | T1 | 193 | T2 | 29 | T3 | 12 | ||||
auto[1] | 4295 | 1 | T2 | 22 | T7 | 11 | T8 | 25 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 238 | 1 | T13 | 27 | T44 | 37 | T161 | 10 | ||||
values[0] | 12 | 1 | T280 | 12 | - | - | - | - | ||||
values[1] | 710 | 1 | T10 | 9 | T11 | 1 | T57 | 11 | ||||
values[2] | 784 | 1 | T8 | 9 | T10 | 22 | T14 | 18 | ||||
values[3] | 703 | 1 | T2 | 16 | T110 | 1 | T49 | 11 | ||||
values[4] | 862 | 1 | T44 | 1 | T161 | 4 | T138 | 33 | ||||
values[5] | 2955 | 1 | T4 | 1 | T9 | 19 | T11 | 1 | ||||
values[6] | 834 | 1 | T2 | 27 | T44 | 6 | T46 | 11 | ||||
values[7] | 738 | 1 | T11 | 1 | T12 | 8 | T134 | 1 | ||||
values[8] | 510 | 1 | T2 | 8 | T14 | 7 | T33 | 28 | ||||
values[9] | 1251 | 1 | T7 | 21 | T8 | 55 | T13 | 11 | ||||
minimum | 17218 | 1 | T1 | 193 | T3 | 12 | T5 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 837 | 1 | T11 | 1 | T14 | 8 | T47 | 1 | ||||
values[1] | 767 | 1 | T8 | 9 | T10 | 22 | T14 | 10 | ||||
values[2] | 807 | 1 | T2 | 16 | T44 | 1 | T110 | 1 | ||||
values[3] | 2810 | 1 | T4 | 1 | T9 | 19 | T136 | 1 | ||||
values[4] | 861 | 1 | T11 | 1 | T44 | 6 | T45 | 7 | ||||
values[5] | 847 | 1 | T2 | 27 | T11 | 1 | T12 | 8 | ||||
values[6] | 672 | 1 | T134 | 1 | T50 | 1 | T57 | 22 | ||||
values[7] | 539 | 1 | T2 | 8 | T7 | 21 | T14 | 7 | ||||
values[8] | 1197 | 1 | T8 | 35 | T13 | 38 | T44 | 25 | ||||
values[9] | 161 | 1 | T8 | 20 | T44 | 37 | T142 | 1 | ||||
minimum | 17317 | 1 | T1 | 193 | T3 | 12 | T5 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22467 | 1 | T1 | 193 | T2 | 25 | T3 | 12 | ||||
auto[1] | 4348 | 1 | T2 | 26 | T7 | 9 | T8 | 36 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 243 | 1 | T14 | 1 | T57 | 6 | T137 | 7 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T11 | 1 | T47 | 1 | T49 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 163 | 1 | T8 | 7 | T10 | 13 | T14 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 254 | 1 | T47 | 20 | T137 | 1 | T147 | 2 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 190 | 1 | T2 | 9 | T49 | 5 | T163 | 10 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 301 | 1 | T44 | 1 | T110 | 1 | T35 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1502 | 1 | T4 | 1 | T9 | 2 | T136 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T161 | 4 | T18 | 5 | T61 | 5 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 258 | 1 | T11 | 1 | T44 | 1 | T45 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 239 | 1 | T47 | 16 | T135 | 5 | T210 | 14 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 232 | 1 | T12 | 6 | T46 | 25 | T157 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 213 | 1 | T2 | 12 | T11 | 1 | T28 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T50 | 1 | T57 | 10 | T171 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T134 | 1 | T145 | 1 | T39 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 106 | 1 | T7 | 10 | T155 | 1 | T175 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 181 | 1 | T2 | 8 | T14 | 1 | T45 | 17 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 369 | 1 | T13 | 20 | T161 | 10 | T33 | 12 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 280 | 1 | T8 | 21 | T44 | 14 | T190 | 10 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 91 | 1 | T8 | 11 | T44 | 25 | T142 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 16 | 1 | T208 | 3 | T281 | 11 | T282 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17117 | 1 | T1 | 193 | T3 | 12 | T5 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 37 | 1 | T10 | 1 | T283 | 4 | T284 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T14 | 7 | T57 | 14 | T137 | 14 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 216 | 1 | T49 | 12 | T27 | 4 | T138 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 133 | 1 | T8 | 2 | T10 | 9 | T14 | 9 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 217 | 1 | T47 | 13 | T137 | 11 | T229 | 7 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 124 | 1 | T2 | 7 | T49 | 6 | T40 | 3 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T35 | 11 | T144 | 11 | T39 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 981 | 1 | T9 | 17 | T138 | 15 | T216 | 26 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T18 | 2 | T61 | 4 | T215 | 6 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T44 | 5 | T49 | 13 | T194 | 17 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 211 | 1 | T47 | 12 | T217 | 9 | T41 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 191 | 1 | T12 | 2 | T218 | 14 | T220 | 12 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 211 | 1 | T2 | 15 | T35 | 12 | T140 | 9 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T57 | 12 | T190 | 14 | T219 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T145 | 9 | T246 | 11 | T202 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 88 | 1 | T7 | 11 | T191 | 5 | T229 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T14 | 6 | T194 | 1 | T33 | 12 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 301 | 1 | T13 | 18 | T33 | 15 | T39 | 4 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 247 | 1 | T8 | 14 | T44 | 11 | T190 | 8 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 43 | 1 | T8 | 9 | T44 | 12 | T209 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T282 | 11 | - | - | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 133 | 1 | T13 | 1 | T48 | 2 | T17 | 4 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T10 | 8 | T285 | 13 | T286 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 5 | 43 | 89.58 | 5 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [values[0]] | * | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 116 | 1 | T13 | 14 | T44 | 25 | T161 | 10 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 16 | 1 | T287 | 1 | T267 | 10 | T288 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 12 | 1 | T280 | 12 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 198 | 1 | T57 | 9 | T137 | 7 | T193 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T10 | 1 | T11 | 1 | T27 | 4 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 164 | 1 | T8 | 7 | T10 | 13 | T14 | 2 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 234 | 1 | T47 | 21 | T49 | 1 | T137 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T2 | 9 | T49 | 5 | T133 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T110 | 1 | T35 | 12 | T147 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 263 | 1 | T138 | 18 | T244 | 11 | T227 | 4 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 216 | 1 | T44 | 1 | T161 | 4 | T184 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1557 | 1 | T4 | 1 | T9 | 2 | T11 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 212 | 1 | T47 | 16 | T135 | 5 | T217 | 12 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 203 | 1 | T44 | 1 | T46 | 11 | T49 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T2 | 12 | T35 | 11 | T210 | 14 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T12 | 6 | T50 | 1 | T46 | 14 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T11 | 1 | T134 | 1 | T28 | 11 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T155 | 1 | T175 | 1 | T141 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T2 | 8 | T14 | 1 | T33 | 16 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 375 | 1 | T7 | 10 | T8 | 11 | T13 | 6 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 323 | 1 | T8 | 21 | T44 | 14 | T45 | 17 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17098 | 1 | T1 | 193 | T3 | 12 | T5 | 20 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 83 | 1 | T13 | 13 | T44 | 12 | T33 | 15 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 23 | 1 | T267 | 12 | T288 | 11 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T57 | 2 | T137 | 14 | T226 | 7 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T10 | 8 | T27 | 4 | T217 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 143 | 1 | T8 | 2 | T10 | 9 | T14 | 16 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 243 | 1 | T47 | 13 | T49 | 12 | T137 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 77 | 1 | T2 | 7 | T49 | 6 | T40 | 3 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T35 | 11 | T144 | 11 | T39 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 191 | 1 | T138 | 15 | T227 | 14 | T226 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T225 | 13 | T198 | 2 | T18 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1000 | 1 | T9 | 17 | T194 | 17 | T17 | 23 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T47 | 12 | T217 | 9 | T41 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 175 | 1 | T44 | 5 | T49 | 13 | T218 | 21 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T2 | 15 | T35 | 12 | T140 | 9 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T12 | 2 | T57 | 12 | T190 | 14 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T145 | 9 | T246 | 11 | T268 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 86 | 1 | T191 | 5 | T247 | 12 | T86 | 5 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 167 | 1 | T14 | 6 | T33 | 12 | T202 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 292 | 1 | T7 | 11 | T8 | 9 | T13 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 261 | 1 | T8 | 14 | T44 | 11 | T194 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 120 | 1 | T13 | 1 | T48 | 2 | T17 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T14 | 8 | T57 | 15 | T137 | 15 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 264 | 1 | T11 | 1 | T47 | 1 | T49 | 13 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T8 | 3 | T10 | 10 | T14 | 10 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 274 | 1 | T47 | 14 | T137 | 12 | T147 | 2 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T2 | 8 | T49 | 7 | T163 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 237 | 1 | T44 | 1 | T110 | 1 | T35 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1310 | 1 | T4 | 1 | T9 | 19 | T136 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T161 | 1 | T18 | 4 | T61 | 5 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 210 | 1 | T11 | 1 | T44 | 6 | T45 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 255 | 1 | T47 | 13 | T135 | 1 | T210 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 232 | 1 | T12 | 3 | T46 | 2 | T157 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 249 | 1 | T2 | 16 | T11 | 1 | T28 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 213 | 1 | T50 | 1 | T57 | 13 | T171 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 178 | 1 | T134 | 1 | T145 | 10 | T39 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T7 | 12 | T155 | 1 | T175 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 194 | 1 | T2 | 1 | T14 | 7 | T45 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 370 | 1 | T13 | 20 | T161 | 1 | T33 | 16 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T8 | 15 | T44 | 12 | T190 | 9 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 55 | 1 | T8 | 10 | T44 | 13 | T142 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 15 | 1 | T208 | 1 | T281 | 1 | T282 | 12 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17239 | 1 | T1 | 193 | T3 | 12 | T5 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 41 | 1 | T10 | 9 | T283 | 1 | T284 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T57 | 5 | T137 | 6 | T197 | 11 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T27 | 2 | T138 | 12 | T141 | 14 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 126 | 1 | T8 | 6 | T10 | 12 | T135 | 17 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 197 | 1 | T47 | 19 | T139 | 10 | T232 | 15 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T2 | 8 | T49 | 4 | T163 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 256 | 1 | T35 | 11 | T144 | 7 | T39 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1173 | 1 | T159 | 20 | T138 | 17 | T234 | 33 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T161 | 3 | T18 | 3 | T61 | 4 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 201 | 1 | T45 | 6 | T49 | 13 | T194 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T47 | 15 | T135 | 4 | T210 | 13 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 191 | 1 | T12 | 5 | T46 | 23 | T197 | 8 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T2 | 11 | T28 | 10 | T35 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T57 | 9 | T190 | 12 | T219 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 121 | 1 | T202 | 7 | T289 | 6 | T290 | 7 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 80 | 1 | T7 | 9 | T141 | 2 | T86 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 151 | 1 | T2 | 7 | T45 | 16 | T33 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 300 | 1 | T13 | 18 | T161 | 9 | T33 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 236 | 1 | T8 | 20 | T44 | 13 | T190 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 79 | 1 | T8 | 10 | T44 | 24 | T208 | 14 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 12 | 1 | T208 | 2 | T281 | 10 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T280 | 11 | - | - | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 26 | 1 | T283 | 3 | T285 | 6 | T291 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 5 | 43 | 89.58 | 5 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 99 | 1 | T13 | 14 | T44 | 13 | T161 | 1 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T287 | 1 | T267 | 13 | T288 | 12 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 1 | 1 | T280 | 1 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 173 | 1 | T57 | 3 | T137 | 15 | T193 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 215 | 1 | T10 | 9 | T11 | 1 | T27 | 6 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 183 | 1 | T8 | 3 | T10 | 10 | T14 | 18 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 300 | 1 | T47 | 15 | T49 | 13 | T137 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 106 | 1 | T2 | 8 | T49 | 7 | T133 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T110 | 1 | T35 | 12 | T147 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 232 | 1 | T138 | 16 | T244 | 1 | T227 | 15 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 232 | 1 | T44 | 1 | T161 | 1 | T184 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1347 | 1 | T4 | 1 | T9 | 19 | T11 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 228 | 1 | T47 | 13 | T135 | 1 | T217 | 10 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 214 | 1 | T44 | 6 | T46 | 1 | T49 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 267 | 1 | T2 | 16 | T35 | 13 | T210 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 224 | 1 | T12 | 3 | T50 | 1 | T46 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T11 | 1 | T134 | 1 | T28 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 113 | 1 | T155 | 1 | T175 | 1 | T141 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 196 | 1 | T2 | 1 | T14 | 7 | T33 | 13 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 364 | 1 | T7 | 12 | T8 | 10 | T13 | 6 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 312 | 1 | T8 | 15 | T44 | 12 | T45 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17218 | 1 | T1 | 193 | T3 | 12 | T5 | 20 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 100 | 1 | T13 | 13 | T44 | 24 | T161 | 9 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T267 | 9 | T292 | 2 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T280 | 11 | - | - | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T57 | 8 | T137 | 6 | T251 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T27 | 2 | T141 | 14 | T162 | 6 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 124 | 1 | T8 | 6 | T10 | 12 | T135 | 17 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T47 | 19 | T138 | 12 | T227 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 122 | 1 | T2 | 8 | T49 | 4 | T133 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 244 | 1 | T35 | 11 | T144 | 7 | T139 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T138 | 17 | T244 | 10 | T227 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T161 | 3 | T184 | 10 | T225 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1210 | 1 | T45 | 6 | T194 | 15 | T17 | 18 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 170 | 1 | T47 | 15 | T135 | 4 | T217 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 164 | 1 | T46 | 10 | T49 | 13 | T218 | 22 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T2 | 11 | T35 | 10 | T210 | 13 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 185 | 1 | T12 | 5 | T46 | 13 | T57 | 9 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T28 | 10 | T158 | 7 | T289 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 78 | 1 | T141 | 2 | T86 | 6 | T293 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T2 | 7 | T33 | 15 | T202 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 303 | 1 | T7 | 9 | T8 | 10 | T13 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 272 | 1 | T8 | 20 | T44 | 13 | T45 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 22467 | 1 | T1 | 193 | T2 | 25 | T3 | 12 | ||||
auto[1] | auto[0] | 4348 | 1 | T2 | 26 | T7 | 9 | T8 | 36 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |