Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22888

1

T1

193

T3

12

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3927

1

T2

51

T7

21

T8

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20426

1

T1

193

T2

24

T3

12

auto[1]

6389

1

T2

27

T4

1

T8

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	226	1			T133	12		T57	11		T220	27
values[0]	3	1			T294	3		-	-		-	-
values[1]	707	1			T14	7		T46	14		T135	5
values[2]	696	1			T2	8		T11	1		T45	7
values[3]	949	1			T10	22		T11	2		T14	10
values[4]	2882	1			T4	1		T9	19		T12	8
values[5]	638	1			T7	21		T8	20		T10	9
values[6]	705	1			T44	1		T49	27		T137	12
values[7]	650	1			T8	9		T50	1		T44	43
values[8]	917	1			T2	27		T8	35		T110	1
values[9]	1224	1			T2	16		T44	25		T46	11
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	524	1			T11	1		T14	7		T46	14
values[1]	722	1			T2	8		T10	22		T17	44
values[2]	1040	1			T11	2		T13	27		T14	10
values[3]	2763	1			T4	1		T7	21		T9	19
values[4]	780	1			T8	20		T10	9		T13	11
values[5]	594	1			T44	1		T135	18		T194	33
values[6]	772	1			T8	44		T50	1		T44	43
values[7]	858	1			T2	27		T57	20		T33	27
values[8]	1105	1			T2	16		T44	25		T46	11
values[9]	154	1			T133	12		T225	25		T220	27
minimum	17503	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	1		T161	4		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	1		T46	14		T135	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T189	1		T197	9		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	8		T10	13		T17	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T11	1		T194	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	1		T13	14		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T4	1		T9	2		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	10		T12	6		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	11		T10	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	6		T45	17		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T194	16		T35	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	1		T135	18		T217	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T44	26		T158	8		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	28		T50	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	6		T39	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	12		T33	12		T210	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T44	14		T46	11		T47	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T2	9		T47	16		T57	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T133	12		T238	1		T279	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T225	12		T220	15		T84	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17191	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T171	1		T256	1		T204	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T14	6		T198	2		T18	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T191	5		T227	9		T81	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T189	6		T148	10		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	9		T17	23		T33	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T194	1		T138	15		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	13		T14	9		T35	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T9	17		T14	7		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	11		T12	2		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	9		T10	8		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	5		T27	4		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T194	17		T35	12		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T217	2		T162	6		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	17		T218	10		T295	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	16		T37	8		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T57	14		T217	13		T190	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	15		T33	15		T39	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	11		T47	13		T49	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	7		T47	12		T57	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T238	12		T279	8		T296	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T225	13		T220	12		T297	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T256	13		T204	1		T68	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T133	12		T208	15		T86	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T57	9		T220	15		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T147	1		T190	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	14		T135	5		T28	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T161	4		T197	9		T218	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	8		T11	1		T45	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T11	1		T194	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	13		T11	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T4	1		T9	2		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	6		T13	14		T35	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	11		T10	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	10		T13	6		T45	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T49	14		T137	1		T194	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T217	11		T197	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	26		T158	8		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	7		T50	1		T135	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T57	6		T39	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	12		T8	21		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T44	14		T46	11		T47	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	9		T47	16		T137	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T86	4		T298	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T57	2		T220	12		T297	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T294	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	6		T190	14		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	12		T191	5		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T218	14		T151	28		T196	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	23		T33	12		T227	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T194	1		T138	15		T189	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	9		T14	9		T35	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T9	17		T14	7		T49	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	2		T13	13		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	9		T10	8		T198	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	11		T13	5		T27	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T49	13		T137	11		T194	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T217	2		T221	9		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T44	17		T246	11		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	2		T33	15		T37	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T57	14		T247	12		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	15		T8	14		T39	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T44	11		T47	13		T49	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	7		T47	12		T137	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	7		T161	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T46	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T189	7		T197	1		T148	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T10	10		T17	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	1		T194	2		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	1		T13	14		T14	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T4	1		T9	19		T14	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	12		T12	3		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	10		T10	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	6		T45	1		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T194	18		T35	13		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	1		T135	1		T217	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	19		T158	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	18		T50	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T57	15		T39	1		T217	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	16		T33	16		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T44	12		T46	1		T47	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T2	8		T47	13		T57	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T133	1		T238	13		T279	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T225	14		T220	13		T84	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17307	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T171	1		T256	14		T204	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T161	3		T18	3		T165	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	13		T135	4		T28	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T197	8		T218	15		T208	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	7		T10	12		T17	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	10		T138	17		T163	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	13		T45	6		T161	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T57	9		T159	20		T234	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	9		T12	5		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	10		T49	13		T141	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	5		T45	16		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T194	15		T35	10		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T135	17		T217	10		T197	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	24		T158	7		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	26		T202	8		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T57	5		T190	9		T251	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	11		T33	11		T210	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T44	13		T46	10		T47	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T2	8		T47	15		T57	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T133	11		T279	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T225	11		T220	14		T297	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T190	12		T222	14		T299	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T204	1		T68	4		T168	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T133	1		T208	1		T86	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T57	3		T220	13		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T294	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	7		T147	1		T190	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	1		T135	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	1		T197	1		T218	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T11	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	1		T194	2		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	10		T11	1		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	1		T9	19		T14	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	3		T13	14		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	10		T10	9		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	12		T13	6		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T49	14		T137	12		T194	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	1		T217	3		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T44	19		T158	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	3		T50	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T57	15		T39	1		T247	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	16		T8	15		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T44	12		T46	1		T47	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	8		T47	13		T137	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T133	11		T208	14		T86	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T57	8		T220	14		T297	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T190	12		T18	3		T165	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	13		T135	4		T28	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T161	3		T197	8		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	7		T45	6		T17	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	10		T138	17		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	12		T161	9		T35	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T57	9		T159	20		T163	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	5		T13	13		T35	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	10		T141	14		T177	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	9		T13	5		T45	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	13		T194	15		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T217	10		T197	11		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	24		T158	7		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	6		T135	17		T33	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T57	5		T243	17		T264	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	11		T8	20		T210	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T44	13		T46	10		T47	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	8		T47	15		T137	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36