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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 920
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T793 /workspace/coverage/default/32.adc_ctrl_smoke.3660932203 Jul 27 06:39:14 PM PDT 24 Jul 27 06:39:23 PM PDT 24 5997017591 ps
T794 /workspace/coverage/default/46.adc_ctrl_poweron_counter.3495748803 Jul 27 06:41:54 PM PDT 24 Jul 27 06:41:57 PM PDT 24 4304809587 ps
T306 /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4088503784 Jul 27 06:40:36 PM PDT 24 Jul 27 06:44:55 PM PDT 24 249504236140 ps
T795 /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.944842496 Jul 27 06:36:39 PM PDT 24 Jul 27 06:37:30 PM PDT 24 207086575447 ps
T270 /workspace/coverage/default/40.adc_ctrl_stress_all.1457726234 Jul 27 06:40:57 PM PDT 24 Jul 27 06:44:32 PM PDT 24 334637824699 ps
T111 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1141814257 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:25 PM PDT 24 396729055 ps
T90 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2770120357 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:38 PM PDT 24 395246409 ps
T128 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.575775269 Jul 27 05:16:04 PM PDT 24 Jul 27 05:16:07 PM PDT 24 1188233360 ps
T796 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3124643966 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 347920920 ps
T797 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2399700338 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 389183664 ps
T63 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3506536108 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:25 PM PDT 24 322998594 ps
T58 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.32344864 Jul 27 05:16:30 PM PDT 24 Jul 27 05:16:42 PM PDT 24 8419523299 ps
T798 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3532908066 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:53 PM PDT 24 465781451 ps
T799 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2874912571 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 524962243 ps
T56 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4223965028 Jul 27 05:16:02 PM PDT 24 Jul 27 05:16:05 PM PDT 24 2519917807 ps
T72 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1161672087 Jul 27 05:16:25 PM PDT 24 Jul 27 05:16:28 PM PDT 24 414675535 ps
T800 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.963944301 Jul 27 05:16:26 PM PDT 24 Jul 27 05:16:27 PM PDT 24 449855045 ps
T801 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2090314494 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 513050001 ps
T53 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2703740716 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:44 PM PDT 24 2501170059 ps
T123 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2627796231 Jul 27 05:16:30 PM PDT 24 Jul 27 05:16:31 PM PDT 24 545124159 ps
T802 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4255691160 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 554511272 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1991377102 Jul 27 05:16:06 PM PDT 24 Jul 27 05:18:46 PM PDT 24 49014422945 ps
T55 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1938636040 Jul 27 05:16:29 PM PDT 24 Jul 27 05:16:41 PM PDT 24 4905674381 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2345668568 Jul 27 05:16:06 PM PDT 24 Jul 27 05:16:10 PM PDT 24 1218141858 ps
T803 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.842797810 Jul 27 05:16:50 PM PDT 24 Jul 27 05:16:51 PM PDT 24 524108447 ps
T804 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3338609286 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:49 PM PDT 24 540346500 ps
T113 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1159851251 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 579275619 ps
T69 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2486043861 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:30 PM PDT 24 552178168 ps
T805 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3701384054 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:53 PM PDT 24 406977651 ps
T124 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3184575864 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:42 PM PDT 24 4111708003 ps
T806 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.630947001 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 483081724 ps
T807 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1227610653 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:52 PM PDT 24 419618050 ps
T76 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2879083444 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:40 PM PDT 24 591787618 ps
T808 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.612368265 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 278778658 ps
T809 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2719105075 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 451476663 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2639544867 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:45 PM PDT 24 4478056901 ps
T810 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2766607109 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:50 PM PDT 24 529168740 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1871739441 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:52 PM PDT 24 2063927870 ps
T126 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3294537339 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:30 PM PDT 24 2255500594 ps
T91 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.365451287 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 625491332 ps
T811 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1001204057 Jul 27 05:16:46 PM PDT 24 Jul 27 05:16:48 PM PDT 24 385630339 ps
T73 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4169882319 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:40 PM PDT 24 556793798 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.154362420 Jul 27 05:16:02 PM PDT 24 Jul 27 05:16:05 PM PDT 24 355967180 ps
T71 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2279853532 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 461369915 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1454007433 Jul 27 05:15:59 PM PDT 24 Jul 27 05:16:01 PM PDT 24 371389870 ps
T813 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.294331748 Jul 27 05:16:35 PM PDT 24 Jul 27 05:16:37 PM PDT 24 418623203 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3218708143 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 567412661 ps
T815 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.600626887 Jul 27 05:16:12 PM PDT 24 Jul 27 05:16:14 PM PDT 24 448766737 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4186850250 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:39 PM PDT 24 345303222 ps
T817 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3802281250 Jul 27 05:16:50 PM PDT 24 Jul 27 05:16:52 PM PDT 24 542273620 ps
T60 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3472611756 Jul 27 05:16:06 PM PDT 24 Jul 27 05:16:18 PM PDT 24 4518477753 ps
T818 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2282998090 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:39 PM PDT 24 521365610 ps
T127 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1295169456 Jul 27 05:16:29 PM PDT 24 Jul 27 05:16:35 PM PDT 24 4178208831 ps
T77 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1187684906 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:58 PM PDT 24 8200401424 ps
T819 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2904861411 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:39 PM PDT 24 2326476805 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.927517520 Jul 27 05:16:28 PM PDT 24 Jul 27 05:16:30 PM PDT 24 499557921 ps
T821 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1143201589 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:32 PM PDT 24 2606057914 ps
T822 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2466262416 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 353205109 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.483314316 Jul 27 05:16:12 PM PDT 24 Jul 27 05:16:22 PM PDT 24 3935270081 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3081852694 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:53 PM PDT 24 423711724 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.190813271 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:39 PM PDT 24 1201296987 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.722238574 Jul 27 05:16:00 PM PDT 24 Jul 27 05:16:05 PM PDT 24 803994469 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1886539277 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:24 PM PDT 24 595026543 ps
T825 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2259132893 Jul 27 05:16:15 PM PDT 24 Jul 27 05:16:18 PM PDT 24 752315497 ps
T826 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.964783693 Jul 27 05:16:06 PM PDT 24 Jul 27 05:16:09 PM PDT 24 368201700 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1811412479 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:38 PM PDT 24 528673512 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1892161769 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:25 PM PDT 24 339895294 ps
T829 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.82689790 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:50 PM PDT 24 344717498 ps
T830 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2905478937 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:49 PM PDT 24 503943649 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3199507978 Jul 27 05:16:11 PM PDT 24 Jul 27 05:16:13 PM PDT 24 1078814476 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.905829803 Jul 27 05:16:39 PM PDT 24 Jul 27 05:16:41 PM PDT 24 458910571 ps
T833 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1745863021 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:50 PM PDT 24 411894650 ps
T834 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3780253940 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 506889745 ps
T334 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1140921645 Jul 27 05:16:12 PM PDT 24 Jul 27 05:16:21 PM PDT 24 4385693739 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1710535996 Jul 27 05:16:14 PM PDT 24 Jul 27 05:16:18 PM PDT 24 2421884828 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1966243940 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:39 PM PDT 24 487328780 ps
T332 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4274068766 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:44 PM PDT 24 8016620999 ps
T837 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1686798664 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:53 PM PDT 24 4181840913 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3333880385 Jul 27 05:16:11 PM PDT 24 Jul 27 05:16:14 PM PDT 24 667693289 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1587662947 Jul 27 05:16:52 PM PDT 24 Jul 27 05:16:53 PM PDT 24 520539553 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3030552295 Jul 27 05:16:05 PM PDT 24 Jul 27 05:16:09 PM PDT 24 638564351 ps
T841 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1980152147 Jul 27 05:16:13 PM PDT 24 Jul 27 05:16:16 PM PDT 24 477911763 ps
T115 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2915136787 Jul 27 05:16:25 PM PDT 24 Jul 27 05:16:26 PM PDT 24 459563405 ps
T842 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3227378637 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 377033341 ps
T843 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.33224999 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 392526261 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3514696129 Jul 27 05:16:18 PM PDT 24 Jul 27 05:16:19 PM PDT 24 378016724 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2079747274 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:40 PM PDT 24 515454012 ps
T846 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1742451015 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:54 PM PDT 24 8668518038 ps
T847 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2391104042 Jul 27 05:16:01 PM PDT 24 Jul 27 05:16:03 PM PDT 24 455302167 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1447184516 Jul 27 05:16:06 PM PDT 24 Jul 27 05:16:08 PM PDT 24 353229858 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2340263612 Jul 27 05:16:11 PM PDT 24 Jul 27 05:18:24 PM PDT 24 41466925710 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1627152182 Jul 27 05:16:12 PM PDT 24 Jul 27 05:16:48 PM PDT 24 52576191226 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.354284621 Jul 27 05:16:13 PM PDT 24 Jul 27 05:16:14 PM PDT 24 607606036 ps
T119 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1091453015 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:37 PM PDT 24 305720797 ps
T849 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4078921151 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:24 PM PDT 24 317036890 ps
T850 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.876272112 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 388556141 ps
T851 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3241084595 Jul 27 05:16:41 PM PDT 24 Jul 27 05:16:43 PM PDT 24 864916340 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3490948756 Jul 27 05:16:15 PM PDT 24 Jul 27 05:16:17 PM PDT 24 839925192 ps
T852 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.914306536 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:26 PM PDT 24 512862780 ps
T121 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.912911437 Jul 27 05:16:16 PM PDT 24 Jul 27 05:16:53 PM PDT 24 30987844826 ps
T853 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2165528218 Jul 27 05:16:15 PM PDT 24 Jul 27 05:16:23 PM PDT 24 8713239157 ps
T854 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2456474540 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:40 PM PDT 24 364491240 ps
T855 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3569866543 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:52 PM PDT 24 833136936 ps
T856 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2008576874 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:51 PM PDT 24 438518057 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1936475841 Jul 27 05:16:35 PM PDT 24 Jul 27 05:16:38 PM PDT 24 435762732 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.477662892 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:44 PM PDT 24 8602668450 ps
T859 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.706545876 Jul 27 05:16:22 PM PDT 24 Jul 27 05:16:25 PM PDT 24 532435342 ps
T860 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.240543964 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 444265606 ps
T861 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.201697238 Jul 27 05:16:07 PM PDT 24 Jul 27 05:16:26 PM PDT 24 8355702505 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2437249481 Jul 27 05:16:13 PM PDT 24 Jul 27 05:16:14 PM PDT 24 731940844 ps
T863 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3974676564 Jul 27 05:16:14 PM PDT 24 Jul 27 05:16:19 PM PDT 24 1204502204 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1236248275 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:46 PM PDT 24 8509123808 ps
T865 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.636048503 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 420514907 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2034018589 Jul 27 05:16:16 PM PDT 24 Jul 27 05:16:17 PM PDT 24 385864825 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4064587331 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:41 PM PDT 24 677981961 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.20748456 Jul 27 05:16:00 PM PDT 24 Jul 27 05:16:02 PM PDT 24 504020445 ps
T122 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2835669204 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:40 PM PDT 24 439330401 ps
T869 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1479073473 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:50 PM PDT 24 277803803 ps
T870 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.100476690 Jul 27 05:16:35 PM PDT 24 Jul 27 05:16:37 PM PDT 24 548184364 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2190944948 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:41 PM PDT 24 2191725175 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3445753594 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:41 PM PDT 24 4649746396 ps
T873 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3326292060 Jul 27 05:16:35 PM PDT 24 Jul 27 05:16:56 PM PDT 24 7698942356 ps
T874 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.107799454 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:38 PM PDT 24 494193328 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.673750909 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:29 PM PDT 24 571823712 ps
T876 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1549409085 Jul 27 05:16:05 PM PDT 24 Jul 27 05:16:53 PM PDT 24 36397694233 ps
T877 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2537188785 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:37 PM PDT 24 293884566 ps
T878 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.700041529 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:41 PM PDT 24 2973731788 ps
T879 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1090658164 Jul 27 05:16:39 PM PDT 24 Jul 27 05:16:40 PM PDT 24 429188019 ps
T880 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1294458485 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:24 PM PDT 24 662597966 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2118429086 Jul 27 05:16:22 PM PDT 24 Jul 27 05:16:25 PM PDT 24 568344727 ps
T333 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2418652001 Jul 27 05:16:39 PM PDT 24 Jul 27 05:16:47 PM PDT 24 7974565905 ps
T882 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3762283818 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:32 PM PDT 24 2778472550 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.971830916 Jul 27 05:16:13 PM PDT 24 Jul 27 05:16:14 PM PDT 24 899179119 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3664085548 Jul 27 05:16:25 PM PDT 24 Jul 27 05:16:28 PM PDT 24 806843970 ps
T885 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.194980370 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:40 PM PDT 24 9080468964 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2432506944 Jul 27 05:16:25 PM PDT 24 Jul 27 05:16:39 PM PDT 24 8278873154 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3811407134 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:51 PM PDT 24 5011382339 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2548110571 Jul 27 05:16:41 PM PDT 24 Jul 27 05:16:43 PM PDT 24 519922349 ps
T889 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1648012380 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 368934952 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3891117954 Jul 27 05:16:14 PM PDT 24 Jul 27 05:16:16 PM PDT 24 462755733 ps
T891 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2986972516 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 410762616 ps
T892 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.981820347 Jul 27 05:16:02 PM PDT 24 Jul 27 05:16:04 PM PDT 24 453209480 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3069128095 Jul 27 05:16:14 PM PDT 24 Jul 27 05:16:15 PM PDT 24 2609183238 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3253096345 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:31 PM PDT 24 2515163228 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.566636532 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:40 PM PDT 24 4519330208 ps
T896 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3447655125 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:39 PM PDT 24 547645243 ps
T897 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.217237778 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 455854585 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4246354997 Jul 27 05:16:15 PM PDT 24 Jul 27 05:16:17 PM PDT 24 292013760 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3293698700 Jul 27 05:16:25 PM PDT 24 Jul 27 05:16:27 PM PDT 24 558781239 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.451952244 Jul 27 05:16:05 PM PDT 24 Jul 27 05:16:06 PM PDT 24 370073708 ps
T901 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1868886156 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:54 PM PDT 24 4731339198 ps
T902 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.653143191 Jul 27 05:16:06 PM PDT 24 Jul 27 05:16:07 PM PDT 24 295426954 ps
T903 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.44796251 Jul 27 05:16:47 PM PDT 24 Jul 27 05:16:48 PM PDT 24 488486648 ps
T904 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.745836890 Jul 27 05:16:49 PM PDT 24 Jul 27 05:16:50 PM PDT 24 359301663 ps
T905 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4144648526 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:53 PM PDT 24 8450361560 ps
T906 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2760651932 Jul 27 05:16:17 PM PDT 24 Jul 27 05:16:18 PM PDT 24 467255495 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2087465480 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:29 PM PDT 24 853927790 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2615173661 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:25 PM PDT 24 425542538 ps
T909 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2242883068 Jul 27 05:16:23 PM PDT 24 Jul 27 05:16:26 PM PDT 24 662032281 ps
T910 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2065254206 Jul 27 05:16:24 PM PDT 24 Jul 27 05:16:25 PM PDT 24 332471120 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4026382825 Jul 27 05:16:02 PM PDT 24 Jul 27 05:16:13 PM PDT 24 5128899259 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2928333100 Jul 27 05:16:39 PM PDT 24 Jul 27 05:16:40 PM PDT 24 446260734 ps
T913 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1488533863 Jul 27 05:16:37 PM PDT 24 Jul 27 05:16:39 PM PDT 24 377157487 ps
T914 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2412523693 Jul 27 05:16:36 PM PDT 24 Jul 27 05:16:38 PM PDT 24 509820829 ps
T915 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.325204340 Jul 27 05:16:29 PM PDT 24 Jul 27 05:16:30 PM PDT 24 593432168 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2121232517 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:39 PM PDT 24 468703502 ps
T917 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3386610707 Jul 27 05:16:27 PM PDT 24 Jul 27 05:16:35 PM PDT 24 4438747720 ps
T918 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1459996923 Jul 27 05:16:51 PM PDT 24 Jul 27 05:16:52 PM PDT 24 364406404 ps
T919 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3546711323 Jul 27 05:16:42 PM PDT 24 Jul 27 05:16:43 PM PDT 24 570772565 ps
T920 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.233504838 Jul 27 05:16:38 PM PDT 24 Jul 27 05:16:51 PM PDT 24 2412613526 ps

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2636645691
Short name T2
Test name
Test status
Simulation time 536310408834 ps
CPU time 1154.93 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:54:52 PM PDT 24
Peak memory 201200 kb
Host smart-9500a81d-0cc5-464a-afeb-44ef14c3199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636645691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2636645691
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2491715538
Short name T49
Test name
Test status
Simulation time 598559316950 ps
CPU time 1424.8 seconds
Started Jul 27 06:40:22 PM PDT 24
Finished Jul 27 07:04:07 PM PDT 24
Peak memory 209800 kb
Host smart-f4fa89ca-2e5b-4367-80bf-308fe58735b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491715538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2491715538
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.503088926
Short name T18
Test name
Test status
Simulation time 152599029758 ps
CPU time 195.31 seconds
Started Jul 27 06:40:15 PM PDT 24
Finished Jul 27 06:43:30 PM PDT 24
Peak memory 217752 kb
Host smart-c47d5702-2edd-4119-862e-2c53bd2f9419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503088926 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.503088926
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1565080851
Short name T35
Test name
Test status
Simulation time 492613096597 ps
CPU time 1081.33 seconds
Started Jul 27 06:41:28 PM PDT 24
Finished Jul 27 06:59:30 PM PDT 24
Peak memory 201212 kb
Host smart-1a9e97f4-cbaa-42a4-80d5-126aabc45c45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565080851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1565080851
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2261955578
Short name T48
Test name
Test status
Simulation time 120189532700 ps
CPU time 655.86 seconds
Started Jul 27 06:39:22 PM PDT 24
Finished Jul 27 06:50:18 PM PDT 24
Peak memory 201668 kb
Host smart-6dec0a9f-76a4-43ab-96aa-a34a740e9edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261955578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2261955578
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1377034556
Short name T44
Test name
Test status
Simulation time 680006511608 ps
CPU time 1671.4 seconds
Started Jul 27 06:36:09 PM PDT 24
Finished Jul 27 07:04:00 PM PDT 24
Peak memory 201220 kb
Host smart-40b873ba-5480-4ef1-b3f5-34f584366bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377034556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1377034556
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1224258906
Short name T57
Test name
Test status
Simulation time 492938222578 ps
CPU time 671.19 seconds
Started Jul 27 06:35:32 PM PDT 24
Finished Jul 27 06:46:43 PM PDT 24
Peak memory 201172 kb
Host smart-66f1081b-8c7d-4234-8679-5afbe347eb0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224258906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1224258906
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2862112197
Short name T217
Test name
Test status
Simulation time 517613911352 ps
CPU time 1237.86 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:56:19 PM PDT 24
Peak memory 201216 kb
Host smart-ff5c401d-7cdc-48c5-be6d-c5be74e592f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862112197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2862112197
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.352984635
Short name T8
Test name
Test status
Simulation time 529620728338 ps
CPU time 679.99 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:46:35 PM PDT 24
Peak memory 201208 kb
Host smart-f06ede6d-891b-4d08-a903-f27fc2cf330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352984635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.352984635
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.32344864
Short name T58
Test name
Test status
Simulation time 8419523299 ps
CPU time 12.14 seconds
Started Jul 27 05:16:30 PM PDT 24
Finished Jul 27 05:16:42 PM PDT 24
Peak memory 201656 kb
Host smart-529091c2-1bd6-4224-8808-205cfc3c43a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_int
g_err.32344864
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3409699049
Short name T141
Test name
Test status
Simulation time 563005930972 ps
CPU time 138.97 seconds
Started Jul 27 06:39:48 PM PDT 24
Finished Jul 27 06:42:07 PM PDT 24
Peak memory 201224 kb
Host smart-690033e6-bce0-4143-9d95-6ef71d3a1406
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409699049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3409699049
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.21909463
Short name T214
Test name
Test status
Simulation time 505687787837 ps
CPU time 1117.99 seconds
Started Jul 27 06:40:05 PM PDT 24
Finished Jul 27 06:58:44 PM PDT 24
Peak memory 201224 kb
Host smart-35f23d71-ee2c-4391-bda3-5c5d81cbe443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21909463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.21909463
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2129740257
Short name T135
Test name
Test status
Simulation time 338765451122 ps
CPU time 95.69 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:37:14 PM PDT 24
Peak memory 201168 kb
Host smart-d49ba22f-c5c5-4d9b-a5d2-9dca373bb793
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129740257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2129740257
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.346385910
Short name T138
Test name
Test status
Simulation time 346132188128 ps
CPU time 220.61 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:39:30 PM PDT 24
Peak memory 201232 kb
Host smart-d853c818-0889-43b9-a785-eb13a61bc6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346385910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.346385910
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2490124952
Short name T362
Test name
Test status
Simulation time 399977519 ps
CPU time 0.77 seconds
Started Jul 27 06:36:02 PM PDT 24
Finished Jul 27 06:36:02 PM PDT 24
Peak memory 201052 kb
Host smart-7351e126-2c64-4734-8c50-e3c271c324ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490124952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2490124952
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1991377102
Short name T54
Test name
Test status
Simulation time 49014422945 ps
CPU time 159.48 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:18:46 PM PDT 24
Peak memory 201696 kb
Host smart-661310ce-194d-43d2-9b36-74e59403071a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991377102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1991377102
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1422439632
Short name T208
Test name
Test status
Simulation time 550407268027 ps
CPU time 352.99 seconds
Started Jul 27 06:36:05 PM PDT 24
Finished Jul 27 06:41:58 PM PDT 24
Peak memory 201220 kb
Host smart-34ebc1c2-41dc-44bb-b96b-c6a345ce4eb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422439632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1422439632
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3945133957
Short name T61
Test name
Test status
Simulation time 213747861592 ps
CPU time 210.06 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:39:05 PM PDT 24
Peak memory 217592 kb
Host smart-ae77c09c-297d-4297-b036-db4253ea72a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945133957 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3945133957
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2736188820
Short name T93
Test name
Test status
Simulation time 511379972305 ps
CPU time 1087.24 seconds
Started Jul 27 06:40:42 PM PDT 24
Finished Jul 27 06:58:50 PM PDT 24
Peak memory 201248 kb
Host smart-50a4b393-cdc4-4890-b51d-cab12163c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736188820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2736188820
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2108798191
Short name T213
Test name
Test status
Simulation time 503454645990 ps
CPU time 308.81 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:42:42 PM PDT 24
Peak memory 201212 kb
Host smart-1d18ecb4-29bd-4aff-b848-10d8d1228139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108798191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2108798191
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.154362420
Short name T70
Test name
Test status
Simulation time 355967180 ps
CPU time 2.9 seconds
Started Jul 27 05:16:02 PM PDT 24
Finished Jul 27 05:16:05 PM PDT 24
Peak memory 217604 kb
Host smart-819d98da-6c62-49f4-924d-7aa526980086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154362420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.154362420
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3749246569
Short name T196
Test name
Test status
Simulation time 499325686002 ps
CPU time 75.42 seconds
Started Jul 27 06:35:59 PM PDT 24
Finished Jul 27 06:37:14 PM PDT 24
Peak memory 201232 kb
Host smart-48916275-426b-48e7-81c4-c2c9f315eb02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749246569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3749246569
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2214577472
Short name T47
Test name
Test status
Simulation time 521077819462 ps
CPU time 640.87 seconds
Started Jul 27 06:42:21 PM PDT 24
Finished Jul 27 06:53:02 PM PDT 24
Peak memory 201196 kb
Host smart-43b5a3e2-f9ed-4f36-bb62-26ec501aa46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214577472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2214577472
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.562029465
Short name T33
Test name
Test status
Simulation time 372193248362 ps
CPU time 803.34 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:51:14 PM PDT 24
Peak memory 201308 kb
Host smart-95b88489-6a8c-4caf-add8-56527b161070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562029465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
562029465
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.137513526
Short name T229
Test name
Test status
Simulation time 324649798248 ps
CPU time 205.72 seconds
Started Jul 27 06:40:23 PM PDT 24
Finished Jul 27 06:43:49 PM PDT 24
Peak memory 201192 kb
Host smart-733d2490-0358-470b-b8da-7171001b03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137513526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.137513526
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.175645751
Short name T194
Test name
Test status
Simulation time 351028235146 ps
CPU time 501.05 seconds
Started Jul 27 06:39:47 PM PDT 24
Finished Jul 27 06:48:08 PM PDT 24
Peak memory 201180 kb
Host smart-35e78e01-402d-4129-a728-2e05ebaa4bf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175645751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.175645751
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.453092277
Short name T218
Test name
Test status
Simulation time 550718561596 ps
CPU time 966.3 seconds
Started Jul 27 06:39:05 PM PDT 24
Finished Jul 27 06:55:11 PM PDT 24
Peak memory 201236 kb
Host smart-493110bd-7670-4578-bdc9-deabc360c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453092277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.453092277
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2228588904
Short name T67
Test name
Test status
Simulation time 8221653484 ps
CPU time 19.91 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:34 PM PDT 24
Peak memory 217880 kb
Host smart-e967b921-5814-4690-8837-e463d186f588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228588904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2228588904
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2814661272
Short name T168
Test name
Test status
Simulation time 506614142712 ps
CPU time 1092.32 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:53:49 PM PDT 24
Peak memory 201264 kb
Host smart-de2bf522-a4d6-4aa6-b7e7-7d886db7d6b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814661272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2814661272
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2571449863
Short name T45
Test name
Test status
Simulation time 340517853097 ps
CPU time 192.6 seconds
Started Jul 27 06:40:05 PM PDT 24
Finished Jul 27 06:43:18 PM PDT 24
Peak memory 201244 kb
Host smart-628cd1af-1474-421e-a9d8-6d15068a3697
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571449863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2571449863
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2343597957
Short name T328
Test name
Test status
Simulation time 544008897828 ps
CPU time 389.93 seconds
Started Jul 27 06:36:50 PM PDT 24
Finished Jul 27 06:43:20 PM PDT 24
Peak memory 201220 kb
Host smart-4d7819bf-f25b-4fe1-b420-ec3aec2b1b8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343597957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2343597957
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3058221104
Short name T149
Test name
Test status
Simulation time 488470985477 ps
CPU time 607 seconds
Started Jul 27 06:36:07 PM PDT 24
Finished Jul 27 06:46:14 PM PDT 24
Peak memory 201204 kb
Host smart-c867799e-2594-49ec-94d1-b4200c32ab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058221104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3058221104
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4083199224
Short name T326
Test name
Test status
Simulation time 643371583882 ps
CPU time 477.7 seconds
Started Jul 27 06:40:10 PM PDT 24
Finished Jul 27 06:48:08 PM PDT 24
Peak memory 201304 kb
Host smart-f80b73f8-00f3-498b-a6d8-016b2e162412
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083199224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4083199224
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2239542091
Short name T307
Test name
Test status
Simulation time 588209418915 ps
CPU time 80.35 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:37:36 PM PDT 24
Peak memory 201280 kb
Host smart-d17bf548-e575-4613-93c7-f43165f7fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239542091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2239542091
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2013117381
Short name T86
Test name
Test status
Simulation time 345838114507 ps
CPU time 220.23 seconds
Started Jul 27 06:38:00 PM PDT 24
Finished Jul 27 06:41:40 PM PDT 24
Peak memory 201256 kb
Host smart-ee881d59-8177-43ac-b2ba-aecc08063172
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013117381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2013117381
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1664895999
Short name T9
Test name
Test status
Simulation time 328842960081 ps
CPU time 198.36 seconds
Started Jul 27 06:40:26 PM PDT 24
Finished Jul 27 06:43:44 PM PDT 24
Peak memory 201224 kb
Host smart-95bb592e-9a8f-4dcf-92db-4abdcd2e23f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664895999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1664895999
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.214908930
Short name T152
Test name
Test status
Simulation time 498741277913 ps
CPU time 294.24 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:40:39 PM PDT 24
Peak memory 201248 kb
Host smart-bb7a001b-81a5-467b-aa58-d37b93544ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214908930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.214908930
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1318838252
Short name T265
Test name
Test status
Simulation time 579279185689 ps
CPU time 295.87 seconds
Started Jul 27 06:40:40 PM PDT 24
Finished Jul 27 06:45:36 PM PDT 24
Peak memory 201180 kb
Host smart-3b3d61da-43df-4a14-a089-0266f0a86957
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318838252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1318838252
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.174041725
Short name T27
Test name
Test status
Simulation time 100937683339 ps
CPU time 62.89 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:36:36 PM PDT 24
Peak memory 209564 kb
Host smart-1a3f6e27-707f-4cc1-9003-ccdc5e7b56f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174041725 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.174041725
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2946332196
Short name T236
Test name
Test status
Simulation time 65180933732 ps
CPU time 76.81 seconds
Started Jul 27 06:42:29 PM PDT 24
Finished Jul 27 06:43:46 PM PDT 24
Peak memory 201324 kb
Host smart-47ea169a-7c6f-4bcb-89d2-6bd4a06ca90a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946332196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2946332196
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1052476866
Short name T206
Test name
Test status
Simulation time 519140583625 ps
CPU time 1112.5 seconds
Started Jul 27 06:39:40 PM PDT 24
Finished Jul 27 06:58:13 PM PDT 24
Peak memory 201216 kb
Host smart-4d126647-cfeb-4f92-b268-3f144dab1eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052476866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1052476866
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3281780908
Short name T238
Test name
Test status
Simulation time 491408754465 ps
CPU time 323.95 seconds
Started Jul 27 06:37:14 PM PDT 24
Finished Jul 27 06:42:38 PM PDT 24
Peak memory 201344 kb
Host smart-d2785171-1e4e-470b-b97c-8548aa6cfc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281780908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3281780908
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.682630965
Short name T183
Test name
Test status
Simulation time 376105690430 ps
CPU time 202.3 seconds
Started Jul 27 06:38:34 PM PDT 24
Finished Jul 27 06:41:57 PM PDT 24
Peak memory 201204 kb
Host smart-5cf7b65e-46a0-4cdc-9707-3ac7e39fc3f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682630965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.682630965
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.4150348431
Short name T294
Test name
Test status
Simulation time 489363077683 ps
CPU time 1106.41 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:54:01 PM PDT 24
Peak memory 201192 kb
Host smart-56f7e550-c9b9-4e4d-a9fc-5ae00228705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150348431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.4150348431
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1979154654
Short name T212
Test name
Test status
Simulation time 717637430068 ps
CPU time 1030.01 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:52:49 PM PDT 24
Peak memory 201232 kb
Host smart-550e8b78-8c43-4388-adbb-677646ac1c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979154654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1979154654
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4223965028
Short name T56
Test name
Test status
Simulation time 2519917807 ps
CPU time 2.77 seconds
Started Jul 27 05:16:02 PM PDT 24
Finished Jul 27 05:16:05 PM PDT 24
Peak memory 201580 kb
Host smart-231a66fa-d66c-4d92-adde-1b8b903a9600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223965028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4223965028
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1973834051
Short name T202
Test name
Test status
Simulation time 367008540110 ps
CPU time 434.82 seconds
Started Jul 27 06:36:27 PM PDT 24
Finished Jul 27 06:43:42 PM PDT 24
Peak memory 201152 kb
Host smart-cbe9b342-dab7-45bb-bdd1-182590cf798c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973834051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1973834051
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.93646873
Short name T51
Test name
Test status
Simulation time 219183072539 ps
CPU time 765.75 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:48:23 PM PDT 24
Peak memory 211080 kb
Host smart-fa89a56a-f83e-437b-9188-a5510ee872d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93646873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.93646873
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1031977400
Short name T280
Test name
Test status
Simulation time 171752693015 ps
CPU time 187.91 seconds
Started Jul 27 06:35:56 PM PDT 24
Finished Jul 27 06:39:04 PM PDT 24
Peak memory 201276 kb
Host smart-0b41cc8f-bd0e-4a59-a93f-0b22f069752b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031977400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1031977400
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.442613632
Short name T269
Test name
Test status
Simulation time 516394745261 ps
CPU time 107.66 seconds
Started Jul 27 06:36:28 PM PDT 24
Finished Jul 27 06:38:16 PM PDT 24
Peak memory 201160 kb
Host smart-057ccd84-0cc3-47be-8457-f914667380c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442613632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.442613632
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3807272109
Short name T26
Test name
Test status
Simulation time 657757371119 ps
CPU time 166.03 seconds
Started Jul 27 06:37:08 PM PDT 24
Finished Jul 27 06:39:54 PM PDT 24
Peak memory 209956 kb
Host smart-6bf6a14d-38e2-42aa-851a-07dfe1abcd68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807272109 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3807272109
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.423828622
Short name T301
Test name
Test status
Simulation time 491900255945 ps
CPU time 578.35 seconds
Started Jul 27 06:39:11 PM PDT 24
Finished Jul 27 06:48:50 PM PDT 24
Peak memory 201292 kb
Host smart-3423d5a5-b756-422b-ae01-fea24cbaa563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423828622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.423828622
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.517489222
Short name T199
Test name
Test status
Simulation time 355078346456 ps
CPU time 200.78 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:38:59 PM PDT 24
Peak memory 201168 kb
Host smart-fefa568c-cd61-4581-8607-aeb56b105400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517489222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.517489222
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3214394314
Short name T244
Test name
Test status
Simulation time 172843204329 ps
CPU time 410.72 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:43:07 PM PDT 24
Peak memory 201224 kb
Host smart-1705a487-b6b1-4089-aa91-7f817c25b6b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214394314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3214394314
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2719178371
Short name T341
Test name
Test status
Simulation time 140594636953 ps
CPU time 363.2 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:42:20 PM PDT 24
Peak memory 201596 kb
Host smart-372446f2-e655-486b-b7a0-99ba4c8e770c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719178371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2719178371
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.111577974
Short name T158
Test name
Test status
Simulation time 179623473909 ps
CPU time 445.75 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:43:52 PM PDT 24
Peak memory 201192 kb
Host smart-0bd1e998-2177-4918-adbd-db64d5a23c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111577974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.111577974
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4238174555
Short name T284
Test name
Test status
Simulation time 317181979740 ps
CPU time 184.98 seconds
Started Jul 27 06:36:28 PM PDT 24
Finished Jul 27 06:39:33 PM PDT 24
Peak memory 218128 kb
Host smart-dcbab3f9-1239-488f-8b23-4ed7a6ea6d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238174555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4238174555
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.487375846
Short name T278
Test name
Test status
Simulation time 370866615862 ps
CPU time 117.99 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:39:41 PM PDT 24
Peak memory 211836 kb
Host smart-7c04d4c4-09f1-4a1a-bb11-d9d0a72dc500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487375846 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.487375846
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.419607073
Short name T256
Test name
Test status
Simulation time 330491400716 ps
CPU time 189.69 seconds
Started Jul 27 06:38:01 PM PDT 24
Finished Jul 27 06:41:11 PM PDT 24
Peak memory 201200 kb
Host smart-4ab2618f-5e20-4c1b-a7be-05b4d53812b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419607073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.419607073
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3474091121
Short name T151
Test name
Test status
Simulation time 496214768864 ps
CPU time 198.63 seconds
Started Jul 27 06:41:17 PM PDT 24
Finished Jul 27 06:44:36 PM PDT 24
Peak memory 201216 kb
Host smart-856f6450-adab-4576-8467-03c182929749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474091121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3474091121
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.865833229
Short name T267
Test name
Test status
Simulation time 159098093500 ps
CPU time 189.99 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:38:47 PM PDT 24
Peak memory 201244 kb
Host smart-01d38531-2b03-4343-aa98-b525b5dafe18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865833229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.865833229
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4274068766
Short name T332
Test name
Test status
Simulation time 8016620999 ps
CPU time 20.36 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:44 PM PDT 24
Peak memory 201796 kb
Host smart-5fe10857-bb5b-439a-978c-6174ee8d99c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274068766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4274068766
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.435424025
Short name T10
Test name
Test status
Simulation time 345469149571 ps
CPU time 157.54 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:38:28 PM PDT 24
Peak memory 201304 kb
Host smart-3987cc2f-53ed-42c4-a41f-dc85dfa25d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435424025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.435424025
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1262205783
Short name T225
Test name
Test status
Simulation time 408062994540 ps
CPU time 68.18 seconds
Started Jul 27 06:35:28 PM PDT 24
Finished Jul 27 06:36:37 PM PDT 24
Peak memory 201272 kb
Host smart-a55bd503-0b48-4b32-a05c-092cfecbdcd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262205783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1262205783
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2997302966
Short name T300
Test name
Test status
Simulation time 161926245366 ps
CPU time 385.92 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:43:14 PM PDT 24
Peak memory 201296 kb
Host smart-29ed8362-b05d-4a70-9f6e-a13497b609d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997302966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2997302966
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.931191821
Short name T37
Test name
Test status
Simulation time 353595938389 ps
CPU time 592.07 seconds
Started Jul 27 06:37:08 PM PDT 24
Finished Jul 27 06:47:00 PM PDT 24
Peak memory 209916 kb
Host smart-f74716b2-0e2c-48e9-874e-84afbadc105d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931191821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
931191821
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2347244284
Short name T239
Test name
Test status
Simulation time 167996651519 ps
CPU time 184.5 seconds
Started Jul 27 06:38:56 PM PDT 24
Finished Jul 27 06:42:01 PM PDT 24
Peak memory 201144 kb
Host smart-caf24462-7952-499f-8ed6-e3a86f13ff01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347244284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2347244284
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2416937610
Short name T39
Test name
Test status
Simulation time 299372040863 ps
CPU time 141.36 seconds
Started Jul 27 06:39:40 PM PDT 24
Finished Jul 27 06:42:02 PM PDT 24
Peak memory 217540 kb
Host smart-d797d554-e255-4cfb-8433-4ee866798698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416937610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2416937610
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2547726233
Short name T255
Test name
Test status
Simulation time 494797083725 ps
CPU time 89.84 seconds
Started Jul 27 06:39:46 PM PDT 24
Finished Jul 27 06:41:17 PM PDT 24
Peak memory 201200 kb
Host smart-032732e0-7c80-4085-834c-0324609123e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547726233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2547726233
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.163435498
Short name T317
Test name
Test status
Simulation time 282422405891 ps
CPU time 162.62 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:42:56 PM PDT 24
Peak memory 201212 kb
Host smart-96296361-e3bb-4668-a72b-7be40dbb14e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163435498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.163435498
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1935801608
Short name T12
Test name
Test status
Simulation time 158197914523 ps
CPU time 59.82 seconds
Started Jul 27 06:35:40 PM PDT 24
Finished Jul 27 06:36:40 PM PDT 24
Peak memory 201208 kb
Host smart-388e703e-1141-42b7-92ad-2f6b4267189d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935801608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1935801608
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1925531229
Short name T349
Test name
Test status
Simulation time 117154684965 ps
CPU time 393.14 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:42:14 PM PDT 24
Peak memory 201716 kb
Host smart-4d5d760c-d3dc-4ca7-a98d-1be5e8ea7d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925531229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1925531229
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1675054499
Short name T322
Test name
Test status
Simulation time 208542322501 ps
CPU time 133.63 seconds
Started Jul 27 06:36:10 PM PDT 24
Finished Jul 27 06:38:24 PM PDT 24
Peak memory 201192 kb
Host smart-bf0b7bc2-2b28-4cb4-a174-d704352e98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675054499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1675054499
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3271214453
Short name T335
Test name
Test status
Simulation time 113512992360 ps
CPU time 657.67 seconds
Started Jul 27 06:37:08 PM PDT 24
Finished Jul 27 06:48:06 PM PDT 24
Peak memory 201708 kb
Host smart-eec7e80c-096a-44f6-8a4c-c4b4c90d8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271214453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3271214453
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.870051651
Short name T182
Test name
Test status
Simulation time 503827813532 ps
CPU time 203.33 seconds
Started Jul 27 06:37:50 PM PDT 24
Finished Jul 27 06:41:14 PM PDT 24
Peak memory 201136 kb
Host smart-a257f495-df2b-4699-a658-1d78761a7b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870051651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.870051651
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1848591444
Short name T148
Test name
Test status
Simulation time 427044267550 ps
CPU time 393.47 seconds
Started Jul 27 06:38:18 PM PDT 24
Finished Jul 27 06:44:52 PM PDT 24
Peak memory 209912 kb
Host smart-6e08d38a-ce0e-4832-bfa4-433eb92be5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848591444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1848591444
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3104718730
Short name T282
Test name
Test status
Simulation time 490168843791 ps
CPU time 170.34 seconds
Started Jul 27 06:39:21 PM PDT 24
Finished Jul 27 06:42:12 PM PDT 24
Peak memory 201296 kb
Host smart-7f8d44c2-6f85-4434-8a6c-cba9bdb57cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104718730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3104718730
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3111594391
Short name T242
Test name
Test status
Simulation time 162319090323 ps
CPU time 357.79 seconds
Started Jul 27 06:39:57 PM PDT 24
Finished Jul 27 06:45:55 PM PDT 24
Peak memory 201232 kb
Host smart-42f7faab-0785-4d7b-a353-17d49c2d3157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111594391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3111594391
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1771686885
Short name T283
Test name
Test status
Simulation time 498200038814 ps
CPU time 178.84 seconds
Started Jul 27 06:40:40 PM PDT 24
Finished Jul 27 06:43:39 PM PDT 24
Peak memory 201204 kb
Host smart-0ec8f57d-04ca-4dcf-8b24-679489b67920
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771686885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1771686885
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.964783693
Short name T826
Test name
Test status
Simulation time 368201700 ps
CPU time 2.56 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:16:09 PM PDT 24
Peak memory 201668 kb
Host smart-633e9eb6-abb2-424d-9556-18b9d3038943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964783693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.964783693
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1780586589
Short name T250
Test name
Test status
Simulation time 507218750416 ps
CPU time 585.08 seconds
Started Jul 27 06:35:51 PM PDT 24
Finished Jul 27 06:45:36 PM PDT 24
Peak memory 201288 kb
Host smart-2a961928-d3e2-4d93-bd8d-6c68bbfc8afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780586589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1780586589
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4088976670
Short name T347
Test name
Test status
Simulation time 83945350389 ps
CPU time 314.55 seconds
Started Jul 27 06:37:49 PM PDT 24
Finished Jul 27 06:43:04 PM PDT 24
Peak memory 201640 kb
Host smart-0554c16e-4f7b-4e1b-9d9e-203e9f8c3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088976670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4088976670
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.455417715
Short name T336
Test name
Test status
Simulation time 93360042993 ps
CPU time 385.53 seconds
Started Jul 27 06:40:25 PM PDT 24
Finished Jul 27 06:46:51 PM PDT 24
Peak memory 201616 kb
Host smart-4712e6bd-3ac7-45f6-8b25-9152cf2d4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455417715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.455417715
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3680071988
Short name T38
Test name
Test status
Simulation time 420877988084 ps
CPU time 517.95 seconds
Started Jul 27 06:41:07 PM PDT 24
Finished Jul 27 06:49:45 PM PDT 24
Peak memory 218032 kb
Host smart-2e4c20f3-3999-4ba1-bcb0-7750ad3efa65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680071988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3680071988
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1483434575
Short name T246
Test name
Test status
Simulation time 251345796134 ps
CPU time 537.71 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:50:36 PM PDT 24
Peak memory 209880 kb
Host smart-f0ca8b73-6df9-478a-b080-7a3e6598c4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483434575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1483434575
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2742975674
Short name T279
Test name
Test status
Simulation time 1340514643199 ps
CPU time 1030.84 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:58:57 PM PDT 24
Peak memory 209868 kb
Host smart-4891156e-0ba2-48bd-8101-e6e98d04c52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742975674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2742975674
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2183046842
Short name T204
Test name
Test status
Simulation time 331132900802 ps
CPU time 282.05 seconds
Started Jul 27 06:42:13 PM PDT 24
Finished Jul 27 06:46:55 PM PDT 24
Peak memory 211016 kb
Host smart-3c4715cf-9889-432f-95b3-6011aba64e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183046842 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2183046842
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1290613615
Short name T305
Test name
Test status
Simulation time 358451094010 ps
CPU time 776 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:48:30 PM PDT 24
Peak memory 201256 kb
Host smart-e710cf59-6f06-4f7b-ba11-95b4c4d6db03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290613615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1290613615
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.106665701
Short name T32
Test name
Test status
Simulation time 118568827347 ps
CPU time 488.32 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:43:48 PM PDT 24
Peak memory 201676 kb
Host smart-68622bc4-4e5f-4755-925c-a00480e01ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106665701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.106665701
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.981820347
Short name T892
Test name
Test status
Simulation time 453209480 ps
CPU time 1.72 seconds
Started Jul 27 05:16:02 PM PDT 24
Finished Jul 27 05:16:04 PM PDT 24
Peak memory 201644 kb
Host smart-b0802c50-4ffa-4f39-86b0-628c21d2840b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981820347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.981820347
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2345668568
Short name T112
Test name
Test status
Simulation time 1218141858 ps
CPU time 3.49 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:16:10 PM PDT 24
Peak memory 201408 kb
Host smart-5021fc1e-5b09-4c12-8c25-cbdf7df57916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345668568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2345668568
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1447184516
Short name T848
Test name
Test status
Simulation time 353229858 ps
CPU time 1.76 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:16:08 PM PDT 24
Peak memory 201480 kb
Host smart-7c4606d3-57d0-4940-b227-6bf76205d530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447184516 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1447184516
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.20748456
Short name T868
Test name
Test status
Simulation time 504020445 ps
CPU time 1.91 seconds
Started Jul 27 05:16:00 PM PDT 24
Finished Jul 27 05:16:02 PM PDT 24
Peak memory 201396 kb
Host smart-76d21222-6344-444b-92c0-5f744833fa64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.20748456
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1454007433
Short name T812
Test name
Test status
Simulation time 371389870 ps
CPU time 1.39 seconds
Started Jul 27 05:15:59 PM PDT 24
Finished Jul 27 05:16:01 PM PDT 24
Peak memory 201436 kb
Host smart-c2b90672-7997-4650-badf-89107ae98acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454007433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1454007433
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.201697238
Short name T861
Test name
Test status
Simulation time 8355702505 ps
CPU time 19.45 seconds
Started Jul 27 05:16:07 PM PDT 24
Finished Jul 27 05:16:26 PM PDT 24
Peak memory 201704 kb
Host smart-31ca6f9b-e8cc-4b4b-a085-ec1390f826c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201697238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.201697238
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.722238574
Short name T114
Test name
Test status
Simulation time 803994469 ps
CPU time 4.24 seconds
Started Jul 27 05:16:00 PM PDT 24
Finished Jul 27 05:16:05 PM PDT 24
Peak memory 201640 kb
Host smart-678e699e-5162-4780-8537-3c68c3e3093b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722238574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.722238574
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1549409085
Short name T876
Test name
Test status
Simulation time 36397694233 ps
CPU time 48.57 seconds
Started Jul 27 05:16:05 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201676 kb
Host smart-ed91d814-aad2-4bc5-a33a-1933932dd64a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549409085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1549409085
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.575775269
Short name T128
Test name
Test status
Simulation time 1188233360 ps
CPU time 2.35 seconds
Started Jul 27 05:16:04 PM PDT 24
Finished Jul 27 05:16:07 PM PDT 24
Peak memory 201380 kb
Host smart-31efb384-fa88-4d91-98b7-f634b1a39adc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575775269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.575775269
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2391104042
Short name T847
Test name
Test status
Simulation time 455302167 ps
CPU time 1.89 seconds
Started Jul 27 05:16:01 PM PDT 24
Finished Jul 27 05:16:03 PM PDT 24
Peak memory 201492 kb
Host smart-216bae0e-9269-4574-8d3c-d71e7b9f3126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391104042 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2391104042
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.451952244
Short name T900
Test name
Test status
Simulation time 370073708 ps
CPU time 1.53 seconds
Started Jul 27 05:16:05 PM PDT 24
Finished Jul 27 05:16:06 PM PDT 24
Peak memory 201364 kb
Host smart-9218f59d-02a3-4e09-b391-da0e6ae0612d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451952244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.451952244
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.653143191
Short name T902
Test name
Test status
Simulation time 295426954 ps
CPU time 0.98 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:16:07 PM PDT 24
Peak memory 201372 kb
Host smart-5ae14ca8-4ec9-4c33-ba05-1c881380df34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653143191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.653143191
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4026382825
Short name T911
Test name
Test status
Simulation time 5128899259 ps
CPU time 10.98 seconds
Started Jul 27 05:16:02 PM PDT 24
Finished Jul 27 05:16:13 PM PDT 24
Peak memory 201784 kb
Host smart-bdb00bb4-4cf8-4d2f-8c57-bdb0abd138d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026382825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4026382825
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3030552295
Short name T840
Test name
Test status
Simulation time 638564351 ps
CPU time 3.99 seconds
Started Jul 27 05:16:05 PM PDT 24
Finished Jul 27 05:16:09 PM PDT 24
Peak memory 209908 kb
Host smart-1a9a60fc-9e2b-4826-9ba4-62aaf4bfc83a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030552295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3030552295
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3472611756
Short name T60
Test name
Test status
Simulation time 4518477753 ps
CPU time 11.96 seconds
Started Jul 27 05:16:06 PM PDT 24
Finished Jul 27 05:16:18 PM PDT 24
Peak memory 201728 kb
Host smart-b803e11e-45cb-4a16-bf7a-9a85768b62da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472611756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3472611756
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2770120357
Short name T90
Test name
Test status
Simulation time 395246409 ps
CPU time 1.08 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 201492 kb
Host smart-5b6fb2d3-133e-4157-a006-70dd2c8f93e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770120357 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2770120357
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.294331748
Short name T813
Test name
Test status
Simulation time 418623203 ps
CPU time 0.95 seconds
Started Jul 27 05:16:35 PM PDT 24
Finished Jul 27 05:16:37 PM PDT 24
Peak memory 201372 kb
Host smart-a8f20055-f78d-4854-a4d7-d45398bf68d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294331748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.294331748
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2537188785
Short name T877
Test name
Test status
Simulation time 293884566 ps
CPU time 1.3 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:37 PM PDT 24
Peak memory 201328 kb
Host smart-5cd2749f-bd7b-4dfa-8459-44f3bde47a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537188785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2537188785
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2904861411
Short name T819
Test name
Test status
Simulation time 2326476805 ps
CPU time 1.47 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201496 kb
Host smart-63cfd059-3e67-4099-9ba3-f6ab02ef4b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904861411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2904861411
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2087465480
Short name T907
Test name
Test status
Simulation time 853927790 ps
CPU time 1.89 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:29 PM PDT 24
Peak memory 210008 kb
Host smart-92ec4b79-ec5c-4ed0-9861-07d630ea3f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087465480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2087465480
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4186850250
Short name T816
Test name
Test status
Simulation time 345303222 ps
CPU time 1.34 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201492 kb
Host smart-d0f3268a-104a-4f9a-ad2f-fd9b91df8eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186850250 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4186850250
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2835669204
Short name T122
Test name
Test status
Simulation time 439330401 ps
CPU time 1.96 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201444 kb
Host smart-c6b964ab-c9ad-468f-a837-79f86e173d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835669204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2835669204
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2548110571
Short name T888
Test name
Test status
Simulation time 519922349 ps
CPU time 1.23 seconds
Started Jul 27 05:16:41 PM PDT 24
Finished Jul 27 05:16:43 PM PDT 24
Peak memory 201344 kb
Host smart-ec205a75-f5e7-4f47-aa6b-9dde2887bf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548110571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2548110571
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3184575864
Short name T124
Test name
Test status
Simulation time 4111708003 ps
CPU time 5.02 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:42 PM PDT 24
Peak memory 201800 kb
Host smart-c02c719a-31c2-48da-9675-ab8022e29820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184575864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3184575864
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2079747274
Short name T845
Test name
Test status
Simulation time 515454012 ps
CPU time 2.5 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201776 kb
Host smart-3e8a44fe-2729-4d06-b5b8-af7bd17b3205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079747274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2079747274
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1187684906
Short name T77
Test name
Test status
Simulation time 8200401424 ps
CPU time 21.44 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:58 PM PDT 24
Peak memory 201732 kb
Host smart-3d974697-4c79-4583-92c3-3758d2ce0a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187684906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1187684906
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2928333100
Short name T912
Test name
Test status
Simulation time 446260734 ps
CPU time 1.19 seconds
Started Jul 27 05:16:39 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201552 kb
Host smart-0a679d2e-160e-4814-b166-8e2dc706d946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928333100 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2928333100
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1091453015
Short name T119
Test name
Test status
Simulation time 305720797 ps
CPU time 1.42 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:37 PM PDT 24
Peak memory 201468 kb
Host smart-f64509f1-b6ff-4e87-ae6d-f9d21372e404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091453015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1091453015
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2121232517
Short name T916
Test name
Test status
Simulation time 468703502 ps
CPU time 0.91 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201324 kb
Host smart-ed1eeeaf-7284-4e34-9b90-39f06597fb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121232517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2121232517
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.700041529
Short name T878
Test name
Test status
Simulation time 2973731788 ps
CPU time 3.42 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 201496 kb
Host smart-1cb21f21-d250-45e2-b483-e21b85b5aaa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700041529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.700041529
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1966243940
Short name T836
Test name
Test status
Simulation time 487328780 ps
CPU time 2.63 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 218144 kb
Host smart-27f8879c-dd8b-40c0-9e1c-b443d328e78b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966243940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1966243940
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3326292060
Short name T873
Test name
Test status
Simulation time 7698942356 ps
CPU time 20.58 seconds
Started Jul 27 05:16:35 PM PDT 24
Finished Jul 27 05:16:56 PM PDT 24
Peak memory 201640 kb
Host smart-0645b1ee-b5b4-4467-8068-4d862fb9f9f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326292060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3326292060
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3546711323
Short name T919
Test name
Test status
Simulation time 570772565 ps
CPU time 1.51 seconds
Started Jul 27 05:16:42 PM PDT 24
Finished Jul 27 05:16:43 PM PDT 24
Peak memory 201576 kb
Host smart-ed67d875-7949-4195-9160-8a8727582347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546711323 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3546711323
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1488533863
Short name T913
Test name
Test status
Simulation time 377157487 ps
CPU time 1.52 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201412 kb
Host smart-78b60e47-9598-4228-8a42-8574b7da3aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488533863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1488533863
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1811412479
Short name T827
Test name
Test status
Simulation time 528673512 ps
CPU time 1.18 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 201348 kb
Host smart-057a1eb8-c659-4122-9a89-a0b05123601c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811412479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1811412479
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2703740716
Short name T53
Test name
Test status
Simulation time 2501170059 ps
CPU time 5.65 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:44 PM PDT 24
Peak memory 201536 kb
Host smart-e7b9d2d5-e703-4310-86fc-ebf2518e1285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703740716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2703740716
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.190813271
Short name T823
Test name
Test status
Simulation time 1201296987 ps
CPU time 1.61 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201800 kb
Host smart-3098c4e0-6e7f-4421-a56b-a55987d40366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190813271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.190813271
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.194980370
Short name T885
Test name
Test status
Simulation time 9080468964 ps
CPU time 3.39 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201720 kb
Host smart-a414ec0e-68da-460e-bc1e-526cc1cfe40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194980370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.194980370
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.905829803
Short name T832
Test name
Test status
Simulation time 458910571 ps
CPU time 1.75 seconds
Started Jul 27 05:16:39 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 201576 kb
Host smart-6fd04c6f-0b5e-41ad-afd8-0c6f08ea4f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905829803 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.905829803
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1090658164
Short name T879
Test name
Test status
Simulation time 429188019 ps
CPU time 1.04 seconds
Started Jul 27 05:16:39 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201364 kb
Host smart-708b5a42-d3f5-4a89-88e7-f0829e575557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090658164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1090658164
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.107799454
Short name T874
Test name
Test status
Simulation time 494193328 ps
CPU time 0.8 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 201464 kb
Host smart-1b34c277-e77c-49ea-a800-8aa90afd0b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107799454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.107799454
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1686798664
Short name T837
Test name
Test status
Simulation time 4181840913 ps
CPU time 14.53 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201832 kb
Host smart-f3228d29-ea6a-4102-9583-63f00e75baba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686798664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1686798664
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1936475841
Short name T857
Test name
Test status
Simulation time 435762732 ps
CPU time 2.78 seconds
Started Jul 27 05:16:35 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 201776 kb
Host smart-99693574-9f3c-4ecb-8f52-21872252b871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936475841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1936475841
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3445753594
Short name T872
Test name
Test status
Simulation time 4649746396 ps
CPU time 4.3 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 201860 kb
Host smart-cba7efc1-67e9-4842-9240-543bb09c8c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445753594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3445753594
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2879083444
Short name T76
Test name
Test status
Simulation time 591787618 ps
CPU time 1.59 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201568 kb
Host smart-9e9a3885-e09e-40c0-8c09-cc4d4f8d7507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879083444 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2879083444
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3447655125
Short name T896
Test name
Test status
Simulation time 547645243 ps
CPU time 2.01 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201380 kb
Host smart-3e60c5ce-5fd7-48c5-8826-ee8501e9366e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447655125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3447655125
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2282998090
Short name T818
Test name
Test status
Simulation time 521365610 ps
CPU time 1.72 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201488 kb
Host smart-8996335e-21a7-49cc-a657-f2c2b28e8db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282998090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2282998090
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.233504838
Short name T920
Test name
Test status
Simulation time 2412613526 ps
CPU time 12.15 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201572 kb
Host smart-b5610eb2-a042-47a8-84e7-6c363f3f220c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233504838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.233504838
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4064587331
Short name T867
Test name
Test status
Simulation time 677981961 ps
CPU time 3.28 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 210008 kb
Host smart-97c7d22e-4b45-4966-ad2d-ccfcaa8e6764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064587331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4064587331
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2639544867
Short name T59
Test name
Test status
Simulation time 4478056901 ps
CPU time 6.77 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:45 PM PDT 24
Peak memory 201780 kb
Host smart-ce3b210b-c868-483d-b759-b4e01b6df653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639544867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2639544867
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2412523693
Short name T914
Test name
Test status
Simulation time 509820829 ps
CPU time 1.52 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 201600 kb
Host smart-a94fded6-78c9-41ce-b57e-a86b78a5cc61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412523693 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2412523693
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.100476690
Short name T870
Test name
Test status
Simulation time 548184364 ps
CPU time 2.17 seconds
Started Jul 27 05:16:35 PM PDT 24
Finished Jul 27 05:16:37 PM PDT 24
Peak memory 201376 kb
Host smart-2b3601db-3632-459f-8e58-fe59b064c017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100476690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.100476690
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2456474540
Short name T854
Test name
Test status
Simulation time 364491240 ps
CPU time 1.07 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201428 kb
Host smart-65c3e026-d86a-4a83-88d2-5057aabdd068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456474540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2456474540
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2190944948
Short name T871
Test name
Test status
Simulation time 2191725175 ps
CPU time 4.58 seconds
Started Jul 27 05:16:36 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 201580 kb
Host smart-750f39fb-ff23-40dd-9551-dd21a50f8073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190944948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2190944948
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4169882319
Short name T73
Test name
Test status
Simulation time 556793798 ps
CPU time 2.88 seconds
Started Jul 27 05:16:37 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 210008 kb
Host smart-8fbb6e2f-ce50-44bf-bc67-cc8a220ab983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169882319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.4169882319
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2418652001
Short name T333
Test name
Test status
Simulation time 7974565905 ps
CPU time 7.49 seconds
Started Jul 27 05:16:39 PM PDT 24
Finished Jul 27 05:16:47 PM PDT 24
Peak memory 201752 kb
Host smart-f9038c03-2f24-4bbb-8132-f307051779cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418652001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2418652001
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.365451287
Short name T91
Test name
Test status
Simulation time 625491332 ps
CPU time 1.37 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201324 kb
Host smart-484281df-60a0-49bc-bddc-fbe1cac8b134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365451287 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.365451287
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3802281250
Short name T817
Test name
Test status
Simulation time 542273620 ps
CPU time 2.04 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 201452 kb
Host smart-0ee9277e-7b2f-4674-b84b-b0a4e04430a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802281250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3802281250
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3218708143
Short name T814
Test name
Test status
Simulation time 567412661 ps
CPU time 0.91 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201344 kb
Host smart-23a8e29b-30a5-45b5-81a6-f2cc8ac7a12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218708143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3218708143
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1868886156
Short name T901
Test name
Test status
Simulation time 4731339198 ps
CPU time 5.6 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:54 PM PDT 24
Peak memory 201752 kb
Host smart-74f7d442-950b-4f1f-ab2d-62e2f6692b3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868886156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1868886156
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3241084595
Short name T851
Test name
Test status
Simulation time 864916340 ps
CPU time 1.67 seconds
Started Jul 27 05:16:41 PM PDT 24
Finished Jul 27 05:16:43 PM PDT 24
Peak memory 201664 kb
Host smart-617bb255-5d46-4265-9f9d-3c6630a19f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241084595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3241084595
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1236248275
Short name T864
Test name
Test status
Simulation time 8509123808 ps
CPU time 7.64 seconds
Started Jul 27 05:16:38 PM PDT 24
Finished Jul 27 05:16:46 PM PDT 24
Peak memory 201732 kb
Host smart-86c65cd7-b2d2-407f-989b-c910d52dde03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236248275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1236248275
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3569866543
Short name T855
Test name
Test status
Simulation time 833136936 ps
CPU time 1.18 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 201480 kb
Host smart-ecf37b5d-0883-4142-8688-3b8299846d4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569866543 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3569866543
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1159851251
Short name T113
Test name
Test status
Simulation time 579275619 ps
CPU time 1.14 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201328 kb
Host smart-8be5f05d-3573-4bfe-a3b1-fc9da7452daa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159851251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1159851251
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1587662947
Short name T839
Test name
Test status
Simulation time 520539553 ps
CPU time 0.92 seconds
Started Jul 27 05:16:52 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201448 kb
Host smart-f5fb7a83-9d4b-47d4-84c5-fa4de6eec7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587662947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1587662947
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1871739441
Short name T125
Test name
Test status
Simulation time 2063927870 ps
CPU time 2.66 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 201492 kb
Host smart-9ac59bf3-7ee6-4a71-89e6-b26cd4ad7b54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871739441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1871739441
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2279853532
Short name T71
Test name
Test status
Simulation time 461369915 ps
CPU time 1.53 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201700 kb
Host smart-2864625f-1864-449f-aa22-5dfd1637dcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279853532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2279853532
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4144648526
Short name T905
Test name
Test status
Simulation time 8450361560 ps
CPU time 5.64 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201680 kb
Host smart-0095f949-9b2b-4c93-8621-46f462d531dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144648526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.4144648526
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3780253940
Short name T834
Test name
Test status
Simulation time 506889745 ps
CPU time 2.26 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201536 kb
Host smart-849df5fb-046c-4b74-bf05-dab4a5900015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780253940 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3780253940
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1459996923
Short name T918
Test name
Test status
Simulation time 364406404 ps
CPU time 0.99 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 201396 kb
Host smart-465454b8-1b9a-4e8e-91e5-8018236bcfe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459996923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1459996923
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2399700338
Short name T797
Test name
Test status
Simulation time 389183664 ps
CPU time 0.79 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201412 kb
Host smart-6767109e-8bc7-4d6d-992b-9df33ae2617c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399700338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2399700338
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3811407134
Short name T887
Test name
Test status
Simulation time 5011382339 ps
CPU time 3.78 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201752 kb
Host smart-93e28efc-fc4d-4ee7-b56b-97a8028079cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811407134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3811407134
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3081852694
Short name T75
Test name
Test status
Simulation time 423711724 ps
CPU time 1.81 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201700 kb
Host smart-89d55c94-33f7-4698-8397-49a55a4e6864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081852694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3081852694
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1742451015
Short name T846
Test name
Test status
Simulation time 8668518038 ps
CPU time 6.61 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:54 PM PDT 24
Peak memory 201712 kb
Host smart-a938ad12-0e2a-4a9a-b4de-93cd46ac16bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742451015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1742451015
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3490948756
Short name T120
Test name
Test status
Simulation time 839925192 ps
CPU time 1.89 seconds
Started Jul 27 05:16:15 PM PDT 24
Finished Jul 27 05:16:17 PM PDT 24
Peak memory 201684 kb
Host smart-3fd908cd-96f4-4ac5-a2be-414347fa6afc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490948756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3490948756
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2340263612
Short name T116
Test name
Test status
Simulation time 41466925710 ps
CPU time 132.65 seconds
Started Jul 27 05:16:11 PM PDT 24
Finished Jul 27 05:18:24 PM PDT 24
Peak memory 201624 kb
Host smart-bd1f7500-bc8d-485b-96b7-22795da013e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340263612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2340263612
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.971830916
Short name T883
Test name
Test status
Simulation time 899179119 ps
CPU time 1.36 seconds
Started Jul 27 05:16:13 PM PDT 24
Finished Jul 27 05:16:14 PM PDT 24
Peak memory 201408 kb
Host smart-1c973b75-050a-436e-8e6d-a9d4b138ff24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971830916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.971830916
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1980152147
Short name T841
Test name
Test status
Simulation time 477911763 ps
CPU time 2.02 seconds
Started Jul 27 05:16:13 PM PDT 24
Finished Jul 27 05:16:16 PM PDT 24
Peak memory 201504 kb
Host smart-d1c6075c-c7fe-4d3c-a2b2-3b5fa8e3d24f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980152147 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1980152147
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2034018589
Short name T866
Test name
Test status
Simulation time 385864825 ps
CPU time 1.17 seconds
Started Jul 27 05:16:16 PM PDT 24
Finished Jul 27 05:16:17 PM PDT 24
Peak memory 201448 kb
Host smart-afbf7a05-48f8-4db7-8dc7-050ef2c70008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034018589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2034018589
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2760651932
Short name T906
Test name
Test status
Simulation time 467255495 ps
CPU time 0.89 seconds
Started Jul 27 05:16:17 PM PDT 24
Finished Jul 27 05:16:18 PM PDT 24
Peak memory 201668 kb
Host smart-1243310d-9847-4d62-8270-eed74732d074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760651932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2760651932
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1710535996
Short name T835
Test name
Test status
Simulation time 2421884828 ps
CPU time 4.41 seconds
Started Jul 27 05:16:14 PM PDT 24
Finished Jul 27 05:16:18 PM PDT 24
Peak memory 201572 kb
Host smart-e89fd7a0-694c-4deb-95b5-310ae17c44f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710535996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1710535996
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.483314316
Short name T64
Test name
Test status
Simulation time 3935270081 ps
CPU time 9.88 seconds
Started Jul 27 05:16:12 PM PDT 24
Finished Jul 27 05:16:22 PM PDT 24
Peak memory 201820 kb
Host smart-719c1349-1269-499c-ab2d-2eb3f5ff13f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483314316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.483314316
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.82689790
Short name T829
Test name
Test status
Simulation time 344717498 ps
CPU time 0.95 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201452 kb
Host smart-15c869c9-4ccc-430b-8511-ee3e7258ea4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82689790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.82689790
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3227378637
Short name T842
Test name
Test status
Simulation time 377033341 ps
CPU time 0.85 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201436 kb
Host smart-b40e046d-b01f-492d-a06f-5b54ce7a8955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227378637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3227378637
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.33224999
Short name T843
Test name
Test status
Simulation time 392526261 ps
CPU time 1.35 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201452 kb
Host smart-29851910-c2bd-4f19-84a8-7552c3a46484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33224999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.33224999
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.217237778
Short name T897
Test name
Test status
Simulation time 455854585 ps
CPU time 1.49 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201468 kb
Host smart-92470890-6176-43c2-8e5a-2f5040976509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217237778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.217237778
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3701384054
Short name T805
Test name
Test status
Simulation time 406977651 ps
CPU time 0.91 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201424 kb
Host smart-877327bf-fd6e-4677-8776-6f578615d97d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701384054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3701384054
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2905478937
Short name T830
Test name
Test status
Simulation time 503943649 ps
CPU time 1.44 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:49 PM PDT 24
Peak memory 201396 kb
Host smart-41714136-db6d-479b-afc5-8ce3138d484c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905478937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2905478937
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.240543964
Short name T860
Test name
Test status
Simulation time 444265606 ps
CPU time 1.56 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201456 kb
Host smart-3ee87d93-de22-4ebe-8e0d-92036769a2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240543964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.240543964
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.630947001
Short name T806
Test name
Test status
Simulation time 483081724 ps
CPU time 1.17 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201444 kb
Host smart-d04330d9-7315-451c-b70c-3bfa5c1db57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630947001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.630947001
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2874912571
Short name T799
Test name
Test status
Simulation time 524962243 ps
CPU time 1.38 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201448 kb
Host smart-52c05ad0-5d16-4ef9-8cb7-ca418977e2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874912571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2874912571
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2466262416
Short name T822
Test name
Test status
Simulation time 353205109 ps
CPU time 1.33 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201436 kb
Host smart-b2a8f520-1162-47e3-9174-5358692a2b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466262416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2466262416
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3974676564
Short name T863
Test name
Test status
Simulation time 1204502204 ps
CPU time 5.46 seconds
Started Jul 27 05:16:14 PM PDT 24
Finished Jul 27 05:16:19 PM PDT 24
Peak memory 201616 kb
Host smart-0e29079d-2ce3-431b-b6f8-b44a5d7189ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974676564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3974676564
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.912911437
Short name T121
Test name
Test status
Simulation time 30987844826 ps
CPU time 37.27 seconds
Started Jul 27 05:16:16 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201744 kb
Host smart-438a42b8-992c-4467-bb3b-7b56081463ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912911437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.912911437
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2437249481
Short name T862
Test name
Test status
Simulation time 731940844 ps
CPU time 1 seconds
Started Jul 27 05:16:13 PM PDT 24
Finished Jul 27 05:16:14 PM PDT 24
Peak memory 201496 kb
Host smart-e8b050ff-27b7-4d25-8954-511f022d3314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437249481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2437249481
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.600626887
Short name T815
Test name
Test status
Simulation time 448766737 ps
CPU time 1.19 seconds
Started Jul 27 05:16:12 PM PDT 24
Finished Jul 27 05:16:14 PM PDT 24
Peak memory 201568 kb
Host smart-ee672a9d-0be1-4eb9-bd50-29757172d4b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600626887 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.600626887
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.354284621
Short name T118
Test name
Test status
Simulation time 607606036 ps
CPU time 0.96 seconds
Started Jul 27 05:16:13 PM PDT 24
Finished Jul 27 05:16:14 PM PDT 24
Peak memory 201368 kb
Host smart-a341777c-97c3-4dab-bbb6-b80f50ccd143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354284621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.354284621
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3514696129
Short name T844
Test name
Test status
Simulation time 378016724 ps
CPU time 0.85 seconds
Started Jul 27 05:16:18 PM PDT 24
Finished Jul 27 05:16:19 PM PDT 24
Peak memory 201668 kb
Host smart-b798cfd4-802d-4754-b416-8df0d2f2adcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514696129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3514696129
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3069128095
Short name T893
Test name
Test status
Simulation time 2609183238 ps
CPU time 1.37 seconds
Started Jul 27 05:16:14 PM PDT 24
Finished Jul 27 05:16:15 PM PDT 24
Peak memory 201572 kb
Host smart-41574320-6ee9-4c36-acca-9ce9639440ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069128095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3069128095
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3333880385
Short name T838
Test name
Test status
Simulation time 667693289 ps
CPU time 2.78 seconds
Started Jul 27 05:16:11 PM PDT 24
Finished Jul 27 05:16:14 PM PDT 24
Peak memory 210008 kb
Host smart-b46a95dd-fd54-4f58-a830-cad11bb7abd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333880385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3333880385
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1140921645
Short name T334
Test name
Test status
Simulation time 4385693739 ps
CPU time 9.22 seconds
Started Jul 27 05:16:12 PM PDT 24
Finished Jul 27 05:16:21 PM PDT 24
Peak memory 201712 kb
Host smart-9bef494e-6586-41c9-bdb0-3cd2f41e5c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140921645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1140921645
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2986972516
Short name T891
Test name
Test status
Simulation time 410762616 ps
CPU time 1.61 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201424 kb
Host smart-0c0bf504-be19-40cf-a0a5-3e86c85c8198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986972516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2986972516
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3124643966
Short name T796
Test name
Test status
Simulation time 347920920 ps
CPU time 1.43 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201408 kb
Host smart-0a80c5ea-7828-42a7-b463-1fa7785adc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124643966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3124643966
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.636048503
Short name T865
Test name
Test status
Simulation time 420514907 ps
CPU time 0.94 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201456 kb
Host smart-25c69fb3-bbc3-4292-b508-81a2040fd882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636048503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.636048503
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2766607109
Short name T810
Test name
Test status
Simulation time 529168740 ps
CPU time 1.23 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201404 kb
Host smart-2dc262bc-9f68-4f8f-93f0-2556fbdeed41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766607109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2766607109
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.745836890
Short name T904
Test name
Test status
Simulation time 359301663 ps
CPU time 1 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201356 kb
Host smart-3af8f1ac-a1fb-43f3-bd7c-69e16be7cd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745836890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.745836890
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.44796251
Short name T903
Test name
Test status
Simulation time 488486648 ps
CPU time 0.66 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201400 kb
Host smart-3015934b-d02d-4935-ad88-f6b94fb45c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44796251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.44796251
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3338609286
Short name T804
Test name
Test status
Simulation time 540346500 ps
CPU time 0.92 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:49 PM PDT 24
Peak memory 201488 kb
Host smart-ad7839d6-0ee4-4649-9fea-93d79cb25d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338609286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3338609286
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1227610653
Short name T807
Test name
Test status
Simulation time 419618050 ps
CPU time 0.72 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 201388 kb
Host smart-ab8c1d1b-6675-4ebc-b51f-73736f828735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227610653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1227610653
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.876272112
Short name T850
Test name
Test status
Simulation time 388556141 ps
CPU time 1.61 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201464 kb
Host smart-3d5baa11-d32d-4f0c-a0d6-81af5639dde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876272112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.876272112
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.842797810
Short name T803
Test name
Test status
Simulation time 524108447 ps
CPU time 0.96 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201348 kb
Host smart-76cd1dc2-abda-4b94-87de-6d97ae4bf7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842797810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.842797810
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3664085548
Short name T884
Test name
Test status
Simulation time 806843970 ps
CPU time 2.56 seconds
Started Jul 27 05:16:25 PM PDT 24
Finished Jul 27 05:16:28 PM PDT 24
Peak memory 201652 kb
Host smart-ff85d9f2-009f-4155-95f7-e90fcc3ee586
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664085548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3664085548
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1627152182
Short name T117
Test name
Test status
Simulation time 52576191226 ps
CPU time 36.54 seconds
Started Jul 27 05:16:12 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201680 kb
Host smart-f1b8acdc-f28a-4fc4-b55d-7006f8f704ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627152182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1627152182
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3199507978
Short name T831
Test name
Test status
Simulation time 1078814476 ps
CPU time 1.32 seconds
Started Jul 27 05:16:11 PM PDT 24
Finished Jul 27 05:16:13 PM PDT 24
Peak memory 201448 kb
Host smart-e33cc108-4039-4a73-b403-fef4d8f89a33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199507978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3199507978
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.927517520
Short name T820
Test name
Test status
Simulation time 499557921 ps
CPU time 2.05 seconds
Started Jul 27 05:16:28 PM PDT 24
Finished Jul 27 05:16:30 PM PDT 24
Peak memory 201428 kb
Host smart-d54c6237-68da-425e-8260-048abfe747cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927517520 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.927517520
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3891117954
Short name T890
Test name
Test status
Simulation time 462755733 ps
CPU time 1.77 seconds
Started Jul 27 05:16:14 PM PDT 24
Finished Jul 27 05:16:16 PM PDT 24
Peak memory 201452 kb
Host smart-a5c130cd-d590-4d20-bcb2-d477a90bc2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891117954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3891117954
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4246354997
Short name T898
Test name
Test status
Simulation time 292013760 ps
CPU time 1.29 seconds
Started Jul 27 05:16:15 PM PDT 24
Finished Jul 27 05:16:17 PM PDT 24
Peak memory 201412 kb
Host smart-db92b7b4-ab40-4325-ab58-d9e855c8d2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246354997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4246354997
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3253096345
Short name T894
Test name
Test status
Simulation time 2515163228 ps
CPU time 5.76 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:31 PM PDT 24
Peak memory 201556 kb
Host smart-e2ca1445-4d0b-4dd0-a149-261cd623cfdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253096345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3253096345
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2259132893
Short name T825
Test name
Test status
Simulation time 752315497 ps
CPU time 2.01 seconds
Started Jul 27 05:16:15 PM PDT 24
Finished Jul 27 05:16:18 PM PDT 24
Peak memory 218076 kb
Host smart-459b32b2-b507-4395-9262-13ae6fd26e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259132893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2259132893
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2165528218
Short name T853
Test name
Test status
Simulation time 8713239157 ps
CPU time 7.67 seconds
Started Jul 27 05:16:15 PM PDT 24
Finished Jul 27 05:16:23 PM PDT 24
Peak memory 201744 kb
Host smart-5456db21-3e1f-4c1a-b14c-7cbbf1590beb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165528218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2165528218
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1745863021
Short name T833
Test name
Test status
Simulation time 411894650 ps
CPU time 0.73 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201372 kb
Host smart-c00791dd-29db-4a6d-b771-e5bc8a1822ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745863021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1745863021
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3532908066
Short name T798
Test name
Test status
Simulation time 465781451 ps
CPU time 1.18 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:16:53 PM PDT 24
Peak memory 201420 kb
Host smart-5ad79ad6-8f52-448b-96ef-dc3413f4aee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532908066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3532908066
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1001204057
Short name T811
Test name
Test status
Simulation time 385630339 ps
CPU time 1.47 seconds
Started Jul 27 05:16:46 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201444 kb
Host smart-0cb4f991-5958-4e8d-bc57-7edbec33e20e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001204057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1001204057
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2719105075
Short name T809
Test name
Test status
Simulation time 451476663 ps
CPU time 1.1 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201420 kb
Host smart-91e89119-bf86-495d-b567-0889deb4a8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719105075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2719105075
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4255691160
Short name T802
Test name
Test status
Simulation time 554511272 ps
CPU time 0.97 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201408 kb
Host smart-417deb70-340d-4080-b5fd-eb72a3788091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255691160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4255691160
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2090314494
Short name T801
Test name
Test status
Simulation time 513050001 ps
CPU time 1.75 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201444 kb
Host smart-59aa39e1-73ef-4ab9-a659-336ab62538b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090314494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2090314494
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2008576874
Short name T856
Test name
Test status
Simulation time 438518057 ps
CPU time 1.6 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201452 kb
Host smart-80d76186-9440-497d-893a-b7e03dc0dfbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008576874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2008576874
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1648012380
Short name T889
Test name
Test status
Simulation time 368934952 ps
CPU time 1.01 seconds
Started Jul 27 05:16:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 201400 kb
Host smart-e8c0d1f2-b66b-4d12-a071-273d5cc974dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648012380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1648012380
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1479073473
Short name T869
Test name
Test status
Simulation time 277803803 ps
CPU time 1.29 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 201356 kb
Host smart-f4ebb575-da5b-4e7c-b139-0292d5e4b320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479073473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1479073473
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.612368265
Short name T808
Test name
Test status
Simulation time 278778658 ps
CPU time 1.2 seconds
Started Jul 27 05:16:49 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 201120 kb
Host smart-cc066004-f18a-4f25-a811-8fc252fc41bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612368265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.612368265
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.706545876
Short name T859
Test name
Test status
Simulation time 532435342 ps
CPU time 2.16 seconds
Started Jul 27 05:16:22 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201544 kb
Host smart-917ec672-d278-4ee4-8e67-fd187be357f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706545876 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.706545876
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2627796231
Short name T123
Test name
Test status
Simulation time 545124159 ps
CPU time 1.38 seconds
Started Jul 27 05:16:30 PM PDT 24
Finished Jul 27 05:16:31 PM PDT 24
Peak memory 201340 kb
Host smart-8125df3d-12cf-4c9a-8062-79f585bcb2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627796231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2627796231
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.963944301
Short name T800
Test name
Test status
Simulation time 449855045 ps
CPU time 1.13 seconds
Started Jul 27 05:16:26 PM PDT 24
Finished Jul 27 05:16:27 PM PDT 24
Peak memory 201444 kb
Host smart-b70aaa3a-bd11-4ec4-9a71-6c910f528bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963944301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.963944301
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1143201589
Short name T821
Test name
Test status
Simulation time 2606057914 ps
CPU time 9.21 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:32 PM PDT 24
Peak memory 201572 kb
Host smart-6012a3d0-1bdf-497e-900b-bc703ebca78e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143201589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1143201589
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3293698700
Short name T899
Test name
Test status
Simulation time 558781239 ps
CPU time 2.53 seconds
Started Jul 27 05:16:25 PM PDT 24
Finished Jul 27 05:16:27 PM PDT 24
Peak memory 201736 kb
Host smart-91598296-4cc7-49f1-ba06-369d100de0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293698700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3293698700
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1886539277
Short name T824
Test name
Test status
Simulation time 595026543 ps
CPU time 1.55 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:24 PM PDT 24
Peak memory 209968 kb
Host smart-a8406b02-8346-4592-8046-471a58e8c1b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886539277 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1886539277
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1141814257
Short name T111
Test name
Test status
Simulation time 396729055 ps
CPU time 1.12 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201376 kb
Host smart-3f7dcead-1b47-4828-83e3-b25995ec5361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141814257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1141814257
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.914306536
Short name T852
Test name
Test status
Simulation time 512862780 ps
CPU time 1.17 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:26 PM PDT 24
Peak memory 201408 kb
Host smart-5e651918-810d-48a8-902d-c2cb452f78b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914306536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.914306536
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3762283818
Short name T882
Test name
Test status
Simulation time 2778472550 ps
CPU time 7.32 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:32 PM PDT 24
Peak memory 201512 kb
Host smart-cac7fc48-bdf3-4e55-b6ce-a2f75bcef9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762283818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3762283818
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2118429086
Short name T881
Test name
Test status
Simulation time 568344727 ps
CPU time 2.84 seconds
Started Jul 27 05:16:22 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 217644 kb
Host smart-d11ae8a3-3f33-468b-821b-951d700d71f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118429086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2118429086
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.477662892
Short name T858
Test name
Test status
Simulation time 8602668450 ps
CPU time 20.39 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:44 PM PDT 24
Peak memory 201704 kb
Host smart-7da16e44-4cc3-42c3-8d76-df024bee171d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477662892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.477662892
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3506536108
Short name T63
Test name
Test status
Simulation time 322998594 ps
CPU time 1.66 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201576 kb
Host smart-ec1fe587-5cbd-4904-8f54-c3b8be73aecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506536108 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3506536108
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2615173661
Short name T908
Test name
Test status
Simulation time 425542538 ps
CPU time 1.77 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201444 kb
Host smart-3451ff43-647f-4b6f-b99d-7acac12379a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615173661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2615173661
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4078921151
Short name T849
Test name
Test status
Simulation time 317036890 ps
CPU time 0.85 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:24 PM PDT 24
Peak memory 201372 kb
Host smart-7fc40487-2c76-4c56-ab46-16b7e0487ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078921151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4078921151
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1295169456
Short name T127
Test name
Test status
Simulation time 4178208831 ps
CPU time 5.75 seconds
Started Jul 27 05:16:29 PM PDT 24
Finished Jul 27 05:16:35 PM PDT 24
Peak memory 201720 kb
Host smart-13d334fd-766c-42a1-b227-cf7c2f1e60cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295169456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1295169456
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1161672087
Short name T72
Test name
Test status
Simulation time 414675535 ps
CPU time 2.85 seconds
Started Jul 27 05:16:25 PM PDT 24
Finished Jul 27 05:16:28 PM PDT 24
Peak memory 218076 kb
Host smart-c4018aff-fa45-4bb8-8b3d-fb1b21ad3ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161672087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1161672087
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2432506944
Short name T886
Test name
Test status
Simulation time 8278873154 ps
CPU time 13.79 seconds
Started Jul 27 05:16:25 PM PDT 24
Finished Jul 27 05:16:39 PM PDT 24
Peak memory 201724 kb
Host smart-4f6b0fd2-a604-4b9e-a510-99a30433f4be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432506944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2432506944
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.325204340
Short name T915
Test name
Test status
Simulation time 593432168 ps
CPU time 1.67 seconds
Started Jul 27 05:16:29 PM PDT 24
Finished Jul 27 05:16:30 PM PDT 24
Peak memory 201416 kb
Host smart-4e8b0604-1cdf-4668-acfe-9abd3528a0f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325204340 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.325204340
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.673750909
Short name T875
Test name
Test status
Simulation time 571823712 ps
CPU time 2.01 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:29 PM PDT 24
Peak memory 201516 kb
Host smart-c6bd7bd9-56c9-464e-8d29-a7d2c368799a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673750909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.673750909
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2065254206
Short name T910
Test name
Test status
Simulation time 332471120 ps
CPU time 0.9 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201416 kb
Host smart-e720bf41-de90-4735-bee5-102689d25860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065254206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2065254206
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1938636040
Short name T55
Test name
Test status
Simulation time 4905674381 ps
CPU time 11.94 seconds
Started Jul 27 05:16:29 PM PDT 24
Finished Jul 27 05:16:41 PM PDT 24
Peak memory 201740 kb
Host smart-68c6fdc8-e1b0-4b29-bb44-a74562ecfb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938636040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1938636040
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2242883068
Short name T909
Test name
Test status
Simulation time 662032281 ps
CPU time 2.97 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:26 PM PDT 24
Peak memory 209896 kb
Host smart-171754c4-d59c-4f23-b556-de8a43aee355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242883068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2242883068
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.566636532
Short name T895
Test name
Test status
Simulation time 4519330208 ps
CPU time 12.2 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:40 PM PDT 24
Peak memory 201808 kb
Host smart-09f14642-d930-4f71-ad69-d9caa6feb544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566636532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.566636532
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1294458485
Short name T880
Test name
Test status
Simulation time 662597966 ps
CPU time 0.96 seconds
Started Jul 27 05:16:23 PM PDT 24
Finished Jul 27 05:16:24 PM PDT 24
Peak memory 201492 kb
Host smart-203afda7-542f-4ead-8b48-dbfd4c7b19d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294458485 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1294458485
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2915136787
Short name T115
Test name
Test status
Simulation time 459563405 ps
CPU time 0.95 seconds
Started Jul 27 05:16:25 PM PDT 24
Finished Jul 27 05:16:26 PM PDT 24
Peak memory 201424 kb
Host smart-cd9284ff-640e-4c89-91c8-50ec91ef0f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915136787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2915136787
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1892161769
Short name T828
Test name
Test status
Simulation time 339895294 ps
CPU time 0.85 seconds
Started Jul 27 05:16:24 PM PDT 24
Finished Jul 27 05:16:25 PM PDT 24
Peak memory 201416 kb
Host smart-1c62d6f2-f956-4830-898d-3bad66da94d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892161769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1892161769
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3294537339
Short name T126
Test name
Test status
Simulation time 2255500594 ps
CPU time 2.49 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:30 PM PDT 24
Peak memory 201648 kb
Host smart-a1228751-a491-44ce-85bf-d283ce831f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294537339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3294537339
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2486043861
Short name T69
Test name
Test status
Simulation time 552178168 ps
CPU time 2.75 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:30 PM PDT 24
Peak memory 201880 kb
Host smart-491ab974-9534-439d-ae1e-0505b89ed326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486043861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2486043861
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3386610707
Short name T917
Test name
Test status
Simulation time 4438747720 ps
CPU time 7.65 seconds
Started Jul 27 05:16:27 PM PDT 24
Finished Jul 27 05:16:35 PM PDT 24
Peak memory 201836 kb
Host smart-b7a45007-87ea-4837-a5b5-ed40a4a9c9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386610707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3386610707
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1132984424
Short name T449
Test name
Test status
Simulation time 320239745 ps
CPU time 0.98 seconds
Started Jul 27 06:35:18 PM PDT 24
Finished Jul 27 06:35:19 PM PDT 24
Peak memory 200968 kb
Host smart-7f1da4ea-9e25-4d75-b7ff-9684f16fa3f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132984424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1132984424
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1125214518
Short name T264
Test name
Test status
Simulation time 390937946146 ps
CPU time 189.12 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:38:25 PM PDT 24
Peak memory 201168 kb
Host smart-211211f2-4ee1-4fbb-979b-cec298e9a4a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125214518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1125214518
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3341850784
Short name T241
Test name
Test status
Simulation time 163471229261 ps
CPU time 368.97 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:41:23 PM PDT 24
Peak memory 201300 kb
Host smart-e2cf9b1d-841a-4e91-8205-ce73a6a1ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341850784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3341850784
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.262616564
Short name T176
Test name
Test status
Simulation time 492365123356 ps
CPU time 280.63 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:39:57 PM PDT 24
Peak memory 201236 kb
Host smart-9d1758f0-c886-4533-b7a2-a159b49c6d2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262616564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.262616564
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.752531617
Short name T492
Test name
Test status
Simulation time 161661179066 ps
CPU time 72.81 seconds
Started Jul 27 06:35:18 PM PDT 24
Finished Jul 27 06:36:31 PM PDT 24
Peak memory 201256 kb
Host smart-79d0a88f-c76c-450a-bf64-ba8c3759fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752531617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.752531617
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3087397219
Short name T472
Test name
Test status
Simulation time 326132187772 ps
CPU time 701.81 seconds
Started Jul 27 06:35:19 PM PDT 24
Finished Jul 27 06:47:01 PM PDT 24
Peak memory 201216 kb
Host smart-9223713a-3b33-4391-b349-cddddb5d1e63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087397219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3087397219
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.237409999
Short name T705
Test name
Test status
Simulation time 196253200578 ps
CPU time 112.77 seconds
Started Jul 27 06:35:12 PM PDT 24
Finished Jul 27 06:37:04 PM PDT 24
Peak memory 201200 kb
Host smart-15326549-e789-466e-a17e-8da9b8a33abf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237409999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.237409999
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4227308963
Short name T549
Test name
Test status
Simulation time 205782208496 ps
CPU time 223.67 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:39:00 PM PDT 24
Peak memory 201252 kb
Host smart-903bb5d1-8d40-47b7-8b59-fa20b0467033
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227308963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4227308963
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.919484063
Short name T585
Test name
Test status
Simulation time 111625351750 ps
CPU time 412.84 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:42:09 PM PDT 24
Peak memory 201700 kb
Host smart-6900befa-f9bd-4fae-939e-8cd7c007dd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919484063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.919484063
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3622546278
Short name T455
Test name
Test status
Simulation time 26972840821 ps
CPU time 57.54 seconds
Started Jul 27 06:35:17 PM PDT 24
Finished Jul 27 06:36:15 PM PDT 24
Peak memory 201056 kb
Host smart-7e945f9f-6ad7-41d7-ad52-65c8ae444b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622546278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3622546278
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1239269867
Short name T445
Test name
Test status
Simulation time 4713382743 ps
CPU time 4.24 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:21 PM PDT 24
Peak memory 200972 kb
Host smart-9f57995e-544e-4d0d-892b-fb82cf98dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239269867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1239269867
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2813350633
Short name T6
Test name
Test status
Simulation time 5942636974 ps
CPU time 14.96 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:35:30 PM PDT 24
Peak memory 201032 kb
Host smart-2666ecc3-7d91-4872-8696-b64ee3b87435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813350633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2813350633
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1608384412
Short name T342
Test name
Test status
Simulation time 135111516915 ps
CPU time 690.51 seconds
Started Jul 27 06:35:13 PM PDT 24
Finished Jul 27 06:46:44 PM PDT 24
Peak memory 217984 kb
Host smart-ddf26380-b380-4eac-908b-cee95ff63a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608384412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1608384412
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.430217482
Short name T23
Test name
Test status
Simulation time 43964246403 ps
CPU time 104.33 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:36:59 PM PDT 24
Peak memory 217232 kb
Host smart-b505445c-6fbc-4664-bfe3-e31ff187e87c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430217482 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.430217482
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1518945805
Short name T647
Test name
Test status
Simulation time 477471015 ps
CPU time 1.77 seconds
Started Jul 27 06:35:27 PM PDT 24
Finished Jul 27 06:35:28 PM PDT 24
Peak memory 201000 kb
Host smart-0eab5772-9bc2-438e-8547-c5b78730ac6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518945805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1518945805
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1031087796
Short name T220
Test name
Test status
Simulation time 344513715107 ps
CPU time 204.9 seconds
Started Jul 27 06:35:22 PM PDT 24
Finished Jul 27 06:38:47 PM PDT 24
Peak memory 201220 kb
Host smart-eb4cc263-074c-49c6-ad0e-030e4dc3c642
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031087796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1031087796
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3681481516
Short name T329
Test name
Test status
Simulation time 166956492958 ps
CPU time 364.34 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:41:29 PM PDT 24
Peak memory 201296 kb
Host smart-4b338d33-3def-4916-8317-6161592b0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681481516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3681481516
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3856561023
Short name T178
Test name
Test status
Simulation time 491330320338 ps
CPU time 153.26 seconds
Started Jul 27 06:35:27 PM PDT 24
Finished Jul 27 06:38:00 PM PDT 24
Peak memory 201296 kb
Host smart-7765b54e-437e-4234-8466-6cba10026738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856561023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3856561023
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.533681852
Short name T363
Test name
Test status
Simulation time 165329337331 ps
CPU time 90.88 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:36:55 PM PDT 24
Peak memory 201236 kb
Host smart-4631e427-5e41-49e0-94dc-604e89041952
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=533681852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.533681852
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1512588720
Short name T142
Test name
Test status
Simulation time 488309595176 ps
CPU time 163.1 seconds
Started Jul 27 06:35:18 PM PDT 24
Finished Jul 27 06:38:01 PM PDT 24
Peak memory 201208 kb
Host smart-4978bfbf-1de8-4891-9f1b-6e725c9b22c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512588720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1512588720
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2037031241
Short name T658
Test name
Test status
Simulation time 161406830653 ps
CPU time 99.3 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:36:54 PM PDT 24
Peak memory 201232 kb
Host smart-6b16124f-0870-48a6-8020-95f752b7045f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037031241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2037031241
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1016720418
Short name T163
Test name
Test status
Simulation time 423673587572 ps
CPU time 178.24 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:38:21 PM PDT 24
Peak memory 201172 kb
Host smart-b623fa38-dc9e-49f4-9709-40b4079ebd43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016720418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1016720418
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1467058937
Short name T478
Test name
Test status
Simulation time 188248796862 ps
CPU time 217.85 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:39:03 PM PDT 24
Peak memory 201156 kb
Host smart-0d64299d-5ee9-4789-b7a3-a4e5492fa340
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467058937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1467058937
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.709798070
Short name T438
Test name
Test status
Simulation time 82748911199 ps
CPU time 417.32 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:42:22 PM PDT 24
Peak memory 201704 kb
Host smart-28eca1a7-294a-4a5a-9b5e-5d9b90db8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709798070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.709798070
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2539341858
Short name T372
Test name
Test status
Simulation time 39372214013 ps
CPU time 46.77 seconds
Started Jul 27 06:35:29 PM PDT 24
Finished Jul 27 06:36:16 PM PDT 24
Peak memory 201096 kb
Host smart-b1261a86-82b5-4006-92d4-c5904303d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539341858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2539341858
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.54126767
Short name T88
Test name
Test status
Simulation time 4391354910 ps
CPU time 5.59 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:35:29 PM PDT 24
Peak memory 201068 kb
Host smart-eddd684a-c5ca-443a-afbf-c9b0f5f92bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54126767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.54126767
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.730895348
Short name T65
Test name
Test status
Simulation time 4096459904 ps
CPU time 5.51 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:35:30 PM PDT 24
Peak memory 216872 kb
Host smart-e30d62fb-8a9d-4688-962d-768e2526e4da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730895348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.730895348
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1731803280
Short name T581
Test name
Test status
Simulation time 5703518019 ps
CPU time 14.22 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:28 PM PDT 24
Peak memory 201100 kb
Host smart-08d8852b-6047-490a-b504-cfd9d2f08ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731803280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1731803280
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3404048878
Short name T153
Test name
Test status
Simulation time 543371481045 ps
CPU time 458.39 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:43:04 PM PDT 24
Peak memory 201228 kb
Host smart-37675d76-a587-4750-948e-ce97dc021131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404048878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3404048878
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4133903420
Short name T36
Test name
Test status
Simulation time 43958610719 ps
CPU time 68.23 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:36:33 PM PDT 24
Peak memory 209620 kb
Host smart-2b92d938-f44f-4a90-aa10-6692720993f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133903420 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4133903420
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1619093226
Short name T729
Test name
Test status
Simulation time 461874109 ps
CPU time 1.14 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:35:51 PM PDT 24
Peak memory 201016 kb
Host smart-dd3b5b31-5835-41bc-b990-368a1cb09a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619093226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1619093226
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4216132151
Short name T292
Test name
Test status
Simulation time 164986430940 ps
CPU time 18.72 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:36:07 PM PDT 24
Peak memory 201284 kb
Host smart-03d0f92d-9c1e-4b43-8537-9cdb9fa24527
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216132151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4216132151
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3061722563
Short name T46
Test name
Test status
Simulation time 350236856105 ps
CPU time 167.52 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:38:29 PM PDT 24
Peak memory 201164 kb
Host smart-3264b008-b19c-41bb-8cab-69f12b797110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061722563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3061722563
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2804542356
Short name T101
Test name
Test status
Simulation time 158040544620 ps
CPU time 392.48 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:42:22 PM PDT 24
Peak memory 201252 kb
Host smart-19b720ad-677d-4f84-927f-5f7dc680bb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804542356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2804542356
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2952113223
Short name T510
Test name
Test status
Simulation time 163890499234 ps
CPU time 357.72 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:41:46 PM PDT 24
Peak memory 201280 kb
Host smart-aa47206d-8d51-4163-90ea-6c86f52fae16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952113223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2952113223
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1060499425
Short name T224
Test name
Test status
Simulation time 329199502326 ps
CPU time 391.24 seconds
Started Jul 27 06:35:42 PM PDT 24
Finished Jul 27 06:42:13 PM PDT 24
Peak memory 201216 kb
Host smart-9767fde4-d953-436a-91d0-86702b5d19e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060499425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1060499425
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.264789758
Short name T563
Test name
Test status
Simulation time 497546639513 ps
CPU time 248.34 seconds
Started Jul 27 06:35:43 PM PDT 24
Finished Jul 27 06:39:51 PM PDT 24
Peak memory 201212 kb
Host smart-38863782-f602-4014-b6e7-7f24a8ade56e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=264789758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.264789758
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3050767360
Short name T237
Test name
Test status
Simulation time 164841792560 ps
CPU time 346.66 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:41:35 PM PDT 24
Peak memory 201220 kb
Host smart-cba20a75-a44b-4aa6-a24a-06833481e764
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050767360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3050767360
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.995510454
Short name T497
Test name
Test status
Simulation time 201971627470 ps
CPU time 305.82 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:40:56 PM PDT 24
Peak memory 201216 kb
Host smart-696fcca4-a456-4d2c-bcd9-3c23d1080eea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995510454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.995510454
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.527419477
Short name T353
Test name
Test status
Simulation time 83508492308 ps
CPU time 488.07 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:43:58 PM PDT 24
Peak memory 201692 kb
Host smart-c07ec2b3-d265-4130-b337-0ea7a156535b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527419477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.527419477
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2466013618
Short name T710
Test name
Test status
Simulation time 36093386692 ps
CPU time 8.34 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:35:56 PM PDT 24
Peak memory 201040 kb
Host smart-8a23ab1d-683b-4805-abc9-481cd656e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466013618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2466013618
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1522794427
Short name T387
Test name
Test status
Simulation time 4620085876 ps
CPU time 3.36 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:35:53 PM PDT 24
Peak memory 201052 kb
Host smart-47bccb19-ed07-4f4a-a5fa-322c2eaa9593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522794427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1522794427
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.4079382207
Short name T105
Test name
Test status
Simulation time 5620304541 ps
CPU time 3.77 seconds
Started Jul 27 06:35:42 PM PDT 24
Finished Jul 27 06:35:46 PM PDT 24
Peak memory 201100 kb
Host smart-849cebeb-7b3b-42ae-84f2-2096787b6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079382207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4079382207
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1251484137
Short name T253
Test name
Test status
Simulation time 78824320984 ps
CPU time 156.61 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:38:26 PM PDT 24
Peak memory 209556 kb
Host smart-b4058769-e11f-4aa4-aa95-3e4b6a033245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251484137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1251484137
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1663361477
Short name T612
Test name
Test status
Simulation time 453743335 ps
CPU time 0.92 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:35:49 PM PDT 24
Peak memory 201000 kb
Host smart-01fe8f4c-141b-41b2-8404-5779027f7ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663361477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1663361477
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2541976163
Short name T626
Test name
Test status
Simulation time 498960889865 ps
CPU time 357.08 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:41:46 PM PDT 24
Peak memory 201192 kb
Host smart-1efefaec-177f-4741-a538-20364d57b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541976163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2541976163
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3748556233
Short name T789
Test name
Test status
Simulation time 161453760849 ps
CPU time 364.47 seconds
Started Jul 27 06:35:44 PM PDT 24
Finished Jul 27 06:41:49 PM PDT 24
Peak memory 201176 kb
Host smart-2db75d60-2483-4a9a-a203-2bfee26bf943
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748556233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3748556233
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2270404590
Short name T437
Test name
Test status
Simulation time 159453520075 ps
CPU time 94.24 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:37:22 PM PDT 24
Peak memory 201188 kb
Host smart-5b30a9ef-1c98-4771-9286-355786e32432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270404590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2270404590
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1944495592
Short name T732
Test name
Test status
Simulation time 165636345738 ps
CPU time 193.12 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:38:55 PM PDT 24
Peak memory 201276 kb
Host smart-ead5d49e-6d89-42a1-a707-50aab0c5e210
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944495592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1944495592
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.861397016
Short name T277
Test name
Test status
Simulation time 544814586130 ps
CPU time 1193.15 seconds
Started Jul 27 06:35:40 PM PDT 24
Finished Jul 27 06:55:34 PM PDT 24
Peak memory 201196 kb
Host smart-fb6b218f-8209-4cc6-93f4-426e107ce789
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861397016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.861397016
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3390185873
Short name T544
Test name
Test status
Simulation time 406313871691 ps
CPU time 843.34 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:49:48 PM PDT 24
Peak memory 201208 kb
Host smart-1fdb649d-3978-48c7-98eb-738ca7eff857
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390185873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3390185873
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2233926726
Short name T392
Test name
Test status
Simulation time 32158185623 ps
CPU time 18.48 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:36:08 PM PDT 24
Peak memory 201072 kb
Host smart-d69f66f5-d6b4-4b0e-851f-0f986cee8420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233926726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2233926726
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.85966187
Short name T547
Test name
Test status
Simulation time 5263378762 ps
CPU time 14.1 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:36:03 PM PDT 24
Peak memory 201032 kb
Host smart-dba578a3-350b-4932-b992-c7ade93a2385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85966187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.85966187
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3724743217
Short name T573
Test name
Test status
Simulation time 5684621151 ps
CPU time 11.56 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:35:52 PM PDT 24
Peak memory 201104 kb
Host smart-8bf4a191-c040-4e69-879f-8255535898f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724743217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3724743217
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3694656398
Short name T167
Test name
Test status
Simulation time 567151094913 ps
CPU time 1990.81 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 07:08:59 PM PDT 24
Peak memory 201668 kb
Host smart-212d7bf0-bd93-431b-a87e-237691c6769f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694656398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3694656398
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3826754154
Short name T205
Test name
Test status
Simulation time 83224669757 ps
CPU time 262.4 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:40:10 PM PDT 24
Peak memory 210000 kb
Host smart-88d5768a-3813-4769-bd32-68c465499fe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826754154 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3826754154
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.582935099
Short name T428
Test name
Test status
Simulation time 526776283 ps
CPU time 1.87 seconds
Started Jul 27 06:35:56 PM PDT 24
Finished Jul 27 06:35:58 PM PDT 24
Peak memory 200984 kb
Host smart-a2970797-32cf-46e4-9b82-caa1512c5e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582935099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.582935099
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1622730170
Short name T741
Test name
Test status
Simulation time 519727450137 ps
CPU time 316.01 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:41:06 PM PDT 24
Peak memory 201224 kb
Host smart-e12fe806-6f43-4cad-b65a-b2f5cb80dddd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622730170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1622730170
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.747710517
Short name T738
Test name
Test status
Simulation time 328883563240 ps
CPU time 224.54 seconds
Started Jul 27 06:35:42 PM PDT 24
Finished Jul 27 06:39:26 PM PDT 24
Peak memory 201160 kb
Host smart-2a96d77c-08b9-4997-ad7a-9b0e385330f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747710517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.747710517
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2482689027
Short name T430
Test name
Test status
Simulation time 326624107678 ps
CPU time 767.74 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:48:38 PM PDT 24
Peak memory 201268 kb
Host smart-34ccffee-4d25-494d-b1da-79f79a03b740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482689027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2482689027
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4177018727
Short name T193
Test name
Test status
Simulation time 491525514237 ps
CPU time 569.29 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:45:15 PM PDT 24
Peak memory 201188 kb
Host smart-d62e373a-64e3-44e5-9d3d-9ba134c20834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177018727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4177018727
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3701983882
Short name T360
Test name
Test status
Simulation time 335185149185 ps
CPU time 418.43 seconds
Started Jul 27 06:35:43 PM PDT 24
Finished Jul 27 06:42:41 PM PDT 24
Peak memory 201140 kb
Host smart-f5158783-f7ca-4862-980d-759ab888149f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701983882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3701983882
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.127984403
Short name T748
Test name
Test status
Simulation time 200710994080 ps
CPU time 118.56 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:37:47 PM PDT 24
Peak memory 201224 kb
Host smart-c2c379de-3eef-48b6-ac16-c3fd48aa4159
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127984403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.127984403
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2782406608
Short name T740
Test name
Test status
Simulation time 106956388490 ps
CPU time 394.4 seconds
Started Jul 27 06:35:52 PM PDT 24
Finished Jul 27 06:42:26 PM PDT 24
Peak memory 201692 kb
Host smart-f89fe5b6-b8be-4367-9d00-a94cc5b7a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782406608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2782406608
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1935758635
Short name T759
Test name
Test status
Simulation time 35026611424 ps
CPU time 15.65 seconds
Started Jul 27 06:35:53 PM PDT 24
Finished Jul 27 06:36:09 PM PDT 24
Peak memory 201052 kb
Host smart-ffbef42d-6b2f-4db6-89a5-f167b03af09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935758635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1935758635
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3167924946
Short name T373
Test name
Test status
Simulation time 3213398944 ps
CPU time 3.92 seconds
Started Jul 27 06:35:51 PM PDT 24
Finished Jul 27 06:35:55 PM PDT 24
Peak memory 201012 kb
Host smart-e2ccf3f9-799a-424c-a774-27821dd3cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167924946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3167924946
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.213645383
Short name T188
Test name
Test status
Simulation time 6028463483 ps
CPU time 6.17 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:35:55 PM PDT 24
Peak memory 201096 kb
Host smart-7f064833-c899-401f-843b-07caeaf29323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213645383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.213645383
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1298812182
Short name T567
Test name
Test status
Simulation time 365767492325 ps
CPU time 836.25 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:49:46 PM PDT 24
Peak memory 201200 kb
Host smart-0cfd9244-fb46-45d6-ad36-a4e398dd14ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298812182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1298812182
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1565224567
Short name T68
Test name
Test status
Simulation time 89252822244 ps
CPU time 103.46 seconds
Started Jul 27 06:35:57 PM PDT 24
Finished Jul 27 06:37:40 PM PDT 24
Peak memory 209588 kb
Host smart-c212c308-a99a-4a1a-a02b-0ac252352006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565224567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1565224567
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3874377575
Short name T304
Test name
Test status
Simulation time 522859919979 ps
CPU time 1111.66 seconds
Started Jul 27 06:36:04 PM PDT 24
Finished Jul 27 06:54:35 PM PDT 24
Peak memory 201240 kb
Host smart-7620a704-8920-47b8-a882-33a489fa98a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874377575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3874377575
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4124503022
Short name T618
Test name
Test status
Simulation time 491867114872 ps
CPU time 533.56 seconds
Started Jul 27 06:35:58 PM PDT 24
Finished Jul 27 06:44:51 PM PDT 24
Peak memory 201264 kb
Host smart-ea04e0ce-ca54-4ad9-aa6a-79684a549e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124503022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4124503022
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2250995284
Short name T755
Test name
Test status
Simulation time 339211729823 ps
CPU time 763.19 seconds
Started Jul 27 06:36:02 PM PDT 24
Finished Jul 27 06:48:46 PM PDT 24
Peak memory 201228 kb
Host smart-2050b65b-a963-4a12-8e42-2c1e13c1ec6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250995284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2250995284
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2784459278
Short name T180
Test name
Test status
Simulation time 331461316546 ps
CPU time 407.59 seconds
Started Jul 27 06:35:51 PM PDT 24
Finished Jul 27 06:42:39 PM PDT 24
Peak memory 201140 kb
Host smart-30a53201-0998-45fc-bc3a-3594ebeb7b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784459278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2784459278
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3720141446
Short name T358
Test name
Test status
Simulation time 334611306994 ps
CPU time 761.4 seconds
Started Jul 27 06:36:01 PM PDT 24
Finished Jul 27 06:48:43 PM PDT 24
Peak memory 201204 kb
Host smart-d06a1ce6-bee5-47e6-a33a-ff9038284548
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720141446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3720141446
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1260438039
Short name T680
Test name
Test status
Simulation time 415701074972 ps
CPU time 886.3 seconds
Started Jul 27 06:36:03 PM PDT 24
Finished Jul 27 06:50:50 PM PDT 24
Peak memory 201244 kb
Host smart-9d7c877c-5b3f-4244-aa77-612495891543
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260438039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1260438039
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2217084394
Short name T52
Test name
Test status
Simulation time 130046832740 ps
CPU time 504.51 seconds
Started Jul 27 06:36:01 PM PDT 24
Finished Jul 27 06:44:25 PM PDT 24
Peak memory 201632 kb
Host smart-4cb8315f-379f-40ff-bbfa-901a1d2cc183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217084394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2217084394
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3441355665
Short name T502
Test name
Test status
Simulation time 38907926934 ps
CPU time 88.13 seconds
Started Jul 27 06:35:57 PM PDT 24
Finished Jul 27 06:37:26 PM PDT 24
Peak memory 201028 kb
Host smart-6e432075-47da-48d3-963c-994a852929d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441355665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3441355665
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2727800647
Short name T559
Test name
Test status
Simulation time 3163672390 ps
CPU time 2.91 seconds
Started Jul 27 06:35:59 PM PDT 24
Finished Jul 27 06:36:02 PM PDT 24
Peak memory 201096 kb
Host smart-0fdfc662-d63e-42f6-91c5-bf82286153db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727800647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2727800647
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2710564111
Short name T443
Test name
Test status
Simulation time 5746452210 ps
CPU time 11.15 seconds
Started Jul 27 06:35:56 PM PDT 24
Finished Jul 27 06:36:08 PM PDT 24
Peak memory 201064 kb
Host smart-1be89a53-86d4-434a-8226-0d7156697790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710564111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2710564111
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3717267595
Short name T203
Test name
Test status
Simulation time 368304261656 ps
CPU time 141.04 seconds
Started Jul 27 06:35:58 PM PDT 24
Finished Jul 27 06:38:19 PM PDT 24
Peak memory 201176 kb
Host smart-35618391-a850-40df-8020-a464a0f31ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717267595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3717267595
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2866347615
Short name T40
Test name
Test status
Simulation time 107097662246 ps
CPU time 59.54 seconds
Started Jul 27 06:36:05 PM PDT 24
Finished Jul 27 06:37:05 PM PDT 24
Peak memory 209516 kb
Host smart-4606e2ee-743b-4289-a4b7-a6fbec23b587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866347615 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2866347615
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3924267964
Short name T356
Test name
Test status
Simulation time 454240561 ps
CPU time 1.68 seconds
Started Jul 27 06:36:07 PM PDT 24
Finished Jul 27 06:36:09 PM PDT 24
Peak memory 200980 kb
Host smart-48a50ff4-e97e-4f98-ab24-569b097e3783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924267964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3924267964
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2183986009
Short name T219
Test name
Test status
Simulation time 161691378602 ps
CPU time 375.94 seconds
Started Jul 27 06:35:59 PM PDT 24
Finished Jul 27 06:42:15 PM PDT 24
Peak memory 201148 kb
Host smart-f2f77a99-cd2f-4014-9761-565dc10c4175
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183986009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2183986009
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3039402721
Short name T81
Test name
Test status
Simulation time 161198277658 ps
CPU time 101.89 seconds
Started Jul 27 06:35:59 PM PDT 24
Finished Jul 27 06:37:41 PM PDT 24
Peak memory 201300 kb
Host smart-5ceaf757-02c5-4928-a864-040cf257f6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039402721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3039402721
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3740576780
Short name T312
Test name
Test status
Simulation time 501305942391 ps
CPU time 1101.77 seconds
Started Jul 27 06:35:58 PM PDT 24
Finished Jul 27 06:54:20 PM PDT 24
Peak memory 201204 kb
Host smart-c4a460d1-448e-467a-af1d-cda55bc2155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740576780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3740576780
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1602683255
Short name T624
Test name
Test status
Simulation time 164085540288 ps
CPU time 103.29 seconds
Started Jul 27 06:36:01 PM PDT 24
Finished Jul 27 06:37:44 PM PDT 24
Peak memory 201296 kb
Host smart-a721ceeb-e2c6-4d67-bafa-e23ed36055d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602683255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1602683255
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1171807343
Short name T548
Test name
Test status
Simulation time 493436882444 ps
CPU time 1136.65 seconds
Started Jul 27 06:36:03 PM PDT 24
Finished Jul 27 06:55:00 PM PDT 24
Peak memory 201276 kb
Host smart-f09b7228-aade-43d1-b0ee-87cfd591e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171807343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1171807343
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3624523925
Short name T470
Test name
Test status
Simulation time 496262118424 ps
CPU time 595.61 seconds
Started Jul 27 06:36:05 PM PDT 24
Finished Jul 27 06:46:01 PM PDT 24
Peak memory 201172 kb
Host smart-717ec88c-e0f3-4173-b7d2-5c18faf480c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624523925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3624523925
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.939290380
Short name T232
Test name
Test status
Simulation time 168056667617 ps
CPU time 394.22 seconds
Started Jul 27 06:36:02 PM PDT 24
Finished Jul 27 06:42:36 PM PDT 24
Peak memory 201244 kb
Host smart-2a3c81ca-d048-4765-b4b2-3e60440259af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939290380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.939290380
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.443972705
Short name T776
Test name
Test status
Simulation time 412329575452 ps
CPU time 432.43 seconds
Started Jul 27 06:35:59 PM PDT 24
Finished Jul 27 06:43:12 PM PDT 24
Peak memory 201136 kb
Host smart-e91e74a0-9c9e-4324-a67c-b9a326db267b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443972705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.443972705
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4017215781
Short name T633
Test name
Test status
Simulation time 66765398275 ps
CPU time 398.42 seconds
Started Jul 27 06:36:08 PM PDT 24
Finished Jul 27 06:42:46 PM PDT 24
Peak memory 201744 kb
Host smart-5641fbe3-93a2-4491-9f1b-74fb979c7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017215781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4017215781
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.835078035
Short name T496
Test name
Test status
Simulation time 28993336040 ps
CPU time 70.12 seconds
Started Jul 27 06:36:07 PM PDT 24
Finished Jul 27 06:37:17 PM PDT 24
Peak memory 200968 kb
Host smart-1e3185df-2450-4b29-9acd-7f6fc9a4774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835078035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.835078035
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1462170791
Short name T442
Test name
Test status
Simulation time 4748018891 ps
CPU time 11.62 seconds
Started Jul 27 06:36:11 PM PDT 24
Finished Jul 27 06:36:22 PM PDT 24
Peak memory 201000 kb
Host smart-df7a14be-5ee0-4024-83a8-707c04b7f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462170791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1462170791
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2226024666
Short name T5
Test name
Test status
Simulation time 5994282975 ps
CPU time 4.33 seconds
Started Jul 27 06:36:04 PM PDT 24
Finished Jul 27 06:36:09 PM PDT 24
Peak memory 201060 kb
Host smart-323ba6a6-ebca-476a-b302-7cf91146d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226024666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2226024666
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2833477006
Short name T260
Test name
Test status
Simulation time 61233063793 ps
CPU time 110.66 seconds
Started Jul 27 06:36:06 PM PDT 24
Finished Jul 27 06:37:57 PM PDT 24
Peak memory 210032 kb
Host smart-10f92153-cb0f-49ee-99f4-d9ef56f3b043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833477006 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2833477006
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1872217735
Short name T537
Test name
Test status
Simulation time 392682265 ps
CPU time 1.17 seconds
Started Jul 27 06:36:18 PM PDT 24
Finished Jul 27 06:36:19 PM PDT 24
Peak memory 201020 kb
Host smart-240c9f40-4b53-4e37-b6a3-e5b7c9c4efb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872217735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1872217735
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1623556509
Short name T589
Test name
Test status
Simulation time 182896137388 ps
CPU time 401.38 seconds
Started Jul 27 06:36:09 PM PDT 24
Finished Jul 27 06:42:51 PM PDT 24
Peak memory 201236 kb
Host smart-3eca5e1b-a1f2-44ce-9491-1bcae64b9df2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623556509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1623556509
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1948463106
Short name T200
Test name
Test status
Simulation time 483489903489 ps
CPU time 286.35 seconds
Started Jul 27 06:36:08 PM PDT 24
Finished Jul 27 06:40:55 PM PDT 24
Peak memory 201220 kb
Host smart-b7481d16-3dc5-4646-8dc5-ba4436add762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948463106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1948463106
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2279021437
Short name T384
Test name
Test status
Simulation time 485305243950 ps
CPU time 1111.16 seconds
Started Jul 27 06:36:09 PM PDT 24
Finished Jul 27 06:54:40 PM PDT 24
Peak memory 201172 kb
Host smart-d55cff63-0735-4830-89b5-c3d264f3a7ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279021437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2279021437
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1006617370
Short name T383
Test name
Test status
Simulation time 497114139350 ps
CPU time 318.71 seconds
Started Jul 27 06:36:10 PM PDT 24
Finished Jul 27 06:41:29 PM PDT 24
Peak memory 201172 kb
Host smart-cd0c1ad9-b36a-4f97-a488-5456fd38da1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006617370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1006617370
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3354653151
Short name T275
Test name
Test status
Simulation time 547581007955 ps
CPU time 305.82 seconds
Started Jul 27 06:36:08 PM PDT 24
Finished Jul 27 06:41:14 PM PDT 24
Peak memory 201240 kb
Host smart-49b967c7-ee6e-4b52-b031-70d67e556d5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354653151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3354653151
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3447710434
Short name T586
Test name
Test status
Simulation time 405280295877 ps
CPU time 237.43 seconds
Started Jul 27 06:36:10 PM PDT 24
Finished Jul 27 06:40:07 PM PDT 24
Peak memory 201252 kb
Host smart-473f4a71-74a6-4b97-bd73-4dd37512cc3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447710434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3447710434
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1075116168
Short name T396
Test name
Test status
Simulation time 76195665430 ps
CPU time 251.98 seconds
Started Jul 27 06:36:10 PM PDT 24
Finished Jul 27 06:40:22 PM PDT 24
Peak memory 201664 kb
Host smart-eaa7554a-5131-4658-8184-843956fa4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075116168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1075116168
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.166911169
Short name T534
Test name
Test status
Simulation time 34405924023 ps
CPU time 37.78 seconds
Started Jul 27 06:36:08 PM PDT 24
Finished Jul 27 06:36:45 PM PDT 24
Peak memory 201088 kb
Host smart-7ae7c677-fbfa-43f8-bf0a-094e55ace96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166911169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.166911169
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3792832819
Short name T156
Test name
Test status
Simulation time 4056264277 ps
CPU time 1.42 seconds
Started Jul 27 06:36:07 PM PDT 24
Finished Jul 27 06:36:08 PM PDT 24
Peak memory 201088 kb
Host smart-0147b408-4f78-4ff7-aa44-18091a8c6978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792832819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3792832819
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3093641677
Short name T678
Test name
Test status
Simulation time 5732915460 ps
CPU time 7.15 seconds
Started Jul 27 06:36:09 PM PDT 24
Finished Jul 27 06:36:16 PM PDT 24
Peak memory 201012 kb
Host smart-5d0d52c5-eac6-4d63-9012-4ab6097948eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093641677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3093641677
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3253651861
Short name T272
Test name
Test status
Simulation time 160564913090 ps
CPU time 182.55 seconds
Started Jul 27 06:36:11 PM PDT 24
Finished Jul 27 06:39:14 PM PDT 24
Peak memory 201188 kb
Host smart-3159c5ef-252e-4532-8e04-a64aa6a333fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253651861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3253651861
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1676685572
Short name T777
Test name
Test status
Simulation time 142172252354 ps
CPU time 146.23 seconds
Started Jul 27 06:36:07 PM PDT 24
Finished Jul 27 06:38:34 PM PDT 24
Peak memory 217324 kb
Host smart-aff0eacf-fc47-4ccd-ae6d-fcfeefe7e05f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676685572 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1676685572
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2154325212
Short name T15
Test name
Test status
Simulation time 458299376 ps
CPU time 1.63 seconds
Started Jul 27 06:36:18 PM PDT 24
Finished Jul 27 06:36:19 PM PDT 24
Peak memory 201020 kb
Host smart-a957d01c-1610-4f67-9e6d-8a6da574877a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154325212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2154325212
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2312632636
Short name T569
Test name
Test status
Simulation time 197305566222 ps
CPU time 114 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:38:10 PM PDT 24
Peak memory 201292 kb
Host smart-2eb25b24-b4ca-4f43-b19f-b917ebe88e7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312632636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2312632636
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4179357256
Short name T494
Test name
Test status
Simulation time 162972900915 ps
CPU time 184.11 seconds
Started Jul 27 06:36:15 PM PDT 24
Finished Jul 27 06:39:19 PM PDT 24
Peak memory 201220 kb
Host smart-ed1f2ff2-5768-4abf-9b11-b02cf3146568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179357256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4179357256
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2122351695
Short name T670
Test name
Test status
Simulation time 324831722080 ps
CPU time 401.35 seconds
Started Jul 27 06:36:17 PM PDT 24
Finished Jul 27 06:42:59 PM PDT 24
Peak memory 201164 kb
Host smart-e71ff677-4202-4bbf-a26b-ed6f2f247421
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122351695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2122351695
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.978842045
Short name T513
Test name
Test status
Simulation time 169333695479 ps
CPU time 105.01 seconds
Started Jul 27 06:36:17 PM PDT 24
Finished Jul 27 06:38:02 PM PDT 24
Peak memory 201276 kb
Host smart-0b31c346-6a17-4fe4-9f5e-38e1870a2f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978842045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.978842045
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.548219759
Short name T419
Test name
Test status
Simulation time 335040133456 ps
CPU time 188.72 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:39:25 PM PDT 24
Peak memory 201308 kb
Host smart-290b427f-b658-4e6a-9f87-9bf3dacb8785
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=548219759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.548219759
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3142338961
Short name T159
Test name
Test status
Simulation time 399178305616 ps
CPU time 478.63 seconds
Started Jul 27 06:36:18 PM PDT 24
Finished Jul 27 06:44:17 PM PDT 24
Peak memory 201220 kb
Host smart-9f51dd6e-f3ad-42bc-833b-2c991475e536
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142338961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3142338961
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2744179193
Short name T668
Test name
Test status
Simulation time 116837556374 ps
CPU time 433.75 seconds
Started Jul 27 06:36:17 PM PDT 24
Finished Jul 27 06:43:31 PM PDT 24
Peak memory 201704 kb
Host smart-e22c29dc-bdeb-4c3e-991f-4c0bdf7b6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744179193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2744179193
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2017447002
Short name T780
Test name
Test status
Simulation time 34895798356 ps
CPU time 39.77 seconds
Started Jul 27 06:36:15 PM PDT 24
Finished Jul 27 06:36:55 PM PDT 24
Peak memory 201060 kb
Host smart-48d8dff0-9d23-436d-a7b7-59539d35bf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017447002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2017447002
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.617605035
Short name T721
Test name
Test status
Simulation time 5341954151 ps
CPU time 13.46 seconds
Started Jul 27 06:36:16 PM PDT 24
Finished Jul 27 06:36:29 PM PDT 24
Peak memory 200996 kb
Host smart-5b587ffc-0d2b-462d-93aa-1404f6403250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617605035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.617605035
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.718853257
Short name T545
Test name
Test status
Simulation time 6013366863 ps
CPU time 3.15 seconds
Started Jul 27 06:36:15 PM PDT 24
Finished Jul 27 06:36:18 PM PDT 24
Peak memory 201060 kb
Host smart-ed845978-246f-41f3-9832-1d79b54ecab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718853257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.718853257
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2672538978
Short name T308
Test name
Test status
Simulation time 258252757507 ps
CPU time 186.91 seconds
Started Jul 27 06:36:14 PM PDT 24
Finished Jul 27 06:39:21 PM PDT 24
Peak memory 210196 kb
Host smart-51f1839d-7827-4d64-8db4-d5ee3f2df1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672538978 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2672538978
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.920500834
Short name T664
Test name
Test status
Simulation time 548725785 ps
CPU time 0.89 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:36:27 PM PDT 24
Peak memory 201008 kb
Host smart-2938e1d4-ed16-4466-93b6-e5747ec43612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920500834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.920500834
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.425759094
Short name T610
Test name
Test status
Simulation time 164297295787 ps
CPU time 185.23 seconds
Started Jul 27 06:36:28 PM PDT 24
Finished Jul 27 06:39:33 PM PDT 24
Peak memory 201236 kb
Host smart-c2ca85af-c661-4381-933f-7dce19a35c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425759094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.425759094
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4185429239
Short name T679
Test name
Test status
Simulation time 481310486672 ps
CPU time 239.01 seconds
Started Jul 27 06:36:27 PM PDT 24
Finished Jul 27 06:40:26 PM PDT 24
Peak memory 201256 kb
Host smart-18032e79-83d1-4127-9841-6b37fc2e58d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185429239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4185429239
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.347487144
Short name T765
Test name
Test status
Simulation time 322021673221 ps
CPU time 758 seconds
Started Jul 27 06:36:25 PM PDT 24
Finished Jul 27 06:49:03 PM PDT 24
Peak memory 201284 kb
Host smart-70507fec-5880-464b-9a1c-92bd6e54a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347487144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.347487144
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4047358131
Short name T625
Test name
Test status
Simulation time 159745411786 ps
CPU time 148.77 seconds
Started Jul 27 06:36:25 PM PDT 24
Finished Jul 27 06:38:54 PM PDT 24
Peak memory 201156 kb
Host smart-2273558f-8e19-4671-85de-0f37591e20e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047358131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4047358131
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2559657287
Short name T471
Test name
Test status
Simulation time 202040408709 ps
CPU time 480.48 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:44:27 PM PDT 24
Peak memory 201224 kb
Host smart-061131e3-08e5-4449-bd6b-a2e8c19dd309
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559657287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2559657287
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2351685350
Short name T420
Test name
Test status
Simulation time 69057981274 ps
CPU time 253.53 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:40:40 PM PDT 24
Peak memory 201684 kb
Host smart-6d15a736-8739-4d01-9d7f-85ebac53d8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351685350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2351685350
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3230494925
Short name T499
Test name
Test status
Simulation time 40561069018 ps
CPU time 5.68 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:36:32 PM PDT 24
Peak memory 201024 kb
Host smart-7272b328-5bfb-4c6b-acae-2b8375e56150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230494925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3230494925
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4032227023
Short name T468
Test name
Test status
Simulation time 4617391019 ps
CPU time 2.95 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:36:29 PM PDT 24
Peak memory 201068 kb
Host smart-2c09a9ad-250c-4818-be6d-1cd5e180d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032227023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4032227023
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3371115369
Short name T619
Test name
Test status
Simulation time 5965189188 ps
CPU time 12.15 seconds
Started Jul 27 06:36:27 PM PDT 24
Finished Jul 27 06:36:40 PM PDT 24
Peak memory 201056 kb
Host smart-7b49cab3-0bcc-4019-bf85-19f48a760e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371115369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3371115369
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.628128548
Short name T245
Test name
Test status
Simulation time 504151960718 ps
CPU time 911.13 seconds
Started Jul 27 06:36:26 PM PDT 24
Finished Jul 27 06:51:37 PM PDT 24
Peak memory 201184 kb
Host smart-b10415f7-7698-497e-8526-89e3b0ddfa56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628128548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
628128548
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1836539117
Short name T600
Test name
Test status
Simulation time 385567969 ps
CPU time 1.04 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:36:39 PM PDT 24
Peak memory 200980 kb
Host smart-6b846044-2487-4605-875f-a61ade70428c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836539117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1836539117
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.354493160
Short name T222
Test name
Test status
Simulation time 521307292545 ps
CPU time 1220.92 seconds
Started Jul 27 06:36:39 PM PDT 24
Finished Jul 27 06:57:00 PM PDT 24
Peak memory 201224 kb
Host smart-f9e0a104-d55c-4566-a63a-49d28a97a242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354493160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.354493160
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3958211087
Short name T598
Test name
Test status
Simulation time 325629390851 ps
CPU time 682.56 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:48:00 PM PDT 24
Peak memory 201296 kb
Host smart-405af8e2-ff16-425d-a18b-e0015dcbf587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958211087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3958211087
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1877197045
Short name T257
Test name
Test status
Simulation time 166321666521 ps
CPU time 109.77 seconds
Started Jul 27 06:36:37 PM PDT 24
Finished Jul 27 06:38:27 PM PDT 24
Peak memory 201200 kb
Host smart-2dc2dfaa-8139-4d11-a2f3-8a3c0f4dbaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877197045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1877197045
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2937189961
Short name T520
Test name
Test status
Simulation time 164386902550 ps
CPU time 390.89 seconds
Started Jul 27 06:36:39 PM PDT 24
Finished Jul 27 06:43:10 PM PDT 24
Peak memory 201460 kb
Host smart-b574ef08-728c-474b-a1da-776d79cf90a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937189961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2937189961
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2935748330
Short name T110
Test name
Test status
Simulation time 167901207622 ps
CPU time 59.89 seconds
Started Jul 27 06:36:25 PM PDT 24
Finished Jul 27 06:37:25 PM PDT 24
Peak memory 201180 kb
Host smart-dc419d43-fe0b-48d1-8d7d-13136b1b2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935748330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2935748330
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2224469200
Short name T482
Test name
Test status
Simulation time 496736669171 ps
CPU time 281.92 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:41:20 PM PDT 24
Peak memory 201156 kb
Host smart-d37d57fd-a717-47e6-9c7b-2aa54ee615df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224469200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2224469200
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.729648310
Short name T210
Test name
Test status
Simulation time 189200967364 ps
CPU time 417.41 seconds
Started Jul 27 06:36:40 PM PDT 24
Finished Jul 27 06:43:38 PM PDT 24
Peak memory 201412 kb
Host smart-f3f6cd60-dd31-4d88-8ce6-ce68e8ee7f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729648310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.729648310
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.944842496
Short name T795
Test name
Test status
Simulation time 207086575447 ps
CPU time 50.7 seconds
Started Jul 27 06:36:39 PM PDT 24
Finished Jul 27 06:37:30 PM PDT 24
Peak memory 201228 kb
Host smart-1b22fe7c-d396-4ffd-97dd-3c7ebf7eddfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944842496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.944842496
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1916340255
Short name T525
Test name
Test status
Simulation time 73713812589 ps
CPU time 372.46 seconds
Started Jul 27 06:36:43 PM PDT 24
Finished Jul 27 06:42:56 PM PDT 24
Peak memory 201696 kb
Host smart-e1e63755-c710-48f0-8c68-674e8a6ae48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916340255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1916340255
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4041324716
Short name T357
Test name
Test status
Simulation time 22096333623 ps
CPU time 53.44 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:37:32 PM PDT 24
Peak memory 201056 kb
Host smart-7e29ab5b-a9a3-4187-94a0-394573fc0ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041324716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4041324716
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.62948719
Short name T666
Test name
Test status
Simulation time 5386219798 ps
CPU time 14.28 seconds
Started Jul 27 06:36:37 PM PDT 24
Finished Jul 27 06:36:52 PM PDT 24
Peak memory 201012 kb
Host smart-8f1da4b5-cefe-4c77-ae88-c5f8b7de3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62948719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.62948719
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2527277572
Short name T405
Test name
Test status
Simulation time 5631335307 ps
CPU time 7.8 seconds
Started Jul 27 06:36:25 PM PDT 24
Finished Jul 27 06:36:33 PM PDT 24
Peak memory 201100 kb
Host smart-0d01c5cf-3c66-40c9-817a-04970bbdd595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527277572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2527277572
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2357181694
Short name T787
Test name
Test status
Simulation time 323118709741 ps
CPU time 88.54 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:38:06 PM PDT 24
Peak memory 201228 kb
Host smart-852524a0-ac39-43c4-b3b5-ea492432cbeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357181694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2357181694
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.379617807
Short name T355
Test name
Test status
Simulation time 97457265555 ps
CPU time 195.77 seconds
Started Jul 27 06:36:43 PM PDT 24
Finished Jul 27 06:39:59 PM PDT 24
Peak memory 210084 kb
Host smart-af5736ce-6ac5-458b-82e5-86482aae5c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379617807 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.379617807
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.949916638
Short name T642
Test name
Test status
Simulation time 526677153 ps
CPU time 1.77 seconds
Started Jul 27 06:36:47 PM PDT 24
Finished Jul 27 06:36:49 PM PDT 24
Peak memory 201020 kb
Host smart-52f2019c-79ab-4fb2-a524-2751dd0ba993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949916638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.949916638
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3369485593
Short name T778
Test name
Test status
Simulation time 558928693227 ps
CPU time 685.54 seconds
Started Jul 27 06:36:51 PM PDT 24
Finished Jul 27 06:48:17 PM PDT 24
Peak memory 201228 kb
Host smart-206d201c-5694-4df3-a36a-33740a02ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369485593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3369485593
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1966599505
Short name T230
Test name
Test status
Simulation time 167421848561 ps
CPU time 381.95 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:43:10 PM PDT 24
Peak memory 201192 kb
Host smart-d55cf6f7-ea84-4850-83d5-ef3dd172fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966599505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1966599505
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1896853916
Short name T480
Test name
Test status
Simulation time 499012382076 ps
CPU time 691.23 seconds
Started Jul 27 06:36:47 PM PDT 24
Finished Jul 27 06:48:19 PM PDT 24
Peak memory 201140 kb
Host smart-848d6c3e-d61f-4ff5-ad4e-2adcb4463c04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896853916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1896853916
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4188135251
Short name T578
Test name
Test status
Simulation time 330208806384 ps
CPU time 755.27 seconds
Started Jul 27 06:36:38 PM PDT 24
Finished Jul 27 06:49:14 PM PDT 24
Peak memory 201216 kb
Host smart-39c7c5ec-5d53-465f-82b1-f9e45b98f76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188135251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4188135251
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3896350691
Short name T457
Test name
Test status
Simulation time 165472223488 ps
CPU time 197.64 seconds
Started Jul 27 06:36:40 PM PDT 24
Finished Jul 27 06:39:57 PM PDT 24
Peak memory 201176 kb
Host smart-580bd9fd-e9d8-445f-af4e-7480ce6cc3b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896350691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3896350691
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.41737460
Short name T271
Test name
Test status
Simulation time 379368228964 ps
CPU time 810.48 seconds
Started Jul 27 06:36:51 PM PDT 24
Finished Jul 27 06:50:21 PM PDT 24
Peak memory 201160 kb
Host smart-737536ca-9c0a-42f2-931e-894d25b70130
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41737460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_w
akeup.41737460
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1200070266
Short name T541
Test name
Test status
Simulation time 594616166122 ps
CPU time 368.66 seconds
Started Jul 27 06:36:49 PM PDT 24
Finished Jul 27 06:42:57 PM PDT 24
Peak memory 201164 kb
Host smart-dcad4bc2-8957-441d-b193-0ece9c9f3a92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200070266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1200070266
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2929106111
Short name T173
Test name
Test status
Simulation time 113236455853 ps
CPU time 609.72 seconds
Started Jul 27 06:36:50 PM PDT 24
Finished Jul 27 06:47:00 PM PDT 24
Peak memory 201640 kb
Host smart-5db33ec6-2781-4c14-95f4-272294bff4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929106111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2929106111
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3492516988
Short name T583
Test name
Test status
Simulation time 34592986302 ps
CPU time 73.87 seconds
Started Jul 27 06:36:50 PM PDT 24
Finished Jul 27 06:38:04 PM PDT 24
Peak memory 201080 kb
Host smart-abfb63b5-7d4b-4259-9618-3aa93f895ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492516988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3492516988
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3116969949
Short name T771
Test name
Test status
Simulation time 4502343164 ps
CPU time 11.15 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:37:00 PM PDT 24
Peak memory 201032 kb
Host smart-55d98f5f-0810-4934-9a34-2e1709ad0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116969949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3116969949
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.575810145
Short name T461
Test name
Test status
Simulation time 6045039135 ps
CPU time 14.27 seconds
Started Jul 27 06:36:43 PM PDT 24
Finished Jul 27 06:36:57 PM PDT 24
Peak memory 201112 kb
Host smart-da9719e6-7042-4b0f-8fca-3e6002296448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575810145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.575810145
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.214974231
Short name T587
Test name
Test status
Simulation time 406381808258 ps
CPU time 982.69 seconds
Started Jul 27 06:36:50 PM PDT 24
Finished Jul 27 06:53:12 PM PDT 24
Peak memory 201268 kb
Host smart-d55851ac-7671-4d8b-af56-9628ba99deca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214974231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
214974231
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.532756813
Short name T42
Test name
Test status
Simulation time 3543168203 ps
CPU time 8.65 seconds
Started Jul 27 06:36:51 PM PDT 24
Finished Jul 27 06:37:00 PM PDT 24
Peak memory 201160 kb
Host smart-30a493e6-9558-4678-802f-6404b9e45b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532756813 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.532756813
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2142973862
Short name T426
Test name
Test status
Simulation time 346695984 ps
CPU time 1.38 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:35:25 PM PDT 24
Peak memory 200972 kb
Host smart-540d5923-7198-4acb-989e-373a05402240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142973862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2142973862
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4116468863
Short name T310
Test name
Test status
Simulation time 256980776131 ps
CPU time 342.96 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:41:08 PM PDT 24
Peak memory 201224 kb
Host smart-0cc0f14a-8165-4d48-b615-048ff0fa2662
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116468863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4116468863
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3222039152
Short name T259
Test name
Test status
Simulation time 331056461560 ps
CPU time 87.49 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:36:50 PM PDT 24
Peak memory 201228 kb
Host smart-2acf80cb-892c-4e88-bccd-74b49fcd293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222039152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3222039152
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.406937052
Short name T170
Test name
Test status
Simulation time 495265405752 ps
CPU time 1111.36 seconds
Started Jul 27 06:35:28 PM PDT 24
Finished Jul 27 06:53:59 PM PDT 24
Peak memory 201308 kb
Host smart-97b7c51c-8aa7-4bbb-9037-9745610361b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406937052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.406937052
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3372442202
Short name T695
Test name
Test status
Simulation time 332925886980 ps
CPU time 787.96 seconds
Started Jul 27 06:35:26 PM PDT 24
Finished Jul 27 06:48:34 PM PDT 24
Peak memory 201224 kb
Host smart-43c8afbd-0fb6-466a-b312-6bebcde9216f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372442202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3372442202
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1173649584
Short name T181
Test name
Test status
Simulation time 483263802868 ps
CPU time 73.38 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:36:38 PM PDT 24
Peak memory 201272 kb
Host smart-f266fa2b-e0bd-422a-807f-39b267430a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173649584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1173649584
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3045785282
Short name T136
Test name
Test status
Simulation time 169654496664 ps
CPU time 91.32 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:36:56 PM PDT 24
Peak memory 201176 kb
Host smart-f344d72c-bca5-4eee-8a14-72c13213fa02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045785282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3045785282
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4051405714
Short name T321
Test name
Test status
Simulation time 435838517097 ps
CPU time 289.45 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:40:15 PM PDT 24
Peak memory 201312 kb
Host smart-db7d00a5-b304-45a8-a023-aa4402847406
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051405714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4051405714
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.244822526
Short name T400
Test name
Test status
Simulation time 197460542307 ps
CPU time 233.04 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:39:17 PM PDT 24
Peak memory 201284 kb
Host smart-210cc158-7968-442d-9c8b-3eba6b171ff9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244822526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.244822526
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.296477158
Short name T352
Test name
Test status
Simulation time 87546940309 ps
CPU time 445.66 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:42:51 PM PDT 24
Peak memory 201648 kb
Host smart-b8f8ad5d-fae5-46c7-ba8e-d82d6db09976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296477158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.296477158
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.112522837
Short name T791
Test name
Test status
Simulation time 28509030319 ps
CPU time 31.52 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:35:56 PM PDT 24
Peak memory 201000 kb
Host smart-ca9ac17c-2260-48ac-aa52-750c70bd0280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112522837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.112522837
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2705791236
Short name T604
Test name
Test status
Simulation time 5319085593 ps
CPU time 14.04 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:35:37 PM PDT 24
Peak memory 200976 kb
Host smart-c09c5371-631d-40e9-9e68-c80f2edac370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705791236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2705791236
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1835412575
Short name T80
Test name
Test status
Simulation time 3820060164 ps
CPU time 8.71 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:35:32 PM PDT 24
Peak memory 216840 kb
Host smart-b5d7b61f-6546-4f23-884e-72abe087a1f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835412575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1835412575
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1560470480
Short name T402
Test name
Test status
Simulation time 5578882654 ps
CPU time 4.38 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:35:29 PM PDT 24
Peak memory 201092 kb
Host smart-8f6f9cf6-3a80-441f-8f3f-93318855200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560470480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1560470480
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3204934743
Short name T41
Test name
Test status
Simulation time 161889377095 ps
CPU time 201.03 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:38:44 PM PDT 24
Peak memory 209960 kb
Host smart-b8771e6b-419f-42c2-a793-e00ee80d3799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204934743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3204934743
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.757984590
Short name T172
Test name
Test status
Simulation time 344964760 ps
CPU time 0.82 seconds
Started Jul 27 06:37:07 PM PDT 24
Finished Jul 27 06:37:08 PM PDT 24
Peak memory 200972 kb
Host smart-cbe21136-7ed1-4e60-ace9-3304a4d7d2f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757984590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.757984590
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3656935136
Short name T243
Test name
Test status
Simulation time 161912631179 ps
CPU time 192.16 seconds
Started Jul 27 06:36:52 PM PDT 24
Finished Jul 27 06:40:04 PM PDT 24
Peak memory 201240 kb
Host smart-91f9698a-8e61-4299-b83a-66b7b8e41482
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656935136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3656935136
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1968191150
Short name T252
Test name
Test status
Simulation time 499408809617 ps
CPU time 570.1 seconds
Started Jul 27 06:36:59 PM PDT 24
Finished Jul 27 06:46:29 PM PDT 24
Peak memory 201220 kb
Host smart-7344cc27-7ace-4f6b-be69-d628b45f14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968191150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1968191150
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3343580450
Short name T495
Test name
Test status
Simulation time 337215126947 ps
CPU time 399.64 seconds
Started Jul 27 06:36:47 PM PDT 24
Finished Jul 27 06:43:27 PM PDT 24
Peak memory 201212 kb
Host smart-0493d3dc-c2de-4e2e-892d-45fc09573d51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343580450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3343580450
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1614191529
Short name T433
Test name
Test status
Simulation time 331166710082 ps
CPU time 756.87 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:49:26 PM PDT 24
Peak memory 201192 kb
Host smart-c416ed30-0c5e-451e-9cf8-5f54702dedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614191529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1614191529
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1769278915
Short name T366
Test name
Test status
Simulation time 159462526654 ps
CPU time 87.15 seconds
Started Jul 27 06:36:52 PM PDT 24
Finished Jul 27 06:38:19 PM PDT 24
Peak memory 201168 kb
Host smart-fe589857-a02a-4b5a-9c3e-7ad5b895c62a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769278915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1769278915
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1589999697
Short name T538
Test name
Test status
Simulation time 539632126005 ps
CPU time 1299.07 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:58:27 PM PDT 24
Peak memory 201224 kb
Host smart-3ec5fbc4-1556-4fc5-ab42-bb494556101e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589999697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1589999697
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.403582191
Short name T530
Test name
Test status
Simulation time 408876531914 ps
CPU time 516.39 seconds
Started Jul 27 06:36:52 PM PDT 24
Finished Jul 27 06:45:28 PM PDT 24
Peak memory 201228 kb
Host smart-9c80de8c-ab60-4be1-b67b-1bf03bf70503
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403582191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.403582191
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2063904649
Short name T514
Test name
Test status
Simulation time 75532516542 ps
CPU time 282.23 seconds
Started Jul 27 06:37:06 PM PDT 24
Finished Jul 27 06:41:48 PM PDT 24
Peak memory 201696 kb
Host smart-f47473f8-8932-4603-b3c6-5c20f38774be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063904649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2063904649
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1444112717
Short name T453
Test name
Test status
Simulation time 42037399394 ps
CPU time 20.19 seconds
Started Jul 27 06:36:59 PM PDT 24
Finished Jul 27 06:37:19 PM PDT 24
Peak memory 201032 kb
Host smart-d9f7d44b-e75e-437b-b85e-2135ed8a77b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444112717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1444112717
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1579032302
Short name T395
Test name
Test status
Simulation time 4335739466 ps
CPU time 9.86 seconds
Started Jul 27 06:36:59 PM PDT 24
Finished Jul 27 06:37:09 PM PDT 24
Peak memory 201036 kb
Host smart-b0cc9354-f7d8-4ba7-8c44-127d41db7e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579032302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1579032302
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3557674386
Short name T648
Test name
Test status
Simulation time 5924268065 ps
CPU time 14.59 seconds
Started Jul 27 06:36:48 PM PDT 24
Finished Jul 27 06:37:03 PM PDT 24
Peak memory 201064 kb
Host smart-d2a15598-3435-4619-b5c4-b469747b0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557674386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3557674386
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1028080280
Short name T164
Test name
Test status
Simulation time 379147906238 ps
CPU time 186.69 seconds
Started Jul 27 06:36:58 PM PDT 24
Finished Jul 27 06:40:05 PM PDT 24
Peak memory 201168 kb
Host smart-9f03de15-eaeb-498e-8efd-28d500f044c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028080280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1028080280
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.588984153
Short name T258
Test name
Test status
Simulation time 103640885339 ps
CPU time 97.27 seconds
Started Jul 27 06:37:06 PM PDT 24
Finished Jul 27 06:38:43 PM PDT 24
Peak memory 209972 kb
Host smart-108650d4-a2a0-4e8a-bea8-573f86da6d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588984153 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.588984153
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4050359564
Short name T669
Test name
Test status
Simulation time 362940919 ps
CPU time 1.05 seconds
Started Jul 27 06:37:10 PM PDT 24
Finished Jul 27 06:37:11 PM PDT 24
Peak memory 201016 kb
Host smart-ebcbe4e4-edec-4756-824f-b74253f05984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050359564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4050359564
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2983917218
Short name T620
Test name
Test status
Simulation time 350114354194 ps
CPU time 838.73 seconds
Started Jul 27 06:37:10 PM PDT 24
Finished Jul 27 06:51:09 PM PDT 24
Peak memory 201236 kb
Host smart-3c6aaf54-2b0c-4849-b405-b549ccb9bf62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983917218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2983917218
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2675941183
Short name T700
Test name
Test status
Simulation time 170226367924 ps
CPU time 371.52 seconds
Started Jul 27 06:37:06 PM PDT 24
Finished Jul 27 06:43:18 PM PDT 24
Peak memory 201204 kb
Host smart-db324173-4a9a-4db1-8d6f-a5e9c9e0ce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675941183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2675941183
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.675722093
Short name T261
Test name
Test status
Simulation time 488730023333 ps
CPU time 289.3 seconds
Started Jul 27 06:36:59 PM PDT 24
Finished Jul 27 06:41:49 PM PDT 24
Peak memory 201280 kb
Host smart-e18193e9-f051-4610-af0e-a24ef95baf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675722093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.675722093
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1911426566
Short name T607
Test name
Test status
Simulation time 165851039424 ps
CPU time 41.48 seconds
Started Jul 27 06:36:56 PM PDT 24
Finished Jul 27 06:37:37 PM PDT 24
Peak memory 201204 kb
Host smart-723aad75-f5b0-4906-b230-abba13c7b8a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911426566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1911426566
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2788029333
Short name T109
Test name
Test status
Simulation time 160924643384 ps
CPU time 335.45 seconds
Started Jul 27 06:36:57 PM PDT 24
Finished Jul 27 06:42:33 PM PDT 24
Peak memory 201216 kb
Host smart-426859c8-1eeb-47e3-b900-0a3b3d1fea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788029333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2788029333
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1997702499
Short name T592
Test name
Test status
Simulation time 327871251499 ps
CPU time 743.5 seconds
Started Jul 27 06:37:00 PM PDT 24
Finished Jul 27 06:49:24 PM PDT 24
Peak memory 201180 kb
Host smart-6935bf83-e409-4a04-926a-b7c08ce5403c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997702499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1997702499
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.655772821
Short name T498
Test name
Test status
Simulation time 366585034549 ps
CPU time 876.08 seconds
Started Jul 27 06:37:00 PM PDT 24
Finished Jul 27 06:51:36 PM PDT 24
Peak memory 201220 kb
Host smart-0519c225-2a0c-40aa-a66e-8c0407a30481
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655772821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.655772821
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.5770073
Short name T693
Test name
Test status
Simulation time 202655108129 ps
CPU time 114.48 seconds
Started Jul 27 06:37:06 PM PDT 24
Finished Jul 27 06:39:00 PM PDT 24
Peak memory 201128 kb
Host smart-fe5819f9-ca98-40e2-85dc-8858c55b2f1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5770073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.ad
c_ctrl_filters_wakeup_fixed.5770073
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.840960590
Short name T570
Test name
Test status
Simulation time 43641604613 ps
CPU time 107.41 seconds
Started Jul 27 06:37:07 PM PDT 24
Finished Jul 27 06:38:54 PM PDT 24
Peak memory 201088 kb
Host smart-ab661b6d-f839-4263-83d7-c3b7cd7097d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840960590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.840960590
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2940035131
Short name T469
Test name
Test status
Simulation time 2786820317 ps
CPU time 2.77 seconds
Started Jul 27 06:37:07 PM PDT 24
Finished Jul 27 06:37:10 PM PDT 24
Peak memory 201028 kb
Host smart-65871f50-2383-40bb-9064-48cbfd7326bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940035131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2940035131
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3845565819
Short name T756
Test name
Test status
Simulation time 5756245100 ps
CPU time 4.22 seconds
Started Jul 27 06:37:00 PM PDT 24
Finished Jul 27 06:37:04 PM PDT 24
Peak memory 201096 kb
Host smart-0e446153-1985-49cd-9565-9ce3e20a9607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845565819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3845565819
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3829560518
Short name T83
Test name
Test status
Simulation time 385284982 ps
CPU time 1.41 seconds
Started Jul 27 06:37:19 PM PDT 24
Finished Jul 27 06:37:20 PM PDT 24
Peak memory 201004 kb
Host smart-a9bf9180-0369-444d-84d8-9523dfa4c37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829560518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3829560518
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.585591547
Short name T733
Test name
Test status
Simulation time 488924966665 ps
CPU time 273.99 seconds
Started Jul 27 06:37:15 PM PDT 24
Finished Jul 27 06:41:49 PM PDT 24
Peak memory 201248 kb
Host smart-d1073ed2-ad8d-459b-992d-9d7f908c78c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585591547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.585591547
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1424299536
Short name T227
Test name
Test status
Simulation time 333392357287 ps
CPU time 203.25 seconds
Started Jul 27 06:37:15 PM PDT 24
Finished Jul 27 06:40:39 PM PDT 24
Peak memory 201300 kb
Host smart-7db0f113-1c3c-4475-81d8-600e606e9232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424299536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1424299536
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1841602551
Short name T745
Test name
Test status
Simulation time 162148825941 ps
CPU time 97.84 seconds
Started Jul 27 06:37:14 PM PDT 24
Finished Jul 27 06:38:52 PM PDT 24
Peak memory 201260 kb
Host smart-11d85ccb-2fa3-4ee3-ad19-964de8ea39cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841602551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1841602551
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.692799768
Short name T623
Test name
Test status
Simulation time 319504092106 ps
CPU time 666.71 seconds
Started Jul 27 06:37:17 PM PDT 24
Finished Jul 27 06:48:23 PM PDT 24
Peak memory 201208 kb
Host smart-a1b31e59-942d-48d3-9b97-ac6c31f505af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692799768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.692799768
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2003703536
Short name T553
Test name
Test status
Simulation time 164761641852 ps
CPU time 206.67 seconds
Started Jul 27 06:37:15 PM PDT 24
Finished Jul 27 06:40:42 PM PDT 24
Peak memory 201204 kb
Host smart-a74a42ec-2cd8-4bd3-83f1-0c1450c44628
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003703536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2003703536
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2573323545
Short name T774
Test name
Test status
Simulation time 537842299105 ps
CPU time 1142.5 seconds
Started Jul 27 06:37:16 PM PDT 24
Finished Jul 27 06:56:18 PM PDT 24
Peak memory 201284 kb
Host smart-308d4344-66de-4698-9e28-a223906f4db5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573323545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2573323545
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1070861308
Short name T590
Test name
Test status
Simulation time 193224674344 ps
CPU time 436.39 seconds
Started Jul 27 06:37:18 PM PDT 24
Finished Jul 27 06:44:35 PM PDT 24
Peak memory 201216 kb
Host smart-faf9b15a-62ef-4919-874f-f63ec3606a65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070861308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1070861308
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.304233488
Short name T690
Test name
Test status
Simulation time 115124511823 ps
CPU time 577.93 seconds
Started Jul 27 06:37:18 PM PDT 24
Finished Jul 27 06:46:56 PM PDT 24
Peak memory 201684 kb
Host smart-e3d7e4c2-8b7b-4f8d-804b-20cdd33b7f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304233488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.304233488
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2170158369
Short name T367
Test name
Test status
Simulation time 46263217734 ps
CPU time 28.06 seconds
Started Jul 27 06:37:17 PM PDT 24
Finished Jul 27 06:37:45 PM PDT 24
Peak memory 201052 kb
Host smart-6e97ee6d-1945-466e-8773-8794f61e6c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170158369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2170158369
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2035765954
Short name T369
Test name
Test status
Simulation time 5366671879 ps
CPU time 7.08 seconds
Started Jul 27 06:37:18 PM PDT 24
Finished Jul 27 06:37:25 PM PDT 24
Peak memory 201044 kb
Host smart-69fa475b-28d1-4d52-a142-0576827fb7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035765954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2035765954
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2166858916
Short name T766
Test name
Test status
Simulation time 5962134526 ps
CPU time 4.31 seconds
Started Jul 27 06:37:17 PM PDT 24
Finished Jul 27 06:37:22 PM PDT 24
Peak memory 201064 kb
Host smart-b7bf854d-058c-49ed-98fc-44079dbc4851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166858916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2166858916
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2367776335
Short name T584
Test name
Test status
Simulation time 537257705277 ps
CPU time 761.46 seconds
Started Jul 27 06:37:16 PM PDT 24
Finished Jul 27 06:49:58 PM PDT 24
Peak memory 201660 kb
Host smart-b2c8ffff-12c8-42df-acb3-14d242307f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367776335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2367776335
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1325187352
Short name T458
Test name
Test status
Simulation time 38172705311 ps
CPU time 111.75 seconds
Started Jul 27 06:37:15 PM PDT 24
Finished Jul 27 06:39:07 PM PDT 24
Peak memory 211064 kb
Host smart-75fd2621-4290-4c39-8207-6b42c4c425e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325187352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1325187352
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2844379110
Short name T725
Test name
Test status
Simulation time 395696522 ps
CPU time 1.06 seconds
Started Jul 27 06:37:32 PM PDT 24
Finished Jul 27 06:37:33 PM PDT 24
Peak memory 200980 kb
Host smart-790f4f87-263b-46cd-9956-96a29e44f918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844379110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2844379110
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1974442180
Short name T209
Test name
Test status
Simulation time 335563712420 ps
CPU time 121.3 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:39:34 PM PDT 24
Peak memory 201296 kb
Host smart-20630591-f0c2-4ae8-bbc0-a858cbe67cdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974442180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1974442180
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1568380134
Short name T662
Test name
Test status
Simulation time 539546626682 ps
CPU time 350.8 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:43:24 PM PDT 24
Peak memory 201248 kb
Host smart-bdcd765c-12c6-4be0-8b3c-0ce73de03ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568380134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1568380134
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3071810846
Short name T231
Test name
Test status
Simulation time 497103074175 ps
CPU time 1065.87 seconds
Started Jul 27 06:37:24 PM PDT 24
Finished Jul 27 06:55:10 PM PDT 24
Peak memory 201292 kb
Host smart-4c22ddb3-39fe-4a9e-afde-c170b49336f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071810846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3071810846
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2723670581
Short name T518
Test name
Test status
Simulation time 499408949009 ps
CPU time 186.35 seconds
Started Jul 27 06:37:26 PM PDT 24
Finished Jul 27 06:40:32 PM PDT 24
Peak memory 201216 kb
Host smart-1c5c3333-0be4-4af2-9750-7afd2f626345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723670581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2723670581
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2613551068
Short name T287
Test name
Test status
Simulation time 166942042697 ps
CPU time 204.05 seconds
Started Jul 27 06:37:24 PM PDT 24
Finished Jul 27 06:40:48 PM PDT 24
Peak memory 201224 kb
Host smart-03dea1ec-2ce9-4ae3-8a41-f54b206ce168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613551068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2613551068
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1038190166
Short name T483
Test name
Test status
Simulation time 162111604005 ps
CPU time 333.46 seconds
Started Jul 27 06:37:26 PM PDT 24
Finished Jul 27 06:42:59 PM PDT 24
Peak memory 201232 kb
Host smart-93e8bb99-0b38-4ef7-bcb7-8313570441b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038190166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1038190166
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.4171057208
Short name T667
Test name
Test status
Simulation time 578530254992 ps
CPU time 757.79 seconds
Started Jul 27 06:37:27 PM PDT 24
Finished Jul 27 06:50:05 PM PDT 24
Peak memory 201240 kb
Host smart-ab98ae99-b382-497b-a3df-19c0b7fd0c83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171057208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.4171057208
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3300973995
Short name T386
Test name
Test status
Simulation time 622253939751 ps
CPU time 1344.89 seconds
Started Jul 27 06:37:35 PM PDT 24
Finished Jul 27 07:00:00 PM PDT 24
Peak memory 201228 kb
Host smart-fab83f48-c667-4f31-87dc-8f96c3a244fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300973995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3300973995
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2422495789
Short name T481
Test name
Test status
Simulation time 121218791215 ps
CPU time 516.14 seconds
Started Jul 27 06:37:32 PM PDT 24
Finished Jul 27 06:46:09 PM PDT 24
Peak memory 201692 kb
Host smart-ca29e56b-b2e1-4757-a14b-3deaeebdda7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422495789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2422495789
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3712400831
Short name T616
Test name
Test status
Simulation time 28415689485 ps
CPU time 65.36 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:38:39 PM PDT 24
Peak memory 201100 kb
Host smart-8d940095-a41b-422d-9a3e-e613131fbaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712400831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3712400831
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1235699469
Short name T359
Test name
Test status
Simulation time 4748259179 ps
CPU time 1.52 seconds
Started Jul 27 06:37:32 PM PDT 24
Finished Jul 27 06:37:34 PM PDT 24
Peak memory 201048 kb
Host smart-9bdcf319-ac27-4a71-800e-16a71188f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235699469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1235699469
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2404022155
Short name T735
Test name
Test status
Simulation time 6035630078 ps
CPU time 4.33 seconds
Started Jul 27 06:37:25 PM PDT 24
Finished Jul 27 06:37:29 PM PDT 24
Peak memory 201044 kb
Host smart-1e4100df-dc14-4c84-840a-619a96cbc2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404022155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2404022155
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2358521309
Short name T286
Test name
Test status
Simulation time 124293150853 ps
CPU time 148.18 seconds
Started Jul 27 06:37:34 PM PDT 24
Finished Jul 27 06:40:02 PM PDT 24
Peak memory 218180 kb
Host smart-6134f488-cdbd-4940-a1eb-59fa97712f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358521309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2358521309
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3377352348
Short name T475
Test name
Test status
Simulation time 352416945 ps
CPU time 0.98 seconds
Started Jul 27 06:37:43 PM PDT 24
Finished Jul 27 06:37:44 PM PDT 24
Peak memory 201020 kb
Host smart-ca499a37-94ce-44a5-963c-887274730bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377352348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3377352348
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.84484768
Short name T627
Test name
Test status
Simulation time 357285936513 ps
CPU time 831.27 seconds
Started Jul 27 06:37:44 PM PDT 24
Finished Jul 27 06:51:35 PM PDT 24
Peak memory 201420 kb
Host smart-b14489d4-694d-4f56-ad02-f6854e7c9df1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84484768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gatin
g.84484768
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3555860448
Short name T665
Test name
Test status
Simulation time 366675827111 ps
CPU time 437.11 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:44:59 PM PDT 24
Peak memory 201152 kb
Host smart-120d54ab-8612-41e4-8aec-889a12ab1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555860448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3555860448
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.782886942
Short name T189
Test name
Test status
Simulation time 166314980123 ps
CPU time 102.38 seconds
Started Jul 27 06:37:43 PM PDT 24
Finished Jul 27 06:39:25 PM PDT 24
Peak memory 201236 kb
Host smart-7a2360ad-14d1-41dd-9e1e-c5a31a293034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782886942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.782886942
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.698284543
Short name T656
Test name
Test status
Simulation time 163385781994 ps
CPU time 37.83 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:38:20 PM PDT 24
Peak memory 201204 kb
Host smart-66b5e01a-0896-4082-aaea-d2d4c541ecd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=698284543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.698284543
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1658806821
Short name T489
Test name
Test status
Simulation time 164039151217 ps
CPU time 339.32 seconds
Started Jul 27 06:37:32 PM PDT 24
Finished Jul 27 06:43:11 PM PDT 24
Peak memory 201228 kb
Host smart-1bcc5e83-adb3-4015-9b12-e0d0b8eaeb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658806821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1658806821
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2908560329
Short name T89
Test name
Test status
Simulation time 322625162663 ps
CPU time 738.18 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:49:51 PM PDT 24
Peak memory 201192 kb
Host smart-2c05db89-790f-41fb-a293-a557831a5541
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908560329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2908560329
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3170266089
Short name T524
Test name
Test status
Simulation time 352804073025 ps
CPU time 142.44 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:40:04 PM PDT 24
Peak memory 201268 kb
Host smart-40302243-6065-441e-8ac2-8e96703976d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170266089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3170266089
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1264412620
Short name T564
Test name
Test status
Simulation time 207519186549 ps
CPU time 240.44 seconds
Started Jul 27 06:37:43 PM PDT 24
Finished Jul 27 06:41:43 PM PDT 24
Peak memory 201228 kb
Host smart-2ae6070a-0c85-4540-894b-27ef22453643
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264412620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1264412620
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1682571984
Short name T338
Test name
Test status
Simulation time 120083354260 ps
CPU time 443.81 seconds
Started Jul 27 06:37:41 PM PDT 24
Finished Jul 27 06:45:05 PM PDT 24
Peak memory 201644 kb
Host smart-49d3ffd1-f56b-45a4-a57c-6de0ec1cca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682571984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1682571984
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.283148373
Short name T34
Test name
Test status
Simulation time 24715456555 ps
CPU time 15.94 seconds
Started Jul 27 06:37:40 PM PDT 24
Finished Jul 27 06:37:57 PM PDT 24
Peak memory 201040 kb
Host smart-2128c061-1d34-4fc0-af5c-7352e0707b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283148373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.283148373
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1324883491
Short name T465
Test name
Test status
Simulation time 4618327207 ps
CPU time 2.18 seconds
Started Jul 27 06:37:43 PM PDT 24
Finished Jul 27 06:37:46 PM PDT 24
Peak memory 201264 kb
Host smart-03b2d411-cef4-41cb-9c73-268d4cd588b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324883491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1324883491
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3588619642
Short name T761
Test name
Test status
Simulation time 5800802539 ps
CPU time 13.43 seconds
Started Jul 27 06:37:33 PM PDT 24
Finished Jul 27 06:37:47 PM PDT 24
Peak memory 201068 kb
Host smart-bd216227-1bdb-4bb2-aa48-6f2ef6081b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588619642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3588619642
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3512077117
Short name T742
Test name
Test status
Simulation time 336284876579 ps
CPU time 45.38 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:38:27 PM PDT 24
Peak memory 201276 kb
Host smart-494d2693-3c06-49c5-8515-76309915f990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512077117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3512077117
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1348234833
Short name T734
Test name
Test status
Simulation time 307717871 ps
CPU time 0.81 seconds
Started Jul 27 06:37:50 PM PDT 24
Finished Jul 27 06:37:51 PM PDT 24
Peak memory 200984 kb
Host smart-35897791-0a0d-44f1-8441-efed5151ed6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348234833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1348234833
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3152349826
Short name T631
Test name
Test status
Simulation time 331296325142 ps
CPU time 595.26 seconds
Started Jul 27 06:37:50 PM PDT 24
Finished Jul 27 06:47:46 PM PDT 24
Peak memory 201272 kb
Host smart-2ec0cc49-4c9f-4fcb-ab1a-138a1ba0f76a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152349826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3152349826
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3636875215
Short name T709
Test name
Test status
Simulation time 503443301213 ps
CPU time 313.92 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:43:05 PM PDT 24
Peak memory 201252 kb
Host smart-62eb62da-0051-486b-a4c8-2c631aeacd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636875215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3636875215
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.781173224
Short name T501
Test name
Test status
Simulation time 160846871569 ps
CPU time 114.39 seconds
Started Jul 27 06:37:50 PM PDT 24
Finished Jul 27 06:39:45 PM PDT 24
Peak memory 201212 kb
Host smart-81cd9c8a-a83e-43f0-9f1f-2302de340c9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=781173224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.781173224
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4016945026
Short name T11
Test name
Test status
Simulation time 500394232517 ps
CPU time 109.48 seconds
Started Jul 27 06:37:42 PM PDT 24
Finished Jul 27 06:39:31 PM PDT 24
Peak memory 201212 kb
Host smart-874118fa-92e0-4749-bb92-fdb013c42aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016945026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4016945026
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.864619313
Short name T597
Test name
Test status
Simulation time 489747210024 ps
CPU time 566.53 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:47:18 PM PDT 24
Peak memory 201168 kb
Host smart-52a12488-7a96-426e-ac0a-8c522b52adfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=864619313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.864619313
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.910955038
Short name T184
Test name
Test status
Simulation time 183408114611 ps
CPU time 102.34 seconds
Started Jul 27 06:37:50 PM PDT 24
Finished Jul 27 06:39:33 PM PDT 24
Peak memory 201212 kb
Host smart-67df377e-5dd4-49c0-a94d-f1e9201fdbdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910955038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.910955038
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1949283277
Short name T652
Test name
Test status
Simulation time 603834816837 ps
CPU time 357.62 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:43:48 PM PDT 24
Peak memory 201216 kb
Host smart-677e59b4-0ae8-4490-81b3-bfce50a7ad66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949283277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1949283277
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1575926198
Short name T560
Test name
Test status
Simulation time 29850520776 ps
CPU time 72.43 seconds
Started Jul 27 06:37:53 PM PDT 24
Finished Jul 27 06:39:06 PM PDT 24
Peak memory 201072 kb
Host smart-1e4921c2-5fb7-49cf-a625-e2120787ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575926198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1575926198
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3037122416
Short name T515
Test name
Test status
Simulation time 4567802783 ps
CPU time 3.24 seconds
Started Jul 27 06:37:53 PM PDT 24
Finished Jul 27 06:37:56 PM PDT 24
Peak memory 201044 kb
Host smart-3fb43b3e-88f8-43b6-842b-ce65ab1b49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037122416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3037122416
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2654498987
Short name T493
Test name
Test status
Simulation time 5707967732 ps
CPU time 4.26 seconds
Started Jul 27 06:37:43 PM PDT 24
Finished Jul 27 06:37:47 PM PDT 24
Peak memory 201108 kb
Host smart-b96c440a-cc67-40f3-b397-bfb480d6c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654498987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2654498987
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.783099835
Short name T632
Test name
Test status
Simulation time 24244214029 ps
CPU time 31.83 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:38:22 PM PDT 24
Peak memory 201304 kb
Host smart-03f9bc9c-7db3-4d68-9c57-bcc11989cd35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783099835 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.783099835
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.863036748
Short name T379
Test name
Test status
Simulation time 425637786 ps
CPU time 1.07 seconds
Started Jul 27 06:38:09 PM PDT 24
Finished Jul 27 06:38:10 PM PDT 24
Peak memory 200984 kb
Host smart-9a30687c-7748-4027-9e87-86eeb90e2080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863036748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.863036748
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2573129016
Short name T750
Test name
Test status
Simulation time 335721893024 ps
CPU time 781.18 seconds
Started Jul 27 06:38:01 PM PDT 24
Finished Jul 27 06:51:03 PM PDT 24
Peak memory 201232 kb
Host smart-92a73f2f-aa3a-4697-a399-0c98812ee186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573129016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2573129016
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1902708756
Short name T439
Test name
Test status
Simulation time 332004970082 ps
CPU time 404.21 seconds
Started Jul 27 06:38:00 PM PDT 24
Finished Jul 27 06:44:45 PM PDT 24
Peak memory 201128 kb
Host smart-763ab415-a6f2-4067-92ef-cbce7a6f301d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902708756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1902708756
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3459828132
Short name T100
Test name
Test status
Simulation time 488403360385 ps
CPU time 252.1 seconds
Started Jul 27 06:38:00 PM PDT 24
Finished Jul 27 06:42:12 PM PDT 24
Peak memory 201160 kb
Host smart-0f37fb82-ab5b-4e92-a049-9b369f548ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459828132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3459828132
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2347422382
Short name T143
Test name
Test status
Simulation time 326338252967 ps
CPU time 105.89 seconds
Started Jul 27 06:37:59 PM PDT 24
Finished Jul 27 06:39:45 PM PDT 24
Peak memory 201180 kb
Host smart-31bfecdc-eea3-413f-9905-45593a60c135
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347422382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2347422382
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2077346088
Short name T254
Test name
Test status
Simulation time 361060558361 ps
CPU time 780.35 seconds
Started Jul 27 06:38:01 PM PDT 24
Finished Jul 27 06:51:01 PM PDT 24
Peak memory 201224 kb
Host smart-990cb6b2-3e54-42e1-a0de-057070cae8b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077346088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2077346088
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1774757340
Short name T684
Test name
Test status
Simulation time 625900489109 ps
CPU time 1403.8 seconds
Started Jul 27 06:38:00 PM PDT 24
Finished Jul 27 07:01:25 PM PDT 24
Peak memory 201232 kb
Host smart-eac47876-d07a-4b68-8af0-898caea3eb86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774757340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1774757340
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.831562323
Short name T375
Test name
Test status
Simulation time 94988082819 ps
CPU time 452.66 seconds
Started Jul 27 06:38:10 PM PDT 24
Finished Jul 27 06:45:43 PM PDT 24
Peak memory 201700 kb
Host smart-12e1f7a4-e8d2-4254-bcd8-d842ac286c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831562323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.831562323
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2234482173
Short name T97
Test name
Test status
Simulation time 43408067551 ps
CPU time 27.83 seconds
Started Jul 27 06:38:09 PM PDT 24
Finished Jul 27 06:38:37 PM PDT 24
Peak memory 201096 kb
Host smart-668a22f1-d0c1-4150-804f-ba0340ee4038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234482173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2234482173
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1334069285
Short name T412
Test name
Test status
Simulation time 5446829707 ps
CPU time 13.82 seconds
Started Jul 27 06:37:59 PM PDT 24
Finished Jul 27 06:38:13 PM PDT 24
Peak memory 201012 kb
Host smart-11f6ac8d-6dcb-46b2-ab83-119176ff1558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334069285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1334069285
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3953050632
Short name T431
Test name
Test status
Simulation time 5682270541 ps
CPU time 14.31 seconds
Started Jul 27 06:37:51 PM PDT 24
Finished Jul 27 06:38:06 PM PDT 24
Peak memory 201056 kb
Host smart-63da4565-14fb-44eb-844c-09c1c8ed38ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953050632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3953050632
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2542788785
Short name T617
Test name
Test status
Simulation time 203590002444 ps
CPU time 450.98 seconds
Started Jul 27 06:38:12 PM PDT 24
Finished Jul 27 06:45:43 PM PDT 24
Peak memory 201204 kb
Host smart-4c44cc49-04be-43d1-9bed-28b9fbc0b461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542788785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2542788785
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2759899552
Short name T102
Test name
Test status
Simulation time 115420312056 ps
CPU time 83.47 seconds
Started Jul 27 06:38:10 PM PDT 24
Finished Jul 27 06:39:34 PM PDT 24
Peak memory 217516 kb
Host smart-a4b1cb63-62d2-4462-8ccb-13899401aee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759899552 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2759899552
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1957927960
Short name T462
Test name
Test status
Simulation time 460295348 ps
CPU time 0.78 seconds
Started Jul 27 06:38:19 PM PDT 24
Finished Jul 27 06:38:20 PM PDT 24
Peak memory 200996 kb
Host smart-d400ab4b-f5f1-437e-8b26-38954840ec06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957927960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1957927960
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2183382898
Short name T107
Test name
Test status
Simulation time 188306656965 ps
CPU time 397.76 seconds
Started Jul 27 06:38:12 PM PDT 24
Finished Jul 27 06:44:50 PM PDT 24
Peak memory 201224 kb
Host smart-1e73593b-2d8d-4ef8-9a9a-3008c75cb9da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183382898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2183382898
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2155351089
Short name T752
Test name
Test status
Simulation time 546363056452 ps
CPU time 659.19 seconds
Started Jul 27 06:38:10 PM PDT 24
Finished Jul 27 06:49:09 PM PDT 24
Peak memory 201176 kb
Host smart-00dd5c76-d888-47a1-8862-3c643aa3181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155351089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2155351089
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.534529775
Short name T240
Test name
Test status
Simulation time 167545040744 ps
CPU time 178.44 seconds
Started Jul 27 06:38:09 PM PDT 24
Finished Jul 27 06:41:08 PM PDT 24
Peak memory 201292 kb
Host smart-b91af0b8-75e4-4b4c-8354-adee4314731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534529775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.534529775
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2848841098
Short name T696
Test name
Test status
Simulation time 496791347256 ps
CPU time 564.88 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:47:36 PM PDT 24
Peak memory 201136 kb
Host smart-816ce51f-cce0-4b71-84a4-8c5042024b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848841098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2848841098
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1377178471
Short name T660
Test name
Test status
Simulation time 159976880322 ps
CPU time 363.99 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:44:15 PM PDT 24
Peak memory 201192 kb
Host smart-7d9bff16-911d-4b55-930b-410cb79b1e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377178471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1377178471
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1835599551
Short name T737
Test name
Test status
Simulation time 495649461051 ps
CPU time 1211.48 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:58:23 PM PDT 24
Peak memory 201220 kb
Host smart-5a1a2521-001e-4536-a3cd-ca92927ef93c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835599551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1835599551
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1337293491
Short name T703
Test name
Test status
Simulation time 183629848511 ps
CPU time 103.99 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:39:55 PM PDT 24
Peak memory 201224 kb
Host smart-f3bb2a3c-212d-43ab-a948-472c79a7ee21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337293491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1337293491
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1622154891
Short name T638
Test name
Test status
Simulation time 608730019961 ps
CPU time 110.86 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:40:02 PM PDT 24
Peak memory 201248 kb
Host smart-578394d0-f688-465b-94cf-df547c9f0d0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622154891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1622154891
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3383569615
Short name T340
Test name
Test status
Simulation time 98932225388 ps
CPU time 331.36 seconds
Started Jul 27 06:38:19 PM PDT 24
Finished Jul 27 06:43:51 PM PDT 24
Peak memory 201752 kb
Host smart-bdd05a8b-b966-42bf-9aa0-7870ab6466f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383569615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3383569615
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4263834878
Short name T640
Test name
Test status
Simulation time 37623720620 ps
CPU time 22.55 seconds
Started Jul 27 06:38:19 PM PDT 24
Finished Jul 27 06:38:42 PM PDT 24
Peak memory 201080 kb
Host smart-642dca0a-af25-4623-b659-d7759a1c7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263834878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4263834878
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.209806609
Short name T688
Test name
Test status
Simulation time 2855905763 ps
CPU time 6.24 seconds
Started Jul 27 06:38:09 PM PDT 24
Finished Jul 27 06:38:16 PM PDT 24
Peak memory 200976 kb
Host smart-7428f232-cb4a-4047-877c-d7900e216b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209806609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.209806609
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3861487400
Short name T622
Test name
Test status
Simulation time 6046396145 ps
CPU time 14.41 seconds
Started Jul 27 06:38:11 PM PDT 24
Finished Jul 27 06:38:26 PM PDT 24
Peak memory 201048 kb
Host smart-a537d57f-a96b-4c3a-bf85-63327e955fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861487400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3861487400
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.274355195
Short name T711
Test name
Test status
Simulation time 206802118499 ps
CPU time 522.9 seconds
Started Jul 27 06:38:17 PM PDT 24
Finished Jul 27 06:47:00 PM PDT 24
Peak memory 210096 kb
Host smart-db55bee8-d48a-4bda-b4fb-3fa853b7e759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274355195 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.274355195
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1000244593
Short name T94
Test name
Test status
Simulation time 565406405 ps
CPU time 0.91 seconds
Started Jul 27 06:38:33 PM PDT 24
Finished Jul 27 06:38:34 PM PDT 24
Peak memory 201028 kb
Host smart-1d1f2ad4-a4a9-47d2-bc21-463d224f75b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000244593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1000244593
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1608349332
Short name T299
Test name
Test status
Simulation time 510142041999 ps
CPU time 398.45 seconds
Started Jul 27 06:38:26 PM PDT 24
Finished Jul 27 06:45:05 PM PDT 24
Peak memory 201180 kb
Host smart-82b19fcd-7d71-437b-b6d9-b674b9166c50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608349332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1608349332
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.718615476
Short name T316
Test name
Test status
Simulation time 511700732251 ps
CPU time 332.77 seconds
Started Jul 27 06:38:33 PM PDT 24
Finished Jul 27 06:44:06 PM PDT 24
Peak memory 201216 kb
Host smart-5d58d100-dd15-4eea-8ef8-b568a12578a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718615476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.718615476
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1751435032
Short name T298
Test name
Test status
Simulation time 489290468395 ps
CPU time 581.03 seconds
Started Jul 27 06:38:20 PM PDT 24
Finished Jul 27 06:48:01 PM PDT 24
Peak memory 201224 kb
Host smart-97e38f13-f43c-4341-a115-19870cf27c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751435032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1751435032
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3881871997
Short name T519
Test name
Test status
Simulation time 331177060746 ps
CPU time 422.61 seconds
Started Jul 27 06:38:19 PM PDT 24
Finished Jul 27 06:45:22 PM PDT 24
Peak memory 201140 kb
Host smart-8d8d9e09-2b2f-4017-a915-63209fa48986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881871997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3881871997
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2984654121
Short name T506
Test name
Test status
Simulation time 491830022193 ps
CPU time 1161.13 seconds
Started Jul 27 06:38:21 PM PDT 24
Finished Jul 27 06:57:42 PM PDT 24
Peak memory 201232 kb
Host smart-6fe0773e-abe4-4d08-9d5a-b02d0a13025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984654121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2984654121
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3298196055
Short name T4
Test name
Test status
Simulation time 164941784858 ps
CPU time 83.26 seconds
Started Jul 27 06:38:20 PM PDT 24
Finished Jul 27 06:39:43 PM PDT 24
Peak memory 201172 kb
Host smart-d5a6c4f4-e51c-4443-84b6-133bc31f8a18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298196055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3298196055
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2639245213
Short name T179
Test name
Test status
Simulation time 515534065384 ps
CPU time 283.75 seconds
Started Jul 27 06:38:26 PM PDT 24
Finished Jul 27 06:43:10 PM PDT 24
Peak memory 201236 kb
Host smart-c43cef8c-1884-4da0-ba5b-42e8a72c57f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639245213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2639245213
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3928832595
Short name T712
Test name
Test status
Simulation time 610669599653 ps
CPU time 117.63 seconds
Started Jul 27 06:38:27 PM PDT 24
Finished Jul 27 06:40:24 PM PDT 24
Peak memory 201472 kb
Host smart-d5b508bf-aa1b-41e7-b4da-69cbed74c284
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928832595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3928832595
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2490093890
Short name T92
Test name
Test status
Simulation time 134047832835 ps
CPU time 514 seconds
Started Jul 27 06:38:27 PM PDT 24
Finished Jul 27 06:47:01 PM PDT 24
Peak memory 201680 kb
Host smart-33efcc9b-2af6-4f7d-a87e-edc5f9f00ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490093890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2490093890
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3146512248
Short name T550
Test name
Test status
Simulation time 40625063986 ps
CPU time 91.31 seconds
Started Jul 27 06:38:26 PM PDT 24
Finished Jul 27 06:39:57 PM PDT 24
Peak memory 201040 kb
Host smart-3a3becaf-9738-48e6-a276-9a071427490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146512248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3146512248
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3823498531
Short name T588
Test name
Test status
Simulation time 5272259822 ps
CPU time 12.46 seconds
Started Jul 27 06:38:28 PM PDT 24
Finished Jul 27 06:38:40 PM PDT 24
Peak memory 201020 kb
Host smart-6ef5ecec-77aa-4180-9217-7dad0a166600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823498531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3823498531
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.676559199
Short name T784
Test name
Test status
Simulation time 5935611302 ps
CPU time 4.06 seconds
Started Jul 27 06:38:18 PM PDT 24
Finished Jul 27 06:38:22 PM PDT 24
Peak memory 201088 kb
Host smart-812543f2-0629-49cd-9b78-a704d776ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676559199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.676559199
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1888420323
Short name T174
Test name
Test status
Simulation time 36905640797 ps
CPU time 22.57 seconds
Started Jul 27 06:38:27 PM PDT 24
Finished Jul 27 06:38:50 PM PDT 24
Peak memory 201088 kb
Host smart-cb478523-b29f-454e-ad72-0c2e1fc3b86f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888420323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1888420323
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.485696070
Short name T775
Test name
Test status
Simulation time 621221023535 ps
CPU time 194.06 seconds
Started Jul 27 06:38:27 PM PDT 24
Finished Jul 27 06:41:41 PM PDT 24
Peak memory 209596 kb
Host smart-b1b94d2a-1d86-4ce7-bf3c-803a3a49555a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485696070 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.485696070
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.63399860
Short name T78
Test name
Test status
Simulation time 413356694 ps
CPU time 0.78 seconds
Started Jul 27 06:38:45 PM PDT 24
Finished Jul 27 06:38:46 PM PDT 24
Peak memory 201028 kb
Host smart-4674072c-1fdc-451d-9488-f57b2289a574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63399860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.63399860
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2131577897
Short name T235
Test name
Test status
Simulation time 512586604698 ps
CPU time 1184.55 seconds
Started Jul 27 06:38:36 PM PDT 24
Finished Jul 27 06:58:20 PM PDT 24
Peak memory 201160 kb
Host smart-f286e7e2-1309-47d9-a3cb-65a4688a3e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131577897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2131577897
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1857752315
Short name T594
Test name
Test status
Simulation time 488252921111 ps
CPU time 1203.67 seconds
Started Jul 27 06:38:37 PM PDT 24
Finished Jul 27 06:58:41 PM PDT 24
Peak memory 201220 kb
Host smart-5c9b38e6-bd1b-4921-b278-b18bca700011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857752315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1857752315
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2443411052
Short name T474
Test name
Test status
Simulation time 332067553083 ps
CPU time 336.41 seconds
Started Jul 27 06:38:35 PM PDT 24
Finished Jul 27 06:44:11 PM PDT 24
Peak memory 201172 kb
Host smart-c848be4f-c692-4fa2-bc99-65bab7aa4a52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443411052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2443411052
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2219393748
Short name T263
Test name
Test status
Simulation time 328454454973 ps
CPU time 55.94 seconds
Started Jul 27 06:38:32 PM PDT 24
Finished Jul 27 06:39:28 PM PDT 24
Peak memory 201228 kb
Host smart-9ff8afe1-abd8-4cb5-bcf4-bb23c28c7abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219393748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2219393748
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.649553425
Short name T528
Test name
Test status
Simulation time 332995670082 ps
CPU time 113.16 seconds
Started Jul 27 06:38:30 PM PDT 24
Finished Jul 27 06:40:23 PM PDT 24
Peak memory 201232 kb
Host smart-2c55e656-5816-404c-8272-435e58ac2b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=649553425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.649553425
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2451049996
Short name T161
Test name
Test status
Simulation time 347393906079 ps
CPU time 782.44 seconds
Started Jul 27 06:38:35 PM PDT 24
Finished Jul 27 06:51:37 PM PDT 24
Peak memory 201144 kb
Host smart-9270f225-b264-477b-8823-4d81548095ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451049996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2451049996
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4161455064
Short name T450
Test name
Test status
Simulation time 402865535936 ps
CPU time 206.74 seconds
Started Jul 27 06:38:34 PM PDT 24
Finished Jul 27 06:42:01 PM PDT 24
Peak memory 201180 kb
Host smart-8436bfef-c540-4047-aa29-b52050e0faa7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161455064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4161455064
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.526400768
Short name T343
Test name
Test status
Simulation time 91895619014 ps
CPU time 311.63 seconds
Started Jul 27 06:38:44 PM PDT 24
Finished Jul 27 06:43:56 PM PDT 24
Peak memory 201740 kb
Host smart-07c9afb8-a632-4f06-b7ec-59c3f949841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526400768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.526400768
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1026103077
Short name T673
Test name
Test status
Simulation time 27069397574 ps
CPU time 65.29 seconds
Started Jul 27 06:38:37 PM PDT 24
Finished Jul 27 06:39:42 PM PDT 24
Peak memory 201072 kb
Host smart-0c32a76a-1280-4de1-b6ab-a02e8d7e85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026103077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1026103077
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2355227456
Short name T399
Test name
Test status
Simulation time 5593671257 ps
CPU time 14.63 seconds
Started Jul 27 06:38:35 PM PDT 24
Finished Jul 27 06:38:50 PM PDT 24
Peak memory 201032 kb
Host smart-e9323345-596e-49eb-bd8c-198402b7f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355227456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2355227456
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2723019370
Short name T611
Test name
Test status
Simulation time 5848900396 ps
CPU time 7.44 seconds
Started Jul 27 06:38:26 PM PDT 24
Finished Jul 27 06:38:33 PM PDT 24
Peak memory 201068 kb
Host smart-696fead1-2f2f-414f-b41a-abdb022609b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723019370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2723019370
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.882965805
Short name T479
Test name
Test status
Simulation time 245775372735 ps
CPU time 80.07 seconds
Started Jul 27 06:38:45 PM PDT 24
Finished Jul 27 06:40:05 PM PDT 24
Peak memory 201196 kb
Host smart-a1bb6bac-49da-4023-a4e5-3e12ddfd5fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882965805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
882965805
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1530406472
Short name T634
Test name
Test status
Simulation time 90542714509 ps
CPU time 66.42 seconds
Started Jul 27 06:38:46 PM PDT 24
Finished Jul 27 06:39:52 PM PDT 24
Peak memory 218144 kb
Host smart-08a44d64-29ac-4ef4-84f5-e435f3467f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530406472 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1530406472
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2393302071
Short name T377
Test name
Test status
Simulation time 417414726 ps
CPU time 0.66 seconds
Started Jul 27 06:35:32 PM PDT 24
Finished Jul 27 06:35:33 PM PDT 24
Peak memory 201000 kb
Host smart-73f9da0a-7b51-4ec4-8d57-73134c2ed309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393302071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2393302071
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1466780836
Short name T527
Test name
Test status
Simulation time 326868925950 ps
CPU time 688.76 seconds
Started Jul 27 06:35:26 PM PDT 24
Finished Jul 27 06:46:55 PM PDT 24
Peak memory 201180 kb
Host smart-92379001-5367-4653-90e4-1795daf66741
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466780836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1466780836
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3278800750
Short name T646
Test name
Test status
Simulation time 164697850550 ps
CPU time 350.48 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:41:16 PM PDT 24
Peak memory 201220 kb
Host smart-2e8e3026-ece5-4ed6-aa98-7c194ef08710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278800750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3278800750
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1061728235
Short name T296
Test name
Test status
Simulation time 166783561550 ps
CPU time 93.87 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:36:59 PM PDT 24
Peak memory 201480 kb
Host smart-d180cc47-29d6-4cb7-8235-0451102eb0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061728235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1061728235
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.458419527
Short name T390
Test name
Test status
Simulation time 167611226881 ps
CPU time 410.13 seconds
Started Jul 27 06:35:30 PM PDT 24
Finished Jul 27 06:42:20 PM PDT 24
Peak memory 201224 kb
Host smart-b1fc000a-393c-411f-a9fa-ff54a40102fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=458419527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.458419527
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2826920588
Short name T657
Test name
Test status
Simulation time 328247852074 ps
CPU time 742.95 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:47:46 PM PDT 24
Peak memory 201284 kb
Host smart-3d7aa3f8-9498-4cb1-8741-c72fb279d65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826920588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2826920588
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.723350959
Short name T601
Test name
Test status
Simulation time 164244471830 ps
CPU time 178.58 seconds
Started Jul 27 06:35:24 PM PDT 24
Finished Jul 27 06:38:22 PM PDT 24
Peak memory 201236 kb
Host smart-a0c95751-a335-45b6-9f52-09282e7333d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=723350959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.723350959
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1196955933
Short name T320
Test name
Test status
Simulation time 535820745598 ps
CPU time 1262.77 seconds
Started Jul 27 06:35:26 PM PDT 24
Finished Jul 27 06:56:29 PM PDT 24
Peak memory 201200 kb
Host smart-34e730bd-be74-4f65-ab0f-0d66177eee43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196955933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1196955933
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1776503022
Short name T490
Test name
Test status
Simulation time 207403599595 ps
CPU time 105.48 seconds
Started Jul 27 06:35:23 PM PDT 24
Finished Jul 27 06:37:09 PM PDT 24
Peak memory 201240 kb
Host smart-86a08e30-5f55-4636-bb26-1a869910b4b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776503022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1776503022
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.933621809
Short name T722
Test name
Test status
Simulation time 89028251362 ps
CPU time 390.86 seconds
Started Jul 27 06:35:26 PM PDT 24
Finished Jul 27 06:41:57 PM PDT 24
Peak memory 201740 kb
Host smart-2d74d8c9-dd63-4786-8831-19fab022f5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933621809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.933621809
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2232628018
Short name T374
Test name
Test status
Simulation time 45254896506 ps
CPU time 7.05 seconds
Started Jul 27 06:35:26 PM PDT 24
Finished Jul 27 06:35:33 PM PDT 24
Peak memory 201056 kb
Host smart-3e86b08e-3f8b-49e4-af09-54162d1fba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232628018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2232628018
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4169933280
Short name T509
Test name
Test status
Simulation time 4221456762 ps
CPU time 2.95 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:35:28 PM PDT 24
Peak memory 201068 kb
Host smart-43914eb6-bc8b-4e27-ad84-8237d93b31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169933280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4169933280
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.548491444
Short name T79
Test name
Test status
Simulation time 4032636959 ps
CPU time 5.04 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:35:44 PM PDT 24
Peak memory 216828 kb
Host smart-f487082a-8645-4379-95ca-f1b299dccc2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548491444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.548491444
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.218996760
Short name T154
Test name
Test status
Simulation time 6296130779 ps
CPU time 2.57 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:35:27 PM PDT 24
Peak memory 201288 kb
Host smart-273fabaf-6e56-4fac-98da-1f2596dddb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218996760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.218996760
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.711492368
Short name T659
Test name
Test status
Simulation time 334790514589 ps
CPU time 97.77 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:37:13 PM PDT 24
Peak memory 201240 kb
Host smart-8d7a5a32-7246-4aab-b129-b2718d79d3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711492368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.711492368
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4152421593
Short name T22
Test name
Test status
Simulation time 190309667319 ps
CPU time 101.36 seconds
Started Jul 27 06:35:25 PM PDT 24
Finished Jul 27 06:37:07 PM PDT 24
Peak memory 209656 kb
Host smart-73634260-8069-4233-ba4e-53b00fa9b53a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152421593 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4152421593
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2141315483
Short name T677
Test name
Test status
Simulation time 553528867 ps
CPU time 0.74 seconds
Started Jul 27 06:38:55 PM PDT 24
Finished Jul 27 06:38:56 PM PDT 24
Peak memory 200980 kb
Host smart-0516d996-1628-4916-9bf5-68a3e53a4c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141315483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2141315483
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3835999629
Short name T516
Test name
Test status
Simulation time 407779598268 ps
CPU time 84.04 seconds
Started Jul 27 06:38:55 PM PDT 24
Finished Jul 27 06:40:19 PM PDT 24
Peak memory 201252 kb
Host smart-8170917f-e30b-408f-85ea-a904952140c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835999629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3835999629
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3459211924
Short name T454
Test name
Test status
Simulation time 332840502775 ps
CPU time 724.68 seconds
Started Jul 27 06:38:44 PM PDT 24
Finished Jul 27 06:50:48 PM PDT 24
Peak memory 201244 kb
Host smart-bc4c5176-1aed-4584-8d94-245828359183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459211924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3459211924
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2524603692
Short name T216
Test name
Test status
Simulation time 492539671511 ps
CPU time 1170.73 seconds
Started Jul 27 06:38:47 PM PDT 24
Finished Jul 27 06:58:18 PM PDT 24
Peak memory 201216 kb
Host smart-f72d5fc6-7d72-48f9-a0b6-aa691b1b3d3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524603692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2524603692
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.99013550
Short name T726
Test name
Test status
Simulation time 494212674307 ps
CPU time 462.1 seconds
Started Jul 27 06:38:44 PM PDT 24
Finished Jul 27 06:46:26 PM PDT 24
Peak memory 201244 kb
Host smart-c81c127b-5ef3-4056-adf6-efb4094ec36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99013550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.99013550
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2183814489
Short name T418
Test name
Test status
Simulation time 337287651000 ps
CPU time 837.06 seconds
Started Jul 27 06:38:45 PM PDT 24
Finished Jul 27 06:52:43 PM PDT 24
Peak memory 201192 kb
Host smart-6cdb116d-3465-4cdd-aea8-93ee25bb6ae8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183814489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2183814489
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2415690334
Short name T165
Test name
Test status
Simulation time 560531992501 ps
CPU time 671.98 seconds
Started Jul 27 06:38:45 PM PDT 24
Finished Jul 27 06:49:57 PM PDT 24
Peak memory 201240 kb
Host smart-450e4f5a-0e4e-490e-a055-1a464390ae4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415690334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2415690334
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3779758422
Short name T436
Test name
Test status
Simulation time 197090664026 ps
CPU time 284.53 seconds
Started Jul 27 06:38:56 PM PDT 24
Finished Jul 27 06:43:41 PM PDT 24
Peak memory 201292 kb
Host smart-3bcbe762-b40d-40fc-ba5a-d1f0bf2f8948
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779758422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3779758422
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1036230632
Short name T487
Test name
Test status
Simulation time 120575622756 ps
CPU time 623.6 seconds
Started Jul 27 06:38:52 PM PDT 24
Finished Jul 27 06:49:16 PM PDT 24
Peak memory 201660 kb
Host smart-f0dc323c-250d-4a22-abbf-2445fd4fced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036230632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1036230632
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2063515236
Short name T397
Test name
Test status
Simulation time 25927505678 ps
CPU time 15.59 seconds
Started Jul 27 06:38:54 PM PDT 24
Finished Jul 27 06:39:10 PM PDT 24
Peak memory 201020 kb
Host smart-86b2c0f9-0612-4c00-8638-462d134e3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063515236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2063515236
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2400195671
Short name T579
Test name
Test status
Simulation time 3041852422 ps
CPU time 2.5 seconds
Started Jul 27 06:38:55 PM PDT 24
Finished Jul 27 06:38:58 PM PDT 24
Peak memory 201072 kb
Host smart-10373537-eaa7-45e6-9a12-de56290f7d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400195671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2400195671
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2990941081
Short name T763
Test name
Test status
Simulation time 5633331502 ps
CPU time 4.35 seconds
Started Jul 27 06:38:47 PM PDT 24
Finished Jul 27 06:38:51 PM PDT 24
Peak memory 201104 kb
Host smart-2535a1f0-01b7-4233-a7bd-dbe0cc92524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990941081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2990941081
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.965577970
Short name T655
Test name
Test status
Simulation time 171830320997 ps
CPU time 38.14 seconds
Started Jul 27 06:38:54 PM PDT 24
Finished Jul 27 06:39:32 PM PDT 24
Peak memory 201312 kb
Host smart-e2b94c8c-3cfa-44e5-a151-fb41ce5cc07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965577970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
965577970
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1129169724
Short name T517
Test name
Test status
Simulation time 76885674846 ps
CPU time 79.82 seconds
Started Jul 27 06:38:56 PM PDT 24
Finished Jul 27 06:40:16 PM PDT 24
Peak memory 210048 kb
Host smart-2ca15499-8be4-4c1f-8216-0ddf3edda355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129169724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1129169724
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1460116451
Short name T16
Test name
Test status
Simulation time 299676919 ps
CPU time 0.83 seconds
Started Jul 27 06:39:13 PM PDT 24
Finished Jul 27 06:39:14 PM PDT 24
Peak memory 200984 kb
Host smart-c9dbe9a0-2d84-4ad1-a994-776537a550aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460116451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1460116451
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.172483956
Short name T562
Test name
Test status
Simulation time 332203438516 ps
CPU time 751.56 seconds
Started Jul 27 06:39:03 PM PDT 24
Finished Jul 27 06:51:35 PM PDT 24
Peak memory 201204 kb
Host smart-da91b1e5-2542-4c45-9e8c-6732f808ce53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172483956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.172483956
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.282752649
Short name T198
Test name
Test status
Simulation time 488837770739 ps
CPU time 629.29 seconds
Started Jul 27 06:39:05 PM PDT 24
Finished Jul 27 06:49:34 PM PDT 24
Peak memory 201192 kb
Host smart-14987768-2ee0-4091-a3b2-9c671be55775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282752649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.282752649
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.611566984
Short name T96
Test name
Test status
Simulation time 166237459439 ps
CPU time 404.14 seconds
Started Jul 27 06:39:02 PM PDT 24
Finished Jul 27 06:45:47 PM PDT 24
Peak memory 201248 kb
Host smart-6e6ca9f8-3cda-47bc-9bbb-6a0b8170e87e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=611566984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.611566984
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2720416676
Short name T175
Test name
Test status
Simulation time 161681719505 ps
CPU time 92.27 seconds
Started Jul 27 06:39:02 PM PDT 24
Finished Jul 27 06:40:34 PM PDT 24
Peak memory 201200 kb
Host smart-3d6c55eb-9938-407f-bac7-19f4bc058844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720416676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2720416676
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2886631179
Short name T561
Test name
Test status
Simulation time 166469396469 ps
CPU time 393.03 seconds
Started Jul 27 06:39:03 PM PDT 24
Finished Jul 27 06:45:36 PM PDT 24
Peak memory 201176 kb
Host smart-34da3175-fdde-4bbe-a3ed-143b45b97525
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886631179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2886631179
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.491720923
Short name T681
Test name
Test status
Simulation time 546047642363 ps
CPU time 471.69 seconds
Started Jul 27 06:39:03 PM PDT 24
Finished Jul 27 06:46:55 PM PDT 24
Peak memory 201200 kb
Host smart-9cf1117a-2c9a-4018-8840-40e41f947383
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491720923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.491720923
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3711850205
Short name T106
Test name
Test status
Simulation time 199278357852 ps
CPU time 43.93 seconds
Started Jul 27 06:39:04 PM PDT 24
Finished Jul 27 06:39:48 PM PDT 24
Peak memory 201192 kb
Host smart-d38302a7-708d-43ad-98b0-2c7169499f2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711850205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3711850205
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3436486760
Short name T702
Test name
Test status
Simulation time 78553185290 ps
CPU time 302.53 seconds
Started Jul 27 06:39:03 PM PDT 24
Finished Jul 27 06:44:06 PM PDT 24
Peak memory 201684 kb
Host smart-d1132741-50db-4545-a378-b9606d316930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436486760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3436486760
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3943429326
Short name T751
Test name
Test status
Simulation time 40242856708 ps
CPU time 15.24 seconds
Started Jul 27 06:39:06 PM PDT 24
Finished Jul 27 06:39:21 PM PDT 24
Peak memory 201080 kb
Host smart-9bb07a7a-e3ff-4e66-b40a-1bcca424ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943429326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3943429326
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.408205886
Short name T614
Test name
Test status
Simulation time 3138953342 ps
CPU time 2.12 seconds
Started Jul 27 06:39:06 PM PDT 24
Finished Jul 27 06:39:08 PM PDT 24
Peak memory 201048 kb
Host smart-7c6cbec9-43df-4a6d-86b5-d647e1c69d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408205886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.408205886
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3984166701
Short name T720
Test name
Test status
Simulation time 5956433879 ps
CPU time 8.2 seconds
Started Jul 27 06:39:02 PM PDT 24
Finished Jul 27 06:39:10 PM PDT 24
Peak memory 201104 kb
Host smart-a0c1c5fc-b429-4936-9014-0d9f3136d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984166701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3984166701
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1898268649
Short name T451
Test name
Test status
Simulation time 172739214163 ps
CPU time 756.3 seconds
Started Jul 27 06:39:02 PM PDT 24
Finished Jul 27 06:51:39 PM PDT 24
Peak memory 209872 kb
Host smart-c7a8027d-5453-4ed0-b846-643e25b03d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898268649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1898268649
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.840513317
Short name T792
Test name
Test status
Simulation time 35799971131 ps
CPU time 44.29 seconds
Started Jul 27 06:39:03 PM PDT 24
Finished Jul 27 06:39:47 PM PDT 24
Peak memory 209628 kb
Host smart-d567d0b2-00e3-492a-8a5d-63c63b561236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840513317 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.840513317
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3515890227
Short name T596
Test name
Test status
Simulation time 540788334 ps
CPU time 0.66 seconds
Started Jul 27 06:39:21 PM PDT 24
Finished Jul 27 06:39:22 PM PDT 24
Peak memory 201000 kb
Host smart-b27c1f0a-5f77-4798-9aff-5d78c8e269f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515890227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3515890227
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.886937184
Short name T727
Test name
Test status
Simulation time 613160138430 ps
CPU time 209.29 seconds
Started Jul 27 06:39:12 PM PDT 24
Finished Jul 27 06:42:41 PM PDT 24
Peak memory 201192 kb
Host smart-0aa144c0-18e5-48e8-bd8d-c116de3cbb51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886937184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.886937184
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1051708127
Short name T293
Test name
Test status
Simulation time 370574749284 ps
CPU time 77.92 seconds
Started Jul 27 06:39:12 PM PDT 24
Finished Jul 27 06:40:31 PM PDT 24
Peak memory 201176 kb
Host smart-bdb8edf7-1c7c-4f46-b31f-65c7692f948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051708127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1051708127
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3747053538
Short name T140
Test name
Test status
Simulation time 169037199537 ps
CPU time 196.94 seconds
Started Jul 27 06:39:12 PM PDT 24
Finished Jul 27 06:42:29 PM PDT 24
Peak memory 201204 kb
Host smart-e20bca3c-d6e7-4f03-b7d1-799dd7b8d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747053538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3747053538
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3229665645
Short name T629
Test name
Test status
Simulation time 162585263344 ps
CPU time 73.59 seconds
Started Jul 27 06:39:16 PM PDT 24
Finished Jul 27 06:40:29 PM PDT 24
Peak memory 201244 kb
Host smart-2e9ef080-5b34-4018-908d-259209697511
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229665645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3229665645
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2910893701
Short name T401
Test name
Test status
Simulation time 326530721702 ps
CPU time 182.8 seconds
Started Jul 27 06:39:13 PM PDT 24
Finished Jul 27 06:42:16 PM PDT 24
Peak memory 201208 kb
Host smart-050254d1-9193-49ae-a429-fef54b2dda50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910893701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2910893701
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1500282521
Short name T749
Test name
Test status
Simulation time 194952400333 ps
CPU time 111.7 seconds
Started Jul 27 06:39:13 PM PDT 24
Finished Jul 27 06:41:05 PM PDT 24
Peak memory 201216 kb
Host smart-b93521a0-a8c3-4e7a-aa31-0d35e1591ec7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500282521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1500282521
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2531439376
Short name T98
Test name
Test status
Simulation time 404644745393 ps
CPU time 275.97 seconds
Started Jul 27 06:39:11 PM PDT 24
Finished Jul 27 06:43:47 PM PDT 24
Peak memory 201228 kb
Host smart-33e53642-b357-4f92-84d0-da88d449a5ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531439376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2531439376
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2418750208
Short name T31
Test name
Test status
Simulation time 129969742765 ps
CPU time 678.09 seconds
Started Jul 27 06:39:24 PM PDT 24
Finished Jul 27 06:50:42 PM PDT 24
Peak memory 201652 kb
Host smart-a41e4a4e-28ac-499e-9e44-ec07d461798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418750208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2418750208
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4190119259
Short name T719
Test name
Test status
Simulation time 25546771027 ps
CPU time 15.37 seconds
Started Jul 27 06:39:21 PM PDT 24
Finished Jul 27 06:39:37 PM PDT 24
Peak memory 201040 kb
Host smart-6de9800c-3beb-46c3-ae19-384337d12c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190119259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4190119259
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4176672410
Short name T661
Test name
Test status
Simulation time 3442381468 ps
CPU time 2.5 seconds
Started Jul 27 06:39:23 PM PDT 24
Finished Jul 27 06:39:26 PM PDT 24
Peak memory 201024 kb
Host smart-4c35f376-2ddd-4666-8521-20398ed357d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176672410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4176672410
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3660932203
Short name T793
Test name
Test status
Simulation time 5997017591 ps
CPU time 8.35 seconds
Started Jul 27 06:39:14 PM PDT 24
Finished Jul 27 06:39:23 PM PDT 24
Peak memory 201072 kb
Host smart-3834849d-14e8-4e1c-b17a-1a662b32246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660932203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3660932203
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3882124460
Short name T20
Test name
Test status
Simulation time 18714450338 ps
CPU time 68.49 seconds
Started Jul 27 06:39:23 PM PDT 24
Finished Jul 27 06:40:31 PM PDT 24
Peak memory 210008 kb
Host smart-2fb648d1-a6d6-48d8-aa86-9348efd84e99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882124460 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3882124460
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1337522714
Short name T408
Test name
Test status
Simulation time 375000571 ps
CPU time 1.35 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:39:33 PM PDT 24
Peak memory 200964 kb
Host smart-7334815b-c111-4720-b4c2-86c03f2ef8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337522714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1337522714
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2054788362
Short name T571
Test name
Test status
Simulation time 173617497782 ps
CPU time 353.15 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:45:25 PM PDT 24
Peak memory 201200 kb
Host smart-00f5c2cf-8d80-4e0b-ab33-f2fa9dd0d1ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054788362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2054788362
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.9777931
Short name T99
Test name
Test status
Simulation time 170439353860 ps
CPU time 101.11 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:41:11 PM PDT 24
Peak memory 201196 kb
Host smart-117afd99-fa77-4081-b799-a9a0c2579f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9777931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.9777931
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1114686526
Short name T613
Test name
Test status
Simulation time 326444791850 ps
CPU time 803.88 seconds
Started Jul 27 06:39:22 PM PDT 24
Finished Jul 27 06:52:46 PM PDT 24
Peak memory 201140 kb
Host smart-19f0ae52-9d88-4190-90ce-9482261fdbdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114686526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1114686526
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4185130302
Short name T603
Test name
Test status
Simulation time 497589829322 ps
CPU time 274.65 seconds
Started Jul 27 06:39:21 PM PDT 24
Finished Jul 27 06:43:56 PM PDT 24
Peak memory 201124 kb
Host smart-2ceeae64-f367-4d0c-894a-7e1e8de0e6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185130302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4185130302
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3592714858
Short name T464
Test name
Test status
Simulation time 328014745997 ps
CPU time 106.24 seconds
Started Jul 27 06:39:22 PM PDT 24
Finished Jul 27 06:41:09 PM PDT 24
Peak memory 201172 kb
Host smart-72e8ab1d-a677-4e3f-a2a0-e3bd7a2ae74f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592714858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3592714858
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1231015637
Short name T28
Test name
Test status
Simulation time 360662830677 ps
CPU time 434.94 seconds
Started Jul 27 06:39:22 PM PDT 24
Finished Jul 27 06:46:37 PM PDT 24
Peak memory 201224 kb
Host smart-e8db5948-5e37-4cb7-a837-857c9e08c5d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231015637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1231015637
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1124284327
Short name T403
Test name
Test status
Simulation time 397772670941 ps
CPU time 956.47 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:55:27 PM PDT 24
Peak memory 201260 kb
Host smart-45efb99d-0451-4964-b630-cfe51d3bd572
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124284327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1124284327
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2604697805
Short name T337
Test name
Test status
Simulation time 120833277615 ps
CPU time 556.7 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:48:48 PM PDT 24
Peak memory 201684 kb
Host smart-305c7bde-d6ff-456a-b6ca-521f4712aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604697805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2604697805
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3978969894
Short name T466
Test name
Test status
Simulation time 40888004349 ps
CPU time 24.78 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:39:56 PM PDT 24
Peak memory 201060 kb
Host smart-cc6a4b43-793a-4277-8440-5b520f33456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978969894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3978969894
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3681775663
Short name T446
Test name
Test status
Simulation time 4115553687 ps
CPU time 5.37 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:39:37 PM PDT 24
Peak memory 201012 kb
Host smart-728a438b-6547-4847-b3fa-890f9be4646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681775663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3681775663
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1250201243
Short name T556
Test name
Test status
Simulation time 5561439514 ps
CPU time 13.22 seconds
Started Jul 27 06:39:21 PM PDT 24
Finished Jul 27 06:39:34 PM PDT 24
Peak memory 201044 kb
Host smart-10334d65-621b-44aa-972b-47f447f1eea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250201243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1250201243
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4007536983
Short name T157
Test name
Test status
Simulation time 316230849876 ps
CPU time 1081.62 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:57:32 PM PDT 24
Peak memory 209860 kb
Host smart-340fc9e7-c91c-4a1b-90aa-32cf1ee41b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007536983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4007536983
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3750706775
Short name T354
Test name
Test status
Simulation time 309780117803 ps
CPU time 268.2 seconds
Started Jul 27 06:39:29 PM PDT 24
Finished Jul 27 06:43:57 PM PDT 24
Peak memory 209920 kb
Host smart-797cc02d-bc82-4a83-b422-28e60088041c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750706775 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3750706775
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.960816972
Short name T554
Test name
Test status
Simulation time 301057365 ps
CPU time 1.3 seconds
Started Jul 27 06:39:41 PM PDT 24
Finished Jul 27 06:39:42 PM PDT 24
Peak memory 201024 kb
Host smart-ec1cc592-7eeb-46cf-b3cf-c8e75718893b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960816972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.960816972
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2799507186
Short name T7
Test name
Test status
Simulation time 163728060208 ps
CPU time 47 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:40:19 PM PDT 24
Peak memory 201180 kb
Host smart-46b53c97-dea7-42eb-91cc-0391406ff91c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799507186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2799507186
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1258066591
Short name T500
Test name
Test status
Simulation time 333763528729 ps
CPU time 413.29 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:46:24 PM PDT 24
Peak memory 201248 kb
Host smart-33f83cd0-2607-4180-8d93-d7c6a86503a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258066591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1258066591
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1690737176
Short name T542
Test name
Test status
Simulation time 482055178366 ps
CPU time 906.76 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:54:37 PM PDT 24
Peak memory 201200 kb
Host smart-0213d156-240f-4a5b-8e57-80b68cc31901
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690737176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1690737176
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.837530757
Short name T767
Test name
Test status
Simulation time 324852100817 ps
CPU time 186.53 seconds
Started Jul 27 06:39:31 PM PDT 24
Finished Jul 27 06:42:37 PM PDT 24
Peak memory 201180 kb
Host smart-9a32425a-3872-475e-91e0-b56b809708b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837530757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.837530757
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2584999585
Short name T526
Test name
Test status
Simulation time 497133315766 ps
CPU time 1129.31 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:58:20 PM PDT 24
Peak memory 201220 kb
Host smart-c0455374-136e-488e-a152-3f00085bbd90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584999585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2584999585
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2652742331
Short name T251
Test name
Test status
Simulation time 362249511837 ps
CPU time 212.45 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:43:03 PM PDT 24
Peak memory 201220 kb
Host smart-e39dc16c-a10f-42d8-a59b-82d4c0577377
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652742331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2652742331
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2167146180
Short name T234
Test name
Test status
Simulation time 591283830198 ps
CPU time 1408.62 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 07:02:59 PM PDT 24
Peak memory 201152 kb
Host smart-dcb70df9-0126-4bd3-8bbb-eac25982a97f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167146180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2167146180
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2214628145
Short name T644
Test name
Test status
Simulation time 67671366417 ps
CPU time 255.99 seconds
Started Jul 27 06:39:39 PM PDT 24
Finished Jul 27 06:43:55 PM PDT 24
Peak memory 201624 kb
Host smart-d9eb896e-100b-426c-bc78-d7eadd809559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214628145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2214628145
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1680047616
Short name T736
Test name
Test status
Simulation time 29143880746 ps
CPU time 16.17 seconds
Started Jul 27 06:39:39 PM PDT 24
Finished Jul 27 06:39:55 PM PDT 24
Peak memory 201076 kb
Host smart-1f7dd4e8-6f1a-4bd4-aa6f-f011b44e2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680047616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1680047616
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.447959070
Short name T672
Test name
Test status
Simulation time 4258124538 ps
CPU time 3.2 seconds
Started Jul 27 06:39:41 PM PDT 24
Finished Jul 27 06:39:44 PM PDT 24
Peak memory 201040 kb
Host smart-73f35fd6-c9fe-42b7-85d8-187543bf11f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447959070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.447959070
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1820348031
Short name T790
Test name
Test status
Simulation time 6034139214 ps
CPU time 8.09 seconds
Started Jul 27 06:39:30 PM PDT 24
Finished Jul 27 06:39:38 PM PDT 24
Peak memory 201104 kb
Host smart-acc81c71-99de-4162-a198-303575920bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820348031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1820348031
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2047183580
Short name T268
Test name
Test status
Simulation time 363238743145 ps
CPU time 124.9 seconds
Started Jul 27 06:39:42 PM PDT 24
Finished Jul 27 06:41:47 PM PDT 24
Peak memory 201244 kb
Host smart-8f7c5c06-6b90-4456-a96d-9c1d1c3a5de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047183580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2047183580
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.236517217
Short name T486
Test name
Test status
Simulation time 336421261 ps
CPU time 0.81 seconds
Started Jul 27 06:39:57 PM PDT 24
Finished Jul 27 06:39:57 PM PDT 24
Peak memory 201036 kb
Host smart-a72d5ad1-25cf-4898-87af-b3254d05d9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236517217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.236517217
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.325725194
Short name T303
Test name
Test status
Simulation time 338325239476 ps
CPU time 569.19 seconds
Started Jul 27 06:39:49 PM PDT 24
Finished Jul 27 06:49:18 PM PDT 24
Peak memory 201276 kb
Host smart-7f30d82d-f539-49ed-9d78-9d435a884279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325725194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.325725194
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.163263970
Short name T413
Test name
Test status
Simulation time 165554007763 ps
CPU time 377.45 seconds
Started Jul 27 06:39:49 PM PDT 24
Finished Jul 27 06:46:06 PM PDT 24
Peak memory 201132 kb
Host smart-5d62cd7a-1030-4ceb-ab27-90e5f8928706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=163263970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.163263970
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.108075239
Short name T743
Test name
Test status
Simulation time 163618755207 ps
CPU time 333.15 seconds
Started Jul 27 06:39:42 PM PDT 24
Finished Jul 27 06:45:15 PM PDT 24
Peak memory 201216 kb
Host smart-9bff0d18-cca5-48e1-bbbe-8ef3353d3066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108075239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.108075239
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3161786321
Short name T440
Test name
Test status
Simulation time 331148836282 ps
CPU time 780.7 seconds
Started Jul 27 06:39:46 PM PDT 24
Finished Jul 27 06:52:47 PM PDT 24
Peak memory 201208 kb
Host smart-71205114-f162-46d1-a320-00bf0deaf7c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161786321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3161786321
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2098167629
Short name T704
Test name
Test status
Simulation time 396782068032 ps
CPU time 102.58 seconds
Started Jul 27 06:39:47 PM PDT 24
Finished Jul 27 06:41:29 PM PDT 24
Peak memory 201232 kb
Host smart-e6a90645-4f46-4140-8129-fee1a17c2898
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098167629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2098167629
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.484088561
Short name T104
Test name
Test status
Simulation time 74640736800 ps
CPU time 250.17 seconds
Started Jul 27 06:39:47 PM PDT 24
Finished Jul 27 06:43:58 PM PDT 24
Peak memory 201684 kb
Host smart-1d066fe5-41a7-4ce0-8660-13d98650bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484088561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.484088561
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2086821396
Short name T691
Test name
Test status
Simulation time 26864775068 ps
CPU time 62.91 seconds
Started Jul 27 06:39:48 PM PDT 24
Finished Jul 27 06:40:51 PM PDT 24
Peak memory 201040 kb
Host smart-d3219999-e241-4a0e-a89f-eeeb39c523ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086821396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2086821396
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3574459202
Short name T378
Test name
Test status
Simulation time 3338361238 ps
CPU time 2.74 seconds
Started Jul 27 06:39:48 PM PDT 24
Finished Jul 27 06:39:51 PM PDT 24
Peak memory 201092 kb
Host smart-42f38c2c-656a-4f74-992a-11f5a835057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574459202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3574459202
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.395845939
Short name T557
Test name
Test status
Simulation time 5884698638 ps
CPU time 13.37 seconds
Started Jul 27 06:39:41 PM PDT 24
Finished Jul 27 06:39:54 PM PDT 24
Peak memory 201148 kb
Host smart-af51ab5f-7b77-47dc-ac89-cd29b3f28a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395845939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.395845939
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3717886841
Short name T137
Test name
Test status
Simulation time 326063132033 ps
CPU time 167.01 seconds
Started Jul 27 06:39:56 PM PDT 24
Finished Jul 27 06:42:43 PM PDT 24
Peak memory 201224 kb
Host smart-1d722d2f-33cb-4e2b-b60a-5744b558de3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717886841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3717886841
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3696566357
Short name T599
Test name
Test status
Simulation time 89528583211 ps
CPU time 50.97 seconds
Started Jul 27 06:39:48 PM PDT 24
Finished Jul 27 06:40:39 PM PDT 24
Peak memory 209564 kb
Host smart-b1991738-d450-4ff5-949b-4d823a11d888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696566357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3696566357
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1268607752
Short name T467
Test name
Test status
Simulation time 523068031 ps
CPU time 1.13 seconds
Started Jul 27 06:40:11 PM PDT 24
Finished Jul 27 06:40:12 PM PDT 24
Peak memory 201044 kb
Host smart-19cac1c2-a747-4238-8b1f-069c99e0b740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268607752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1268607752
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.13882604
Short name T381
Test name
Test status
Simulation time 495017404323 ps
CPU time 1077.18 seconds
Started Jul 27 06:39:56 PM PDT 24
Finished Jul 27 06:57:54 PM PDT 24
Peak memory 201236 kb
Host smart-c7b03db6-78da-432d-9b1e-768507019de4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt
_fixed.13882604
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3662406265
Short name T134
Test name
Test status
Simulation time 171983017844 ps
CPU time 98.88 seconds
Started Jul 27 06:39:55 PM PDT 24
Finished Jul 27 06:41:34 PM PDT 24
Peak memory 201196 kb
Host smart-f7a9a574-0767-42c8-b418-4b892badfc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662406265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3662406265
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3475968041
Short name T731
Test name
Test status
Simulation time 481451282440 ps
CPU time 336.15 seconds
Started Jul 27 06:39:55 PM PDT 24
Finished Jul 27 06:45:31 PM PDT 24
Peak memory 201176 kb
Host smart-0b6c5903-89c4-43d5-90ce-71eef3968934
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475968041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3475968041
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2199759110
Short name T788
Test name
Test status
Simulation time 395264557576 ps
CPU time 446.21 seconds
Started Jul 27 06:40:07 PM PDT 24
Finished Jul 27 06:47:33 PM PDT 24
Peak memory 201272 kb
Host smart-3ddf41d9-d7de-47b3-a953-77f0aac133d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199759110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2199759110
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2026811271
Short name T406
Test name
Test status
Simulation time 88245835008 ps
CPU time 414.01 seconds
Started Jul 27 06:40:09 PM PDT 24
Finished Jul 27 06:47:04 PM PDT 24
Peak memory 201768 kb
Host smart-6c8c7cc1-b6c4-4389-897b-d463dd6a5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026811271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2026811271
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2980917868
Short name T459
Test name
Test status
Simulation time 29437231694 ps
CPU time 18.13 seconds
Started Jul 27 06:40:05 PM PDT 24
Finished Jul 27 06:40:23 PM PDT 24
Peak memory 201072 kb
Host smart-fb05fda5-d97b-450a-8ccf-e9cede332d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980917868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2980917868
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2535871476
Short name T637
Test name
Test status
Simulation time 2901806662 ps
CPU time 2.48 seconds
Started Jul 27 06:40:07 PM PDT 24
Finished Jul 27 06:40:10 PM PDT 24
Peak memory 200980 kb
Host smart-fb976f5d-1175-4cdc-a0b9-3d46c67a6ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535871476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2535871476
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3688845225
Short name T503
Test name
Test status
Simulation time 5621078009 ps
CPU time 15.06 seconds
Started Jul 27 06:39:57 PM PDT 24
Finished Jul 27 06:40:12 PM PDT 24
Peak memory 201116 kb
Host smart-82f2a12d-ddf5-4b10-a034-128bd908caa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688845225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3688845225
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4210884821
Short name T309
Test name
Test status
Simulation time 372966511091 ps
CPU time 217.63 seconds
Started Jul 27 06:40:11 PM PDT 24
Finished Jul 27 06:43:49 PM PDT 24
Peak memory 201268 kb
Host smart-844ee1dd-d061-4411-aad1-eb8c599034c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210884821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4210884821
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.4162507531
Short name T17
Test name
Test status
Simulation time 255569032068 ps
CPU time 47.15 seconds
Started Jul 27 06:40:07 PM PDT 24
Finished Jul 27 06:40:54 PM PDT 24
Peak memory 209548 kb
Host smart-2cc2eee3-f159-4285-a44b-4cb194356117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162507531 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.4162507531
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2673424055
Short name T484
Test name
Test status
Simulation time 324910641 ps
CPU time 0.74 seconds
Started Jul 27 06:40:20 PM PDT 24
Finished Jul 27 06:40:21 PM PDT 24
Peak memory 201020 kb
Host smart-49826139-c889-473e-a5e1-2ec62b90da43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673424055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2673424055
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.201296676
Short name T207
Test name
Test status
Simulation time 490000421255 ps
CPU time 786.87 seconds
Started Jul 27 06:40:15 PM PDT 24
Finished Jul 27 06:53:22 PM PDT 24
Peak memory 201200 kb
Host smart-e7bc0e75-ab26-4198-8f60-1bd1a682d63f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201296676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.201296676
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1786818607
Short name T568
Test name
Test status
Simulation time 167140639981 ps
CPU time 398.03 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:46:52 PM PDT 24
Peak memory 201296 kb
Host smart-9e32e879-fd50-473a-909b-b330d200256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786818607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1786818607
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1633216631
Short name T593
Test name
Test status
Simulation time 323207827158 ps
CPU time 390.47 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:46:44 PM PDT 24
Peak memory 201300 kb
Host smart-fcc88346-9ff0-4f1c-9a98-804622752067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633216631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1633216631
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3117630652
Short name T546
Test name
Test status
Simulation time 494069061747 ps
CPU time 1107.56 seconds
Started Jul 27 06:40:13 PM PDT 24
Finished Jul 27 06:58:40 PM PDT 24
Peak memory 201196 kb
Host smart-e2e8c6c1-7219-4927-b4f6-d572d6c3b5ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117630652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3117630652
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1283499704
Short name T565
Test name
Test status
Simulation time 166559919706 ps
CPU time 188.22 seconds
Started Jul 27 06:40:10 PM PDT 24
Finished Jul 27 06:43:18 PM PDT 24
Peak memory 201268 kb
Host smart-e00e1da2-6d7c-404a-81e4-b3c3d0901f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283499704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1283499704
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1477213124
Short name T753
Test name
Test status
Simulation time 493790266085 ps
CPU time 354.35 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:46:08 PM PDT 24
Peak memory 201160 kb
Host smart-13ad6cc1-bcac-4fb2-87b1-0e73e78ec4ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477213124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1477213124
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1748927144
Short name T82
Test name
Test status
Simulation time 589411440187 ps
CPU time 221.29 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:43:55 PM PDT 24
Peak memory 201284 kb
Host smart-2c95e616-9204-41e1-b4f9-042278ce6dfd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748927144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1748927144
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1462156902
Short name T572
Test name
Test status
Simulation time 115624520507 ps
CPU time 411.03 seconds
Started Jul 27 06:40:13 PM PDT 24
Finished Jul 27 06:47:04 PM PDT 24
Peak memory 201652 kb
Host smart-f3c084d3-6d83-4521-a677-0863e59a86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462156902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1462156902
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.480531872
Short name T410
Test name
Test status
Simulation time 31020230937 ps
CPU time 70.55 seconds
Started Jul 27 06:40:16 PM PDT 24
Finished Jul 27 06:41:27 PM PDT 24
Peak memory 201088 kb
Host smart-f94b242b-b603-485a-bcca-724935e93330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480531872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.480531872
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1541754017
Short name T385
Test name
Test status
Simulation time 5508329455 ps
CPU time 7.45 seconds
Started Jul 27 06:40:15 PM PDT 24
Finished Jul 27 06:40:22 PM PDT 24
Peak memory 201020 kb
Host smart-e2200a4b-3bf2-426d-b8a5-0bfe27daba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541754017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1541754017
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.108778576
Short name T417
Test name
Test status
Simulation time 5803099646 ps
CPU time 7.06 seconds
Started Jul 27 06:40:06 PM PDT 24
Finished Jul 27 06:40:13 PM PDT 24
Peak memory 201008 kb
Host smart-43a7c15e-dfc6-4059-9bbe-4c952f7dd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108778576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.108778576
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2447907708
Short name T190
Test name
Test status
Simulation time 542346211781 ps
CPU time 319.28 seconds
Started Jul 27 06:40:17 PM PDT 24
Finished Jul 27 06:45:37 PM PDT 24
Peak memory 201252 kb
Host smart-746968e8-ca53-438d-8320-3f80b6287949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447907708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2447907708
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3642439679
Short name T511
Test name
Test status
Simulation time 354986244 ps
CPU time 0.79 seconds
Started Jul 27 06:40:34 PM PDT 24
Finished Jul 27 06:40:35 PM PDT 24
Peak memory 200976 kb
Host smart-7253e586-e902-4ab5-a845-e002e0748064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642439679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3642439679
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3146354914
Short name T221
Test name
Test status
Simulation time 416593502928 ps
CPU time 968.12 seconds
Started Jul 27 06:40:21 PM PDT 24
Finished Jul 27 06:56:29 PM PDT 24
Peak memory 201248 kb
Host smart-2ec76b76-7410-4177-8779-c9e61fac2196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146354914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3146354914
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.565737733
Short name T746
Test name
Test status
Simulation time 160984014639 ps
CPU time 96.82 seconds
Started Jul 27 06:40:21 PM PDT 24
Finished Jul 27 06:41:58 PM PDT 24
Peak memory 201136 kb
Host smart-6aac712c-fb71-4c67-b7a0-404f831a286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565737733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.565737733
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3896105201
Short name T155
Test name
Test status
Simulation time 162475957508 ps
CPU time 375.77 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:46:30 PM PDT 24
Peak memory 201252 kb
Host smart-73f9daa5-761d-4316-bff4-2d50d428edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896105201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3896105201
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.833220053
Short name T421
Test name
Test status
Simulation time 501897106464 ps
CPU time 1142.95 seconds
Started Jul 27 06:40:14 PM PDT 24
Finished Jul 27 06:59:17 PM PDT 24
Peak memory 201176 kb
Host smart-6556d29c-1702-4574-b289-840fa452849f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=833220053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.833220053
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.204072714
Short name T262
Test name
Test status
Simulation time 181354876756 ps
CPU time 110.25 seconds
Started Jul 27 06:40:24 PM PDT 24
Finished Jul 27 06:42:15 PM PDT 24
Peak memory 201260 kb
Host smart-c7c47b9e-5d06-4ed7-b9e5-a41f26b573b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204072714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.204072714
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2333365545
Short name T697
Test name
Test status
Simulation time 199932607434 ps
CPU time 121.67 seconds
Started Jul 27 06:40:24 PM PDT 24
Finished Jul 27 06:42:26 PM PDT 24
Peak memory 201276 kb
Host smart-f8b5cee2-b25f-44d1-8ff3-e2497e03781b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333365545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2333365545
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1651304142
Short name T685
Test name
Test status
Simulation time 28883820332 ps
CPU time 67.17 seconds
Started Jul 27 06:40:23 PM PDT 24
Finished Jul 27 06:41:30 PM PDT 24
Peak memory 201048 kb
Host smart-12193331-2f4c-48dc-9a5f-83ea1a5e9780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651304142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1651304142
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.337347664
Short name T85
Test name
Test status
Simulation time 3292838395 ps
CPU time 1.02 seconds
Started Jul 27 06:40:23 PM PDT 24
Finished Jul 27 06:40:25 PM PDT 24
Peak memory 200976 kb
Host smart-39df2f4b-c6ac-45f7-8c79-ae48a08493d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337347664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.337347664
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3723624222
Short name T650
Test name
Test status
Simulation time 5693623861 ps
CPU time 2.44 seconds
Started Jul 27 06:40:13 PM PDT 24
Finished Jul 27 06:40:16 PM PDT 24
Peak memory 201016 kb
Host smart-6f332e86-1160-45ac-aee5-ef82316fa2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723624222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3723624222
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2983525668
Short name T228
Test name
Test status
Simulation time 25646007900 ps
CPU time 45.52 seconds
Started Jul 27 06:40:24 PM PDT 24
Finished Jul 27 06:41:10 PM PDT 24
Peak memory 209588 kb
Host smart-13c8d3a1-805d-4a68-9e58-873b81339ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983525668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2983525668
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2942083793
Short name T370
Test name
Test status
Simulation time 386323470 ps
CPU time 1.51 seconds
Started Jul 27 06:40:38 PM PDT 24
Finished Jul 27 06:40:40 PM PDT 24
Peak memory 201020 kb
Host smart-df212d7a-2ff3-4fb3-b59e-affa5d957694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942083793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2942083793
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3857666497
Short name T150
Test name
Test status
Simulation time 330550890430 ps
CPU time 748.79 seconds
Started Jul 27 06:40:35 PM PDT 24
Finished Jul 27 06:53:04 PM PDT 24
Peak memory 201288 kb
Host smart-7c943495-f4fe-4029-8dce-3413adb0011d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857666497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3857666497
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3930528126
Short name T327
Test name
Test status
Simulation time 159273827696 ps
CPU time 72.65 seconds
Started Jul 27 06:40:33 PM PDT 24
Finished Jul 27 06:41:45 PM PDT 24
Peak memory 201240 kb
Host smart-dd31c3fa-8436-4e13-8668-032277ad2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930528126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3930528126
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3995531282
Short name T247
Test name
Test status
Simulation time 164252826376 ps
CPU time 106.49 seconds
Started Jul 27 06:40:32 PM PDT 24
Finished Jul 27 06:42:19 PM PDT 24
Peak memory 201240 kb
Host smart-cc77f2c4-89c4-41d9-bb72-deb540c6ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995531282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3995531282
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.487292701
Short name T577
Test name
Test status
Simulation time 165322316041 ps
CPU time 374.52 seconds
Started Jul 27 06:40:34 PM PDT 24
Finished Jul 27 06:46:48 PM PDT 24
Peak memory 201220 kb
Host smart-12bbee75-6f51-47e4-8531-e8d5d0c7be7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=487292701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.487292701
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2328719530
Short name T147
Test name
Test status
Simulation time 501259718854 ps
CPU time 303.64 seconds
Started Jul 27 06:40:32 PM PDT 24
Finished Jul 27 06:45:36 PM PDT 24
Peak memory 201268 kb
Host smart-d1715afe-adf6-49dd-80da-273d68e0d3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328719530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2328719530
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2031855629
Short name T393
Test name
Test status
Simulation time 498128637121 ps
CPU time 279.68 seconds
Started Jul 27 06:40:33 PM PDT 24
Finished Jul 27 06:45:13 PM PDT 24
Peak memory 201228 kb
Host smart-065be35b-7dd8-4727-ab0c-acf3a8778e46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031855629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2031855629
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2753351394
Short name T201
Test name
Test status
Simulation time 562482166148 ps
CPU time 294.07 seconds
Started Jul 27 06:40:33 PM PDT 24
Finished Jul 27 06:45:27 PM PDT 24
Peak memory 201184 kb
Host smart-2055d564-252b-48e1-93ff-2f9eb2103f39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753351394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2753351394
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3694233536
Short name T463
Test name
Test status
Simulation time 407437477824 ps
CPU time 829.18 seconds
Started Jul 27 06:40:38 PM PDT 24
Finished Jul 27 06:54:27 PM PDT 24
Peak memory 201208 kb
Host smart-0294f491-d81a-43c1-acac-8f12014f1e77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694233536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3694233536
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2370202395
Short name T348
Test name
Test status
Simulation time 106616112135 ps
CPU time 416.12 seconds
Started Jul 27 06:40:36 PM PDT 24
Finished Jul 27 06:47:32 PM PDT 24
Peak memory 201676 kb
Host smart-414cc7a7-9d88-4005-b00c-7ab4914bc8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370202395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2370202395
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3677652147
Short name T3
Test name
Test status
Simulation time 27159787329 ps
CPU time 15.77 seconds
Started Jul 27 06:40:32 PM PDT 24
Finished Jul 27 06:40:48 PM PDT 24
Peak memory 201048 kb
Host smart-f89bad1f-2824-494e-8844-e4cb7b1fcc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677652147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3677652147
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.636911411
Short name T130
Test name
Test status
Simulation time 3848918045 ps
CPU time 9.93 seconds
Started Jul 27 06:40:33 PM PDT 24
Finished Jul 27 06:40:43 PM PDT 24
Peak memory 201020 kb
Host smart-6e5b8f87-2356-4a58-b047-5098811da3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636911411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.636911411
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3001815511
Short name T364
Test name
Test status
Simulation time 5732316260 ps
CPU time 13.47 seconds
Started Jul 27 06:40:32 PM PDT 24
Finished Jul 27 06:40:46 PM PDT 24
Peak memory 201100 kb
Host smart-cea043b0-ab6f-401a-ab31-3edfac7e6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001815511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3001815511
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.175746803
Short name T13
Test name
Test status
Simulation time 335201893129 ps
CPU time 748.94 seconds
Started Jul 27 06:40:37 PM PDT 24
Finished Jul 27 06:53:06 PM PDT 24
Peak memory 201220 kb
Host smart-b8bb69fe-e874-4c0f-a7fc-fdb769a762d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175746803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
175746803
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4088503784
Short name T306
Test name
Test status
Simulation time 249504236140 ps
CPU time 258.91 seconds
Started Jul 27 06:40:36 PM PDT 24
Finished Jul 27 06:44:55 PM PDT 24
Peak memory 217576 kb
Host smart-fc356a2f-02f1-482c-8636-276d75fe3710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088503784 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4088503784
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1670540702
Short name T694
Test name
Test status
Simulation time 342522665 ps
CPU time 0.99 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:35:40 PM PDT 24
Peak memory 201028 kb
Host smart-7b9e4c5c-c372-4625-8ced-29dda17a6d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670540702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1670540702
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2091179021
Short name T760
Test name
Test status
Simulation time 485344447039 ps
CPU time 244.46 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:39:37 PM PDT 24
Peak memory 201316 kb
Host smart-3dff671d-86f1-4bc6-b2b2-0107d04707c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091179021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2091179021
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3844801723
Short name T628
Test name
Test status
Simulation time 494092396489 ps
CPU time 325.77 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:41:04 PM PDT 24
Peak memory 201228 kb
Host smart-b8ce9559-c22c-41d9-bf87-137e93399b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844801723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3844801723
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4194710746
Short name T605
Test name
Test status
Simulation time 163198272511 ps
CPU time 199.42 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:38:52 PM PDT 24
Peak memory 201232 kb
Host smart-d2309b8a-8c7e-4adf-bc01-095478f5b88a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194710746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4194710746
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1155123539
Short name T313
Test name
Test status
Simulation time 328111291838 ps
CPU time 197.15 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:38:51 PM PDT 24
Peak memory 201152 kb
Host smart-e8299ae0-fe5d-4abc-ba53-a03dca9c8fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155123539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1155123539
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1358922251
Short name T456
Test name
Test status
Simulation time 494110647627 ps
CPU time 586.22 seconds
Started Jul 27 06:35:32 PM PDT 24
Finished Jul 27 06:45:18 PM PDT 24
Peak memory 201232 kb
Host smart-cbb5174d-a3d4-4dca-9093-7af0489a1684
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358922251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1358922251
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3176701027
Short name T197
Test name
Test status
Simulation time 348577882014 ps
CPU time 345.94 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:41:21 PM PDT 24
Peak memory 201164 kb
Host smart-9b0f3d68-7073-407e-a319-e9f4efa54724
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176701027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3176701027
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4041570686
Short name T686
Test name
Test status
Simulation time 210865773977 ps
CPU time 66.35 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:36:51 PM PDT 24
Peak memory 201220 kb
Host smart-4c1afbb3-3e8a-4c4b-80fa-e49a282084af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041570686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4041570686
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2471034702
Short name T339
Test name
Test status
Simulation time 78729363745 ps
CPU time 285.8 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:40:23 PM PDT 24
Peak memory 201552 kb
Host smart-cf4e3dcb-8336-468e-b2dc-8b64fdbbdc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471034702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2471034702
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.118865709
Short name T757
Test name
Test status
Simulation time 38946828507 ps
CPU time 6.85 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:35:44 PM PDT 24
Peak memory 200972 kb
Host smart-a3f9781d-e653-482d-a3fd-36d9f95c1ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118865709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.118865709
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1522526791
Short name T621
Test name
Test status
Simulation time 4184270229 ps
CPU time 5.5 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:35:44 PM PDT 24
Peak memory 201136 kb
Host smart-fadfde87-4bce-4b30-80d7-3f70839559f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522526791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1522526791
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2367122272
Short name T66
Test name
Test status
Simulation time 8604287253 ps
CPU time 21.82 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:35:58 PM PDT 24
Peak memory 218028 kb
Host smart-2e5f4e54-5653-46d9-95ab-d92eb18a3464
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367122272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2367122272
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2549278882
Short name T723
Test name
Test status
Simulation time 6126554837 ps
CPU time 14.18 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:35:50 PM PDT 24
Peak memory 201060 kb
Host smart-0de39aa2-ce1f-4f0a-b504-e6e513c32bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549278882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2549278882
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3860944127
Short name T507
Test name
Test status
Simulation time 13157342970 ps
CPU time 53.87 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:36:31 PM PDT 24
Peak memory 210028 kb
Host smart-9dbe64ce-9aed-484a-8775-61cfb089129f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860944127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3860944127
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3464316043
Short name T654
Test name
Test status
Simulation time 327599664 ps
CPU time 0.8 seconds
Started Jul 27 06:40:52 PM PDT 24
Finished Jul 27 06:40:53 PM PDT 24
Peak memory 201052 kb
Host smart-d5bcbe77-b91e-4342-bd7d-2524a7581f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464316043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3464316043
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3269820650
Short name T166
Test name
Test status
Simulation time 495596002055 ps
CPU time 1023.73 seconds
Started Jul 27 06:40:41 PM PDT 24
Finished Jul 27 06:57:45 PM PDT 24
Peak memory 201180 kb
Host smart-795c8727-4a48-4182-9158-bd8bc3aee623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269820650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3269820650
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.848196061
Short name T786
Test name
Test status
Simulation time 497358892277 ps
CPU time 286.98 seconds
Started Jul 27 06:40:44 PM PDT 24
Finished Jul 27 06:45:31 PM PDT 24
Peak memory 201204 kb
Host smart-42f05980-cffc-44ea-9a48-10a41b522f27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848196061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.848196061
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3754701591
Short name T504
Test name
Test status
Simulation time 327811538632 ps
CPU time 65.49 seconds
Started Jul 27 06:40:41 PM PDT 24
Finished Jul 27 06:41:47 PM PDT 24
Peak memory 201288 kb
Host smart-aa919e38-b3ab-44ab-aa49-5c07ed82c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754701591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3754701591
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1140099336
Short name T543
Test name
Test status
Simulation time 491732145247 ps
CPU time 1125.19 seconds
Started Jul 27 06:40:43 PM PDT 24
Finished Jul 27 06:59:29 PM PDT 24
Peak memory 201232 kb
Host smart-fda2c90a-72e0-4129-93fb-47c5310989c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140099336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1140099336
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2008251743
Short name T715
Test name
Test status
Simulation time 382535182212 ps
CPU time 231.82 seconds
Started Jul 27 06:40:43 PM PDT 24
Finished Jul 27 06:44:35 PM PDT 24
Peak memory 201212 kb
Host smart-99656f46-b8ea-4bc4-bd45-6bb6c57f5f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008251743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2008251743
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4045472718
Short name T532
Test name
Test status
Simulation time 85846718325 ps
CPU time 321.67 seconds
Started Jul 27 06:40:42 PM PDT 24
Finished Jul 27 06:46:04 PM PDT 24
Peak memory 201632 kb
Host smart-91c18c19-b591-4f4d-876f-aac4609ccfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045472718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4045472718
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.669591179
Short name T29
Test name
Test status
Simulation time 44688099262 ps
CPU time 111.78 seconds
Started Jul 27 06:40:41 PM PDT 24
Finished Jul 27 06:42:33 PM PDT 24
Peak memory 201036 kb
Host smart-0da614c0-1ed0-4f47-9377-1865ef0f32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669591179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.669591179
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1061201305
Short name T448
Test name
Test status
Simulation time 2768449818 ps
CPU time 2.23 seconds
Started Jul 27 06:40:42 PM PDT 24
Finished Jul 27 06:40:44 PM PDT 24
Peak memory 201148 kb
Host smart-5065c9bf-6fca-4e27-82bb-69996d0d4c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061201305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1061201305
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.407048422
Short name T781
Test name
Test status
Simulation time 6150398456 ps
CPU time 15.4 seconds
Started Jul 27 06:40:41 PM PDT 24
Finished Jul 27 06:40:56 PM PDT 24
Peak memory 201096 kb
Host smart-ded4178f-ca26-4e2b-8455-00ff31cb0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407048422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.407048422
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1457726234
Short name T270
Test name
Test status
Simulation time 334637824699 ps
CPU time 215.27 seconds
Started Jul 27 06:40:57 PM PDT 24
Finished Jul 27 06:44:32 PM PDT 24
Peak memory 201228 kb
Host smart-7ff4ebc4-f4ea-4e18-a302-0e6c4d15eb72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457726234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1457726234
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2973503401
Short name T24
Test name
Test status
Simulation time 259267413860 ps
CPU time 409.83 seconds
Started Jul 27 06:40:50 PM PDT 24
Finished Jul 27 06:47:40 PM PDT 24
Peak memory 210192 kb
Host smart-337fd196-860b-4628-93ce-bf1bbdd5cc29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973503401 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2973503401
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3419608354
Short name T74
Test name
Test status
Simulation time 395874800 ps
CPU time 0.81 seconds
Started Jul 27 06:41:00 PM PDT 24
Finished Jul 27 06:41:00 PM PDT 24
Peak memory 200964 kb
Host smart-c3d8aa90-7d25-4112-8102-22fb5fe8bcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419608354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3419608354
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2148828536
Short name T529
Test name
Test status
Simulation time 207650658213 ps
CPU time 221.83 seconds
Started Jul 27 06:40:50 PM PDT 24
Finished Jul 27 06:44:32 PM PDT 24
Peak memory 201248 kb
Host smart-169dcd81-3873-4601-a00a-bf7c9775f1f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148828536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2148828536
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1890492013
Short name T319
Test name
Test status
Simulation time 495795384174 ps
CPU time 1037.82 seconds
Started Jul 27 06:40:58 PM PDT 24
Finished Jul 27 06:58:16 PM PDT 24
Peak memory 201500 kb
Host smart-f343f98f-0f7e-42e6-b446-815d6a86420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890492013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1890492013
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4106182589
Short name T302
Test name
Test status
Simulation time 326438629388 ps
CPU time 350.98 seconds
Started Jul 27 06:40:55 PM PDT 24
Finished Jul 27 06:46:46 PM PDT 24
Peak memory 201296 kb
Host smart-14ccf3b3-769d-4911-a892-932828eada2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106182589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4106182589
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3628289418
Short name T770
Test name
Test status
Simulation time 322714020898 ps
CPU time 184.42 seconds
Started Jul 27 06:40:51 PM PDT 24
Finished Jul 27 06:43:56 PM PDT 24
Peak memory 201316 kb
Host smart-24611f34-59af-4c4f-8e2b-efb066e3b62a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628289418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3628289418
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2658016631
Short name T211
Test name
Test status
Simulation time 484309050933 ps
CPU time 289.87 seconds
Started Jul 27 06:40:49 PM PDT 24
Finished Jul 27 06:45:39 PM PDT 24
Peak memory 201204 kb
Host smart-3d60f453-6a38-4e99-bb0e-e166d4a4516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658016631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2658016631
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.92625640
Short name T707
Test name
Test status
Simulation time 323953507454 ps
CPU time 268.36 seconds
Started Jul 27 06:40:57 PM PDT 24
Finished Jul 27 06:45:25 PM PDT 24
Peak memory 201212 kb
Host smart-05353821-cf6f-4ecf-be01-1b46f417a32e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=92625640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed
.92625640
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1829001437
Short name T315
Test name
Test status
Simulation time 168258360381 ps
CPU time 125.42 seconds
Started Jul 27 06:40:50 PM PDT 24
Finished Jul 27 06:42:56 PM PDT 24
Peak memory 201208 kb
Host smart-65c0e2f3-5936-4c14-bafb-d93d13047f13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829001437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1829001437
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1200050694
Short name T87
Test name
Test status
Simulation time 198075030556 ps
CPU time 404.71 seconds
Started Jul 27 06:40:49 PM PDT 24
Finished Jul 27 06:47:34 PM PDT 24
Peak memory 201216 kb
Host smart-ba705c31-871f-4c1a-bcb2-b30eb4def4ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200050694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1200050694
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3347639989
Short name T389
Test name
Test status
Simulation time 95971968449 ps
CPU time 356.91 seconds
Started Jul 27 06:40:58 PM PDT 24
Finished Jul 27 06:46:55 PM PDT 24
Peak memory 201676 kb
Host smart-3030b4b5-0585-4817-9226-94aabc2c05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347639989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3347639989
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.4101504397
Short name T391
Test name
Test status
Simulation time 37870567955 ps
CPU time 84.69 seconds
Started Jul 27 06:40:59 PM PDT 24
Finished Jul 27 06:42:24 PM PDT 24
Peak memory 201032 kb
Host smart-b5551a11-872e-4d3f-9c70-8ddc07580418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101504397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.4101504397
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1631855298
Short name T434
Test name
Test status
Simulation time 5477521774 ps
CPU time 12.35 seconds
Started Jul 27 06:40:59 PM PDT 24
Finished Jul 27 06:41:11 PM PDT 24
Peak memory 201076 kb
Host smart-50a82f70-08b8-4775-a9e7-7ba1c5062408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631855298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1631855298
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1608530483
Short name T415
Test name
Test status
Simulation time 5983503239 ps
CPU time 14.02 seconds
Started Jul 27 06:40:57 PM PDT 24
Finished Jul 27 06:41:11 PM PDT 24
Peak memory 201104 kb
Host smart-79c2ce89-2634-4c8d-9c8f-2de20af3a467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608530483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1608530483
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3443413845
Short name T25
Test name
Test status
Simulation time 81749568637 ps
CPU time 146.66 seconds
Started Jul 27 06:40:59 PM PDT 24
Finished Jul 27 06:43:26 PM PDT 24
Peak memory 209552 kb
Host smart-7ed3c7e2-222f-494f-96bd-6dc8895164b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443413845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3443413845
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1360112309
Short name T675
Test name
Test status
Simulation time 375813722 ps
CPU time 0.84 seconds
Started Jul 27 06:41:19 PM PDT 24
Finished Jul 27 06:41:20 PM PDT 24
Peak memory 200976 kb
Host smart-1f430ca9-790c-40ec-8754-42caade2fc31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360112309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1360112309
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.4192489506
Short name T226
Test name
Test status
Simulation time 551980505089 ps
CPU time 71.36 seconds
Started Jul 27 06:41:06 PM PDT 24
Finished Jul 27 06:42:18 PM PDT 24
Peak memory 201168 kb
Host smart-d625c598-3ece-40dc-ba12-eb1d40d1bd3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192489506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.4192489506
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.343406160
Short name T144
Test name
Test status
Simulation time 176485940251 ps
CPU time 198.88 seconds
Started Jul 27 06:41:07 PM PDT 24
Finished Jul 27 06:44:26 PM PDT 24
Peak memory 201228 kb
Host smart-f814c1e1-4798-4e96-acbd-508b8a931c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343406160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.343406160
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1062168523
Short name T671
Test name
Test status
Simulation time 161401586592 ps
CPU time 179.44 seconds
Started Jul 27 06:40:59 PM PDT 24
Finished Jul 27 06:43:59 PM PDT 24
Peak memory 201240 kb
Host smart-e5152de1-e6fa-4dfb-8df3-d428053b20c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062168523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1062168523
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3666626660
Short name T692
Test name
Test status
Simulation time 495145430965 ps
CPU time 325.4 seconds
Started Jul 27 06:41:13 PM PDT 24
Finished Jul 27 06:46:38 PM PDT 24
Peak memory 201216 kb
Host smart-1dafb4cd-d4e7-4d03-b9db-77cbc8b7af25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666626660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3666626660
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2260867410
Short name T540
Test name
Test status
Simulation time 164489220342 ps
CPU time 101.07 seconds
Started Jul 27 06:41:00 PM PDT 24
Finished Jul 27 06:42:41 PM PDT 24
Peak memory 201192 kb
Host smart-50607f0f-cfc5-4a61-8253-3b7f532af4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260867410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2260867410
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1604483403
Short name T582
Test name
Test status
Simulation time 489894013702 ps
CPU time 586.72 seconds
Started Jul 27 06:41:00 PM PDT 24
Finished Jul 27 06:50:47 PM PDT 24
Peak memory 201204 kb
Host smart-fd36ee35-da03-47bd-98c0-857889adae67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604483403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1604483403
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1047205954
Short name T273
Test name
Test status
Simulation time 575518824296 ps
CPU time 335.01 seconds
Started Jul 27 06:41:06 PM PDT 24
Finished Jul 27 06:46:42 PM PDT 24
Peak memory 201252 kb
Host smart-928132cc-7324-422f-9234-fc83000d0f23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047205954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1047205954
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2251019566
Short name T365
Test name
Test status
Simulation time 203422386711 ps
CPU time 458.15 seconds
Started Jul 27 06:41:12 PM PDT 24
Finished Jul 27 06:48:51 PM PDT 24
Peak memory 201236 kb
Host smart-67962c89-4d9b-4882-b5d5-4036e4e12475
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251019566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2251019566
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3065396836
Short name T744
Test name
Test status
Simulation time 126021933374 ps
CPU time 443.33 seconds
Started Jul 27 06:41:07 PM PDT 24
Finished Jul 27 06:48:31 PM PDT 24
Peak memory 201620 kb
Host smart-4da8b1de-5499-4aa6-ae5b-5a40953f96e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065396836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3065396836
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1014769500
Short name T512
Test name
Test status
Simulation time 31663840874 ps
CPU time 5.07 seconds
Started Jul 27 06:41:12 PM PDT 24
Finished Jul 27 06:41:17 PM PDT 24
Peak memory 201080 kb
Host smart-ed8d8570-3b31-4d8a-8d3c-26287eaa377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014769500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1014769500
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3393923199
Short name T411
Test name
Test status
Simulation time 3354257636 ps
CPU time 4.48 seconds
Started Jul 27 06:41:07 PM PDT 24
Finished Jul 27 06:41:11 PM PDT 24
Peak memory 201016 kb
Host smart-36233f1c-5b23-4888-8651-d7ecf7063654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393923199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3393923199
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2005904550
Short name T160
Test name
Test status
Simulation time 5656908354 ps
CPU time 7.97 seconds
Started Jul 27 06:41:06 PM PDT 24
Finished Jul 27 06:41:15 PM PDT 24
Peak memory 201104 kb
Host smart-31ffb03c-52ea-4fcc-a09a-3552b1f8b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005904550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2005904550
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2614123534
Short name T785
Test name
Test status
Simulation time 213972700427 ps
CPU time 124.08 seconds
Started Jul 27 06:41:19 PM PDT 24
Finished Jul 27 06:43:23 PM PDT 24
Peak memory 201292 kb
Host smart-bec72ed9-e2b1-421b-a359-bf8d8c45837c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614123534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2614123534
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1509338952
Short name T43
Test name
Test status
Simulation time 12906654608 ps
CPU time 34.08 seconds
Started Jul 27 06:41:14 PM PDT 24
Finished Jul 27 06:41:48 PM PDT 24
Peak memory 201796 kb
Host smart-1b38379e-f8b3-44fa-a580-ee075beda636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509338952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1509338952
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3259836154
Short name T575
Test name
Test status
Simulation time 375258295 ps
CPU time 1.42 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:41:31 PM PDT 24
Peak memory 201012 kb
Host smart-ee851c12-9101-4566-a75f-68c89568eefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259836154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3259836154
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.680456556
Short name T701
Test name
Test status
Simulation time 359719960764 ps
CPU time 392.75 seconds
Started Jul 27 06:41:18 PM PDT 24
Finished Jul 27 06:47:51 PM PDT 24
Peak memory 201252 kb
Host smart-f348cf0a-de04-4465-9473-3b81927e0738
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680456556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.680456556
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3890642776
Short name T266
Test name
Test status
Simulation time 366936574191 ps
CPU time 61.72 seconds
Started Jul 27 06:41:17 PM PDT 24
Finished Jul 27 06:42:19 PM PDT 24
Peak memory 201272 kb
Host smart-903de1d0-7665-426d-bab6-19b22852d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890642776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3890642776
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.848409416
Short name T248
Test name
Test status
Simulation time 490186219415 ps
CPU time 608.06 seconds
Started Jul 27 06:41:18 PM PDT 24
Finished Jul 27 06:51:26 PM PDT 24
Peak memory 201196 kb
Host smart-bc32ff15-576e-45c2-bfcc-f134e4f123d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848409416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.848409416
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.433278944
Short name T171
Test name
Test status
Simulation time 325075665145 ps
CPU time 748.45 seconds
Started Jul 27 06:41:18 PM PDT 24
Finished Jul 27 06:53:47 PM PDT 24
Peak memory 201224 kb
Host smart-26a374a3-e7a6-4f2c-937c-61f027f112cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433278944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.433278944
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3882398261
Short name T414
Test name
Test status
Simulation time 166525406519 ps
CPU time 382 seconds
Started Jul 27 06:41:23 PM PDT 24
Finished Jul 27 06:47:45 PM PDT 24
Peak memory 201212 kb
Host smart-9bdb2736-8757-4275-8269-6586826cf7f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882398261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3882398261
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2382287770
Short name T508
Test name
Test status
Simulation time 228968207874 ps
CPU time 129.01 seconds
Started Jul 27 06:41:23 PM PDT 24
Finished Jul 27 06:43:32 PM PDT 24
Peak memory 201228 kb
Host smart-1bc5bb9a-da61-4503-b89a-09723d311718
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382287770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2382287770
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2044565380
Short name T536
Test name
Test status
Simulation time 192894208115 ps
CPU time 458.93 seconds
Started Jul 27 06:41:18 PM PDT 24
Finished Jul 27 06:48:57 PM PDT 24
Peak memory 201216 kb
Host smart-9a4b48a8-01d3-4edf-a758-f50ca4dcbc37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044565380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2044565380
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1352352243
Short name T350
Test name
Test status
Simulation time 115098308858 ps
CPU time 363.43 seconds
Started Jul 27 06:41:28 PM PDT 24
Finished Jul 27 06:47:32 PM PDT 24
Peak memory 201644 kb
Host smart-ea67fd9a-177b-4b87-9870-88adcc7be099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352352243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1352352243
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.995762142
Short name T361
Test name
Test status
Simulation time 30471742328 ps
CPU time 37.51 seconds
Started Jul 27 06:41:21 PM PDT 24
Finished Jul 27 06:41:59 PM PDT 24
Peak memory 201144 kb
Host smart-58683f53-4e06-45f2-8af0-c165b2697363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995762142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.995762142
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.873946170
Short name T103
Test name
Test status
Simulation time 4195227245 ps
CPU time 3.17 seconds
Started Jul 27 06:41:19 PM PDT 24
Finished Jul 27 06:41:22 PM PDT 24
Peak memory 201020 kb
Host smart-ffd95d2b-21ea-4e4f-a6a8-2e4d33d89493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873946170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.873946170
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2637224648
Short name T376
Test name
Test status
Simulation time 5578014624 ps
CPU time 7.8 seconds
Started Jul 27 06:41:19 PM PDT 24
Finished Jul 27 06:41:27 PM PDT 24
Peak memory 201096 kb
Host smart-4215db84-947b-4a20-9292-a32c5af5b0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637224648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2637224648
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1454963211
Short name T281
Test name
Test status
Simulation time 169552048178 ps
CPU time 271.6 seconds
Started Jul 27 06:41:28 PM PDT 24
Finished Jul 27 06:46:00 PM PDT 24
Peak memory 201220 kb
Host smart-a914f786-bddc-473e-b750-b27ade921c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454963211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1454963211
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1397078211
Short name T769
Test name
Test status
Simulation time 215761447523 ps
CPU time 194.27 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:44:45 PM PDT 24
Peak memory 210028 kb
Host smart-a2075c73-6ee2-4088-bf7e-df97434fe251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397078211 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1397078211
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2349653888
Short name T521
Test name
Test status
Simulation time 411870962 ps
CPU time 1.47 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:41:39 PM PDT 24
Peak memory 201016 kb
Host smart-545bb6d0-9dfa-4e2f-83ad-c13394de6eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349653888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2349653888
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.202640776
Short name T323
Test name
Test status
Simulation time 387306436188 ps
CPU time 440.32 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:48:59 PM PDT 24
Peak memory 201176 kb
Host smart-2752ff27-300b-4305-9c29-adddb005a177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202640776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.202640776
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.384476961
Short name T423
Test name
Test status
Simulation time 168865729794 ps
CPU time 406.01 seconds
Started Jul 27 06:41:29 PM PDT 24
Finished Jul 27 06:48:15 PM PDT 24
Peak memory 201216 kb
Host smart-d4c26167-eec6-40ec-b744-125b5c738cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384476961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.384476961
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.73287844
Short name T779
Test name
Test status
Simulation time 330843702845 ps
CPU time 831.02 seconds
Started Jul 27 06:41:28 PM PDT 24
Finished Jul 27 06:55:19 PM PDT 24
Peak memory 201316 kb
Host smart-94ec6c2b-5161-4ed7-a8dc-815169baaf43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=73287844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt
_fixed.73287844
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.327827686
Short name T195
Test name
Test status
Simulation time 326456875884 ps
CPU time 111.37 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:43:22 PM PDT 24
Peak memory 201212 kb
Host smart-92caeb19-bc53-4acb-946a-b3560e9e2d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327827686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.327827686
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.605658251
Short name T425
Test name
Test status
Simulation time 326228350356 ps
CPU time 166.29 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:44:16 PM PDT 24
Peak memory 201212 kb
Host smart-ba60556e-6f06-4deb-b8fe-a4f8033dfe15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=605658251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.605658251
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3149262510
Short name T768
Test name
Test status
Simulation time 171172403111 ps
CPU time 104.3 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:43:15 PM PDT 24
Peak memory 201232 kb
Host smart-c2612e52-df01-4559-b280-429f2b791aef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149262510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3149262510
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1956951133
Short name T404
Test name
Test status
Simulation time 611929354459 ps
CPU time 763.73 seconds
Started Jul 27 06:41:29 PM PDT 24
Finished Jul 27 06:54:13 PM PDT 24
Peak memory 201148 kb
Host smart-eda24081-9fc0-404c-96af-33f17aa7a9bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956951133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1956951133
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.422662971
Short name T1
Test name
Test status
Simulation time 138848966596 ps
CPU time 495.96 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:49:54 PM PDT 24
Peak memory 201736 kb
Host smart-44000a06-0aae-42dd-80be-a3a8344ff78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422662971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.422662971
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.416469341
Short name T416
Test name
Test status
Simulation time 31693629626 ps
CPU time 33.64 seconds
Started Jul 27 06:41:40 PM PDT 24
Finished Jul 27 06:42:14 PM PDT 24
Peak memory 201000 kb
Host smart-9fd73f95-fa26-4c4d-9643-faa91cf60ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416469341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.416469341
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3574773493
Short name T539
Test name
Test status
Simulation time 3485977673 ps
CPU time 7.75 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:41:45 PM PDT 24
Peak memory 201056 kb
Host smart-cdbc7420-67c1-4d23-b02e-9116cfdc86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574773493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3574773493
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1734011207
Short name T435
Test name
Test status
Simulation time 5774655998 ps
CPU time 7.29 seconds
Started Jul 27 06:41:30 PM PDT 24
Finished Jul 27 06:41:37 PM PDT 24
Peak memory 201148 kb
Host smart-37c31d2a-042b-437e-a4f1-bcd8dfdf1704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734011207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1734011207
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2020208099
Short name T21
Test name
Test status
Simulation time 42062222234 ps
CPU time 24.3 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:42:02 PM PDT 24
Peak memory 201388 kb
Host smart-923f54dd-3f17-4c39-9ecf-1f7037573439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020208099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2020208099
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4149853033
Short name T653
Test name
Test status
Simulation time 359151400 ps
CPU time 1.47 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:41:47 PM PDT 24
Peak memory 201036 kb
Host smart-908947ee-bccb-41d4-a3fa-6869fce766ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149853033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4149853033
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2473327922
Short name T162
Test name
Test status
Simulation time 163183960115 ps
CPU time 23.69 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:42:09 PM PDT 24
Peak memory 201180 kb
Host smart-4567eaa5-e740-47c6-a0b6-fdb66e8b577b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473327922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2473327922
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3768654914
Short name T233
Test name
Test status
Simulation time 173541007175 ps
CPU time 98.22 seconds
Started Jul 27 06:41:48 PM PDT 24
Finished Jul 27 06:43:26 PM PDT 24
Peak memory 201304 kb
Host smart-dd40dd23-2c1a-4f23-8b61-66a97b104fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768654914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3768654914
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2202171069
Short name T14
Test name
Test status
Simulation time 493270567957 ps
CPU time 296.94 seconds
Started Jul 27 06:41:37 PM PDT 24
Finished Jul 27 06:46:34 PM PDT 24
Peak memory 201288 kb
Host smart-ffc6f77d-4a61-4a1d-8b7c-685487557d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202171069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2202171069
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3648302095
Short name T718
Test name
Test status
Simulation time 325401075096 ps
CPU time 369.95 seconds
Started Jul 27 06:41:37 PM PDT 24
Finished Jul 27 06:47:47 PM PDT 24
Peak memory 201172 kb
Host smart-789b954a-045e-44d1-bbb6-1490e44bc9c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648302095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3648302095
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1598956896
Short name T318
Test name
Test status
Simulation time 165203800897 ps
CPU time 127.36 seconds
Started Jul 27 06:41:40 PM PDT 24
Finished Jul 27 06:43:48 PM PDT 24
Peak memory 201140 kb
Host smart-25c9e6a1-3c53-4a67-bc78-a59facdcc641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598956896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1598956896
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2049665408
Short name T754
Test name
Test status
Simulation time 493177417101 ps
CPU time 1066.69 seconds
Started Jul 27 06:41:40 PM PDT 24
Finished Jul 27 06:59:27 PM PDT 24
Peak memory 201244 kb
Host smart-5efecb8f-e446-440c-875f-65ed433ff1fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049665408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2049665408
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2133768377
Short name T324
Test name
Test status
Simulation time 196327929969 ps
CPU time 104.81 seconds
Started Jul 27 06:41:38 PM PDT 24
Finished Jul 27 06:43:23 PM PDT 24
Peak memory 201252 kb
Host smart-0109c08a-3d7f-4a30-b7f9-f4918d9d4937
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133768377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2133768377
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1901801977
Short name T636
Test name
Test status
Simulation time 201753779289 ps
CPU time 450.13 seconds
Started Jul 27 06:41:48 PM PDT 24
Finished Jul 27 06:49:18 PM PDT 24
Peak memory 201280 kb
Host smart-cd8d567e-18d0-4798-96a0-736b5be54a21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901801977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1901801977
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.561882774
Short name T344
Test name
Test status
Simulation time 95184456866 ps
CPU time 339.07 seconds
Started Jul 27 06:41:47 PM PDT 24
Finished Jul 27 06:47:26 PM PDT 24
Peak memory 201688 kb
Host smart-73c27778-df4f-4ea2-b907-411868ac4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561882774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.561882774
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.427147740
Short name T689
Test name
Test status
Simulation time 30846436557 ps
CPU time 17.36 seconds
Started Jul 27 06:41:48 PM PDT 24
Finished Jul 27 06:42:06 PM PDT 24
Peak memory 201068 kb
Host smart-aa342f4e-d592-4d59-a8df-b398cde9cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427147740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.427147740
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2670471706
Short name T635
Test name
Test status
Simulation time 2902864607 ps
CPU time 8.51 seconds
Started Jul 27 06:41:47 PM PDT 24
Finished Jul 27 06:41:55 PM PDT 24
Peak memory 201020 kb
Host smart-b3665eb7-71cb-40b1-aca2-347f3d4f4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670471706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2670471706
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.275153515
Short name T192
Test name
Test status
Simulation time 6240428387 ps
CPU time 4.51 seconds
Started Jul 27 06:41:37 PM PDT 24
Finished Jul 27 06:41:42 PM PDT 24
Peak memory 201100 kb
Host smart-f4dca93c-fffe-45ac-8f47-806581c98fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275153515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.275153515
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3185753374
Short name T276
Test name
Test status
Simulation time 81780424461 ps
CPU time 176.25 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:44:43 PM PDT 24
Peak memory 209684 kb
Host smart-1a97a528-0915-4f8f-8d88-b7f32602e401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185753374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3185753374
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.756414394
Short name T427
Test name
Test status
Simulation time 368628204 ps
CPU time 1.03 seconds
Started Jul 27 06:41:55 PM PDT 24
Finished Jul 27 06:41:56 PM PDT 24
Peak memory 200952 kb
Host smart-53bcdadf-1718-4a2c-9395-fd3c88734dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756414394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.756414394
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2386127411
Short name T682
Test name
Test status
Simulation time 548927017100 ps
CPU time 282.11 seconds
Started Jul 27 06:41:55 PM PDT 24
Finished Jul 27 06:46:38 PM PDT 24
Peak memory 201200 kb
Host smart-409b14d5-5e87-4532-a7f1-16c7f71f9f83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386127411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2386127411
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2478879300
Short name T274
Test name
Test status
Simulation time 555960735816 ps
CPU time 323.97 seconds
Started Jul 27 06:41:56 PM PDT 24
Finished Jul 27 06:47:21 PM PDT 24
Peak memory 201232 kb
Host smart-835ff80e-5424-4f38-b669-5b24db004588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478879300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2478879300
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.221778951
Short name T249
Test name
Test status
Simulation time 328130509554 ps
CPU time 379.2 seconds
Started Jul 27 06:41:47 PM PDT 24
Finished Jul 27 06:48:06 PM PDT 24
Peak memory 201240 kb
Host smart-6dabc6e9-3070-46ef-8ded-58bd53a9e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221778951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.221778951
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2302300223
Short name T485
Test name
Test status
Simulation time 331566702758 ps
CPU time 324.15 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:47:11 PM PDT 24
Peak memory 201180 kb
Host smart-e2ecacc2-ae10-4db4-9e4f-591c6e99a222
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302300223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2302300223
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1453946618
Short name T714
Test name
Test status
Simulation time 160531583827 ps
CPU time 91.33 seconds
Started Jul 27 06:41:45 PM PDT 24
Finished Jul 27 06:43:17 PM PDT 24
Peak memory 201188 kb
Host smart-cedbb844-2354-44fd-b397-625c9791ef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453946618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1453946618
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3556008652
Short name T187
Test name
Test status
Simulation time 325193534349 ps
CPU time 373.98 seconds
Started Jul 27 06:41:44 PM PDT 24
Finished Jul 27 06:47:58 PM PDT 24
Peak memory 201220 kb
Host smart-2a7852f0-ddd4-470c-ae01-f9fe929444f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556008652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3556008652
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1554121790
Short name T290
Test name
Test status
Simulation time 352557416786 ps
CPU time 799.97 seconds
Started Jul 27 06:41:45 PM PDT 24
Finished Jul 27 06:55:06 PM PDT 24
Peak memory 201200 kb
Host smart-0e3b0ea9-1186-43fd-a97d-dce34969409c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554121790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1554121790
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3782060596
Short name T522
Test name
Test status
Simulation time 401389582627 ps
CPU time 490.89 seconds
Started Jul 27 06:41:56 PM PDT 24
Finished Jul 27 06:50:07 PM PDT 24
Peak memory 201196 kb
Host smart-b7e585f4-d02f-4527-924d-ffa7de2278fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782060596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3782060596
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1110657790
Short name T730
Test name
Test status
Simulation time 88991672660 ps
CPU time 361.92 seconds
Started Jul 27 06:41:58 PM PDT 24
Finished Jul 27 06:48:00 PM PDT 24
Peak memory 201680 kb
Host smart-f83edeb6-43f6-43f2-b8c7-c4f4804fa167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110657790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1110657790
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2726960989
Short name T429
Test name
Test status
Simulation time 26734305779 ps
CPU time 57.76 seconds
Started Jul 27 06:41:57 PM PDT 24
Finished Jul 27 06:42:55 PM PDT 24
Peak memory 201036 kb
Host smart-771a605f-aa78-42ce-a8c6-7ec36d71ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726960989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2726960989
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3495748803
Short name T794
Test name
Test status
Simulation time 4304809587 ps
CPU time 3.06 seconds
Started Jul 27 06:41:54 PM PDT 24
Finished Jul 27 06:41:57 PM PDT 24
Peak memory 200980 kb
Host smart-06946ace-7fd4-4cee-9c5c-4e61d17371d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495748803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3495748803
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3246276320
Short name T473
Test name
Test status
Simulation time 5897135678 ps
CPU time 11.12 seconds
Started Jul 27 06:41:46 PM PDT 24
Finished Jul 27 06:41:57 PM PDT 24
Peak memory 201288 kb
Host smart-b51ddeda-ddac-4938-aff9-4994c2f7daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246276320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3246276320
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3967411305
Short name T297
Test name
Test status
Simulation time 181101712573 ps
CPU time 212.89 seconds
Started Jul 27 06:41:55 PM PDT 24
Finished Jul 27 06:45:28 PM PDT 24
Peak memory 201236 kb
Host smart-a9ddf790-8ba0-4502-82e3-43d3bc76cd4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967411305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3967411305
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3339124497
Short name T739
Test name
Test status
Simulation time 268507982960 ps
CPU time 470.92 seconds
Started Jul 27 06:41:58 PM PDT 24
Finished Jul 27 06:49:49 PM PDT 24
Peak memory 209956 kb
Host smart-46f340b7-bacd-4947-a8ba-671ef978cd14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339124497 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3339124497
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2422271567
Short name T683
Test name
Test status
Simulation time 322901554 ps
CPU time 0.8 seconds
Started Jul 27 06:42:10 PM PDT 24
Finished Jul 27 06:42:11 PM PDT 24
Peak memory 200936 kb
Host smart-47ff69f2-f214-4682-b5d6-693ff3e36edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422271567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2422271567
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3387897375
Short name T615
Test name
Test status
Simulation time 171269751015 ps
CPU time 382.25 seconds
Started Jul 27 06:42:03 PM PDT 24
Finished Jul 27 06:48:25 PM PDT 24
Peak memory 201240 kb
Host smart-1b423b4d-79bb-4f3d-b62f-52704b6100c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387897375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3387897375
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1943736405
Short name T177
Test name
Test status
Simulation time 329603615465 ps
CPU time 191.44 seconds
Started Jul 27 06:42:05 PM PDT 24
Finished Jul 27 06:45:17 PM PDT 24
Peak memory 201296 kb
Host smart-ed8637cc-323e-4ba2-8563-178d3b065876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943736405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1943736405
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4057982527
Short name T325
Test name
Test status
Simulation time 167014361239 ps
CPU time 237.97 seconds
Started Jul 27 06:42:05 PM PDT 24
Finished Jul 27 06:46:04 PM PDT 24
Peak memory 201248 kb
Host smart-7bd8d027-ba79-4ffe-9db0-90e63ce5f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057982527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4057982527
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3748262425
Short name T699
Test name
Test status
Simulation time 163850337679 ps
CPU time 369.52 seconds
Started Jul 27 06:42:04 PM PDT 24
Finished Jul 27 06:48:13 PM PDT 24
Peak memory 201200 kb
Host smart-247f356c-e8bd-461f-a6c8-bdc47c4538e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748262425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3748262425
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2020390624
Short name T706
Test name
Test status
Simulation time 326551691363 ps
CPU time 193.57 seconds
Started Jul 27 06:42:03 PM PDT 24
Finished Jul 27 06:45:17 PM PDT 24
Peak memory 201280 kb
Host smart-815dd9eb-f855-4f63-b639-496c7e4532d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020390624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2020390624
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.713459151
Short name T185
Test name
Test status
Simulation time 486858276369 ps
CPU time 1051.76 seconds
Started Jul 27 06:42:06 PM PDT 24
Finished Jul 27 06:59:38 PM PDT 24
Peak memory 201220 kb
Host smart-2a8b638b-72e7-41f7-9c4f-e7a75287b14d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713459151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.713459151
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1762980476
Short name T716
Test name
Test status
Simulation time 534715221761 ps
CPU time 275.33 seconds
Started Jul 27 06:42:05 PM PDT 24
Finished Jul 27 06:46:40 PM PDT 24
Peak memory 201224 kb
Host smart-af5e622e-1c9e-48ef-9104-c25852dc2691
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762980476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1762980476
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2929226236
Short name T762
Test name
Test status
Simulation time 401216227825 ps
CPU time 939.66 seconds
Started Jul 27 06:42:04 PM PDT 24
Finished Jul 27 06:57:44 PM PDT 24
Peak memory 201236 kb
Host smart-9b68e6ab-0d60-43f6-ae2f-7be7848a834d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929226236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2929226236
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2662784802
Short name T639
Test name
Test status
Simulation time 122909746707 ps
CPU time 534.68 seconds
Started Jul 27 06:42:03 PM PDT 24
Finished Jul 27 06:50:58 PM PDT 24
Peak memory 201672 kb
Host smart-eebb0d87-440a-40dd-a55e-80eb79f7bef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662784802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2662784802
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2638596553
Short name T371
Test name
Test status
Simulation time 44814885510 ps
CPU time 7.46 seconds
Started Jul 27 06:42:04 PM PDT 24
Finished Jul 27 06:42:11 PM PDT 24
Peak memory 201000 kb
Host smart-5cafb141-c5d3-492d-8300-26f9524eac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638596553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2638596553
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.387844672
Short name T531
Test name
Test status
Simulation time 3651317449 ps
CPU time 4.5 seconds
Started Jul 27 06:42:05 PM PDT 24
Finished Jul 27 06:42:10 PM PDT 24
Peak memory 201080 kb
Host smart-dc9f0219-1a82-4fdb-97c2-2e0cbcd8c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387844672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.387844672
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2115264500
Short name T491
Test name
Test status
Simulation time 5892002471 ps
CPU time 2.81 seconds
Started Jul 27 06:41:55 PM PDT 24
Finished Jul 27 06:41:58 PM PDT 24
Peak memory 201120 kb
Host smart-f7d21c17-9f4d-4d1e-8895-68065bde3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115264500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2115264500
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1985132802
Short name T146
Test name
Test status
Simulation time 419777587286 ps
CPU time 470.77 seconds
Started Jul 27 06:42:11 PM PDT 24
Finished Jul 27 06:50:02 PM PDT 24
Peak memory 201748 kb
Host smart-b7335852-a8ae-47e8-856b-74838272ee36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985132802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1985132802
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1007879287
Short name T687
Test name
Test status
Simulation time 325763395 ps
CPU time 0.73 seconds
Started Jul 27 06:42:21 PM PDT 24
Finished Jul 27 06:42:22 PM PDT 24
Peak memory 201032 kb
Host smart-f2ce8fe5-7a32-4e16-b219-b8a56df12bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007879287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1007879287
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.649200575
Short name T651
Test name
Test status
Simulation time 331790324905 ps
CPU time 47.51 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:43:08 PM PDT 24
Peak memory 201208 kb
Host smart-c8611dd6-61cd-430e-80db-cb66f49f0009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649200575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.649200575
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.107624496
Short name T424
Test name
Test status
Simulation time 164911878590 ps
CPU time 31.49 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:42:52 PM PDT 24
Peak memory 201244 kb
Host smart-b0b3a8e2-b3aa-49f6-8ad7-3f28af14f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107624496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.107624496
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1664082622
Short name T407
Test name
Test status
Simulation time 329731389629 ps
CPU time 98.87 seconds
Started Jul 27 06:42:21 PM PDT 24
Finished Jul 27 06:44:00 PM PDT 24
Peak memory 201228 kb
Host smart-a294cf25-0eb6-404f-82f8-6c343d0dda34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664082622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1664082622
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3347895155
Short name T84
Test name
Test status
Simulation time 488616553098 ps
CPU time 1133.48 seconds
Started Jul 27 06:42:12 PM PDT 24
Finished Jul 27 07:01:06 PM PDT 24
Peak memory 201200 kb
Host smart-3f56765a-b358-43dd-9c8a-6ef995e4734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347895155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3347895155
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3772358523
Short name T552
Test name
Test status
Simulation time 163735088932 ps
CPU time 395.66 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:48:56 PM PDT 24
Peak memory 201220 kb
Host smart-77073c2c-3427-4ed3-b334-c43cf5226ffb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772358523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3772358523
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2074146115
Short name T602
Test name
Test status
Simulation time 197320722267 ps
CPU time 447.21 seconds
Started Jul 27 06:42:21 PM PDT 24
Finished Jul 27 06:49:48 PM PDT 24
Peak memory 201220 kb
Host smart-e15de269-53c5-46d1-8b65-4b49923a0db3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074146115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2074146115
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2349791578
Short name T551
Test name
Test status
Simulation time 599412325060 ps
CPU time 379.89 seconds
Started Jul 27 06:42:19 PM PDT 24
Finished Jul 27 06:48:40 PM PDT 24
Peak memory 201208 kb
Host smart-7f3ac688-57c0-4bbf-bbbd-99c074340afd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349791578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2349791578
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4241785476
Short name T345
Test name
Test status
Simulation time 104213319099 ps
CPU time 475.28 seconds
Started Jul 27 06:42:21 PM PDT 24
Finished Jul 27 06:50:16 PM PDT 24
Peak memory 201672 kb
Host smart-20b5e7b5-823f-429b-a13f-2cb18dbf9230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241785476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4241785476
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3447597992
Short name T580
Test name
Test status
Simulation time 29509347941 ps
CPU time 63.83 seconds
Started Jul 27 06:42:19 PM PDT 24
Finished Jul 27 06:43:23 PM PDT 24
Peak memory 201104 kb
Host smart-cb751cff-b0ed-4dd2-b713-a4807ddf00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447597992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3447597992
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.4173951862
Short name T394
Test name
Test status
Simulation time 4695556361 ps
CPU time 11.96 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:42:32 PM PDT 24
Peak memory 201056 kb
Host smart-264c6422-be08-47e1-8c5e-8538d58dbe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173951862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.4173951862
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.459039385
Short name T452
Test name
Test status
Simulation time 5663288588 ps
CPU time 12.85 seconds
Started Jul 27 06:42:11 PM PDT 24
Finished Jul 27 06:42:24 PM PDT 24
Peak memory 201076 kb
Host smart-f1400cb5-60ce-45e4-bb5f-73126dd21c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459039385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.459039385
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1998169031
Short name T169
Test name
Test status
Simulation time 345929052862 ps
CPU time 794.51 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:55:35 PM PDT 24
Peak memory 201240 kb
Host smart-3dd64ebb-15e5-4a94-bb80-98a934b9026a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998169031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1998169031
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1951942092
Short name T606
Test name
Test status
Simulation time 57261648012 ps
CPU time 68.93 seconds
Started Jul 27 06:42:20 PM PDT 24
Finished Jul 27 06:43:29 PM PDT 24
Peak memory 209576 kb
Host smart-6f99f359-8129-4e45-9376-8c7e51569812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951942092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1951942092
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.952599707
Short name T422
Test name
Test status
Simulation time 398626616 ps
CPU time 1.04 seconds
Started Jul 27 06:42:39 PM PDT 24
Finished Jul 27 06:42:40 PM PDT 24
Peak memory 200980 kb
Host smart-01cc4e63-7ba9-4d5f-bf86-0bd8de6af43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952599707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.952599707
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.325746278
Short name T330
Test name
Test status
Simulation time 506302327084 ps
CPU time 284.1 seconds
Started Jul 27 06:42:29 PM PDT 24
Finished Jul 27 06:47:13 PM PDT 24
Peak memory 201244 kb
Host smart-0904d8df-abf6-411c-a976-3d2806958e82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325746278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.325746278
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1671515701
Short name T285
Test name
Test status
Simulation time 537222762472 ps
CPU time 1368.75 seconds
Started Jul 27 06:42:33 PM PDT 24
Finished Jul 27 07:05:22 PM PDT 24
Peak memory 201188 kb
Host smart-931a8902-376e-4e10-a4a7-fd5ad875f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671515701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1671515701
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.818276248
Short name T145
Test name
Test status
Simulation time 162808489941 ps
CPU time 99.21 seconds
Started Jul 27 06:42:30 PM PDT 24
Finished Jul 27 06:44:09 PM PDT 24
Peak memory 201244 kb
Host smart-40c07b4f-273c-40a3-bb97-a4983ce10069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818276248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.818276248
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1697277731
Short name T758
Test name
Test status
Simulation time 162204997131 ps
CPU time 199.83 seconds
Started Jul 27 06:42:29 PM PDT 24
Finished Jul 27 06:45:49 PM PDT 24
Peak memory 201224 kb
Host smart-48271db0-023e-4ca8-9f36-f40a175104b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697277731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1697277731
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2669258364
Short name T641
Test name
Test status
Simulation time 333990518961 ps
CPU time 413.26 seconds
Started Jul 27 06:42:30 PM PDT 24
Finished Jul 27 06:49:23 PM PDT 24
Peak memory 201240 kb
Host smart-2aaa561c-6300-4a7b-b12f-f4fceb4e684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669258364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2669258364
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.40850372
Short name T505
Test name
Test status
Simulation time 489831230096 ps
CPU time 1076.35 seconds
Started Jul 27 06:42:28 PM PDT 24
Finished Jul 27 07:00:25 PM PDT 24
Peak memory 201176 kb
Host smart-786d22cd-a7d7-4b4e-bf64-6c30d61dc8a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed
.40850372
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4196565548
Short name T314
Test name
Test status
Simulation time 358633546463 ps
CPU time 387.73 seconds
Started Jul 27 06:42:33 PM PDT 24
Finished Jul 27 06:49:01 PM PDT 24
Peak memory 201148 kb
Host smart-78431b35-654c-4153-aea8-bff4f7cdd5d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196565548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4196565548
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.394959338
Short name T409
Test name
Test status
Simulation time 596664346246 ps
CPU time 354.07 seconds
Started Jul 27 06:42:29 PM PDT 24
Finished Jul 27 06:48:23 PM PDT 24
Peak memory 201196 kb
Host smart-547f0dbd-4010-4c40-8165-ed6d974b4d4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394959338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.394959338
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2712869187
Short name T645
Test name
Test status
Simulation time 110860899961 ps
CPU time 366.44 seconds
Started Jul 27 06:42:33 PM PDT 24
Finished Jul 27 06:48:40 PM PDT 24
Peak memory 201596 kb
Host smart-bd7af235-f32d-4067-a3dc-f8b0319a8c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712869187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2712869187
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2311692112
Short name T717
Test name
Test status
Simulation time 33093739707 ps
CPU time 19.04 seconds
Started Jul 27 06:42:29 PM PDT 24
Finished Jul 27 06:42:48 PM PDT 24
Peak memory 201020 kb
Host smart-c41ed313-2c47-4c43-baa3-92846cf953bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311692112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2311692112
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3238780790
Short name T674
Test name
Test status
Simulation time 3209746753 ps
CPU time 2.53 seconds
Started Jul 27 06:42:30 PM PDT 24
Finished Jul 27 06:42:33 PM PDT 24
Peak memory 201088 kb
Host smart-84a81d82-fa5f-4e0b-9754-ad682bdd5ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238780790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3238780790
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3040025555
Short name T747
Test name
Test status
Simulation time 5820944049 ps
CPU time 9.2 seconds
Started Jul 27 06:42:28 PM PDT 24
Finished Jul 27 06:42:38 PM PDT 24
Peak memory 201108 kb
Host smart-8468e4b7-acf2-4c92-83c2-c4cf0c4b3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040025555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3040025555
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.718698144
Short name T764
Test name
Test status
Simulation time 347579460843 ps
CPU time 126.42 seconds
Started Jul 27 06:42:33 PM PDT 24
Finished Jul 27 06:44:40 PM PDT 24
Peak memory 201248 kb
Host smart-a0f6e27e-668f-423b-8539-61c7eda6b2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718698144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
718698144
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2381303231
Short name T477
Test name
Test status
Simulation time 442926200 ps
CPU time 1.61 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:35:35 PM PDT 24
Peak memory 201212 kb
Host smart-25c7e70d-9ff0-497f-bee5-f6393c31fd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381303231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2381303231
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1398342140
Short name T295
Test name
Test status
Simulation time 161021167723 ps
CPU time 98.73 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:37:15 PM PDT 24
Peak memory 201208 kb
Host smart-75f93885-d3a9-46a8-b8c5-32334df7cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398342140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1398342140
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4007483530
Short name T388
Test name
Test status
Simulation time 486725207256 ps
CPU time 145.12 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:37:59 PM PDT 24
Peak memory 201136 kb
Host smart-d17019fb-477a-4416-b2ed-141b130e1229
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007483530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4007483530
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3955937092
Short name T724
Test name
Test status
Simulation time 168317637502 ps
CPU time 349.76 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:41:25 PM PDT 24
Peak memory 201240 kb
Host smart-3ecf8e94-ed51-4549-a32a-1e7afca2fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955937092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3955937092
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.849952280
Short name T30
Test name
Test status
Simulation time 496765379157 ps
CPU time 568.62 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:45:02 PM PDT 24
Peak memory 201220 kb
Host smart-df05356b-7a95-40b4-b41e-9f529be5d73a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=849952280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.849952280
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3404570640
Short name T133
Test name
Test status
Simulation time 207082442122 ps
CPU time 104.38 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:37:18 PM PDT 24
Peak memory 201140 kb
Host smart-60d886cc-588c-4f17-99a7-b8a8a355ca19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404570640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3404570640
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1726437754
Short name T608
Test name
Test status
Simulation time 603775318056 ps
CPU time 676.84 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:46:58 PM PDT 24
Peak memory 201192 kb
Host smart-96b4e317-d297-4570-a24d-85bf0cfa59cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726437754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1726437754
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1757234098
Short name T728
Test name
Test status
Simulation time 123855021963 ps
CPU time 655.71 seconds
Started Jul 27 06:35:31 PM PDT 24
Finished Jul 27 06:46:27 PM PDT 24
Peak memory 201624 kb
Host smart-364b7c46-58c4-4c79-9191-3b1d5be78556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757234098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1757234098
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2372266954
Short name T576
Test name
Test status
Simulation time 25596652070 ps
CPU time 30.31 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:36:05 PM PDT 24
Peak memory 200984 kb
Host smart-06355666-f9d6-4457-b3e0-8aee06650176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372266954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2372266954
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.143517834
Short name T574
Test name
Test status
Simulation time 2968335659 ps
CPU time 2.48 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:35:37 PM PDT 24
Peak memory 200972 kb
Host smart-1d13df00-2e36-46ea-a347-47e464e6d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143517834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.143517834
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1047059962
Short name T444
Test name
Test status
Simulation time 5581344655 ps
CPU time 13.89 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:35:47 PM PDT 24
Peak memory 201100 kb
Host smart-43045874-20ee-4501-8df1-523135fa93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047059962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1047059962
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3865068586
Short name T19
Test name
Test status
Simulation time 15251864910 ps
CPU time 37.28 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:36:13 PM PDT 24
Peak memory 201416 kb
Host smart-24215c83-70bd-41b1-a88a-f2396b8c9d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865068586 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3865068586
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2236802177
Short name T108
Test name
Test status
Simulation time 487727273 ps
CPU time 0.93 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:35:35 PM PDT 24
Peak memory 201016 kb
Host smart-3bae95d1-d446-451b-acda-f7e3e0f39842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236802177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2236802177
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1978231224
Short name T223
Test name
Test status
Simulation time 189738139682 ps
CPU time 391.62 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:42:05 PM PDT 24
Peak memory 201196 kb
Host smart-1be103ea-15c0-4a8c-881d-2b2064a3210d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978231224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1978231224
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2867459678
Short name T782
Test name
Test status
Simulation time 330379023532 ps
CPU time 730.54 seconds
Started Jul 27 06:35:32 PM PDT 24
Finished Jul 27 06:47:43 PM PDT 24
Peak memory 201252 kb
Host smart-7109ac3d-d1af-4fe5-8063-58816827f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867459678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2867459678
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1355088632
Short name T191
Test name
Test status
Simulation time 327182032999 ps
CPU time 717.57 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:47:31 PM PDT 24
Peak memory 201260 kb
Host smart-d0aa7836-422e-49cd-a1eb-6ff0758c504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355088632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1355088632
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3061970575
Short name T676
Test name
Test status
Simulation time 485858455620 ps
CPU time 1052.17 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:53:11 PM PDT 24
Peak memory 201280 kb
Host smart-dc0721af-3ae6-4e46-b05b-1a6683e74614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061970575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3061970575
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1291908686
Short name T772
Test name
Test status
Simulation time 490894114922 ps
CPU time 536.8 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:44:34 PM PDT 24
Peak memory 201340 kb
Host smart-3f1b6a21-ae27-47ca-96f4-f5f776fa6187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291908686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1291908686
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.166635063
Short name T535
Test name
Test status
Simulation time 329892011539 ps
CPU time 398.48 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:42:13 PM PDT 24
Peak memory 201188 kb
Host smart-eb1e22fa-5512-421d-ae8a-fece63401433
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=166635063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.166635063
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1680965718
Short name T139
Test name
Test status
Simulation time 196739231409 ps
CPU time 222.16 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:39:20 PM PDT 24
Peak memory 201276 kb
Host smart-21efd5b5-48bd-4ffb-9072-f154471e4137
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680965718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1680965718
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.886254880
Short name T447
Test name
Test status
Simulation time 412857210292 ps
CPU time 189.63 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:38:44 PM PDT 24
Peak memory 201204 kb
Host smart-a8c560d6-8503-416d-a4dd-914656b37518
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886254880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.886254880
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1707233584
Short name T346
Test name
Test status
Simulation time 117270343462 ps
CPU time 573.08 seconds
Started Jul 27 06:35:32 PM PDT 24
Finished Jul 27 06:45:05 PM PDT 24
Peak memory 201676 kb
Host smart-67f5d540-19d6-451a-87be-b3e1b98e534e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707233584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1707233584
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.656829260
Short name T460
Test name
Test status
Simulation time 37416079319 ps
CPU time 82.88 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:36:59 PM PDT 24
Peak memory 201048 kb
Host smart-88caad4a-91cb-4a1b-98d5-3de45cb52dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656829260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.656829260
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1451402968
Short name T132
Test name
Test status
Simulation time 5136600408 ps
CPU time 3.6 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:35:40 PM PDT 24
Peak memory 201048 kb
Host smart-6d68cf0d-a612-4987-a66f-b90633293264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451402968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1451402968
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3142377898
Short name T382
Test name
Test status
Simulation time 6225866710 ps
CPU time 2.3 seconds
Started Jul 27 06:35:33 PM PDT 24
Finished Jul 27 06:35:36 PM PDT 24
Peak memory 201052 kb
Host smart-bf0cebdc-52ce-48d0-8d08-5521210b123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142377898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3142377898
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3837565820
Short name T311
Test name
Test status
Simulation time 482053237270 ps
CPU time 1510.89 seconds
Started Jul 27 06:35:31 PM PDT 24
Finished Jul 27 07:00:43 PM PDT 24
Peak memory 212348 kb
Host smart-d1390add-1794-440e-8b59-f7b9090dec3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837565820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3837565820
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.51461737
Short name T533
Test name
Test status
Simulation time 312159459 ps
CPU time 0.84 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:35:35 PM PDT 24
Peak memory 200976 kb
Host smart-788ee644-333b-4699-9690-a84a66065cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51461737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.51461737
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1731674796
Short name T649
Test name
Test status
Simulation time 166205393192 ps
CPU time 192.6 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:38:48 PM PDT 24
Peak memory 201172 kb
Host smart-5e2de688-5515-48f1-b2e6-3ddca2561091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731674796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1731674796
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1031648538
Short name T288
Test name
Test status
Simulation time 333016289182 ps
CPU time 216.58 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:39:14 PM PDT 24
Peak memory 201260 kb
Host smart-12c54758-6c2a-49b1-b16b-9e2ec33d3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031648538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1031648538
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1681104039
Short name T630
Test name
Test status
Simulation time 482809767903 ps
CPU time 1075.9 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:53:31 PM PDT 24
Peak memory 201184 kb
Host smart-4ba50fcd-d014-4b49-b316-9c5e7fb237fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681104039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1681104039
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1809269595
Short name T643
Test name
Test status
Simulation time 322464813957 ps
CPU time 190.5 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:38:48 PM PDT 24
Peak memory 201180 kb
Host smart-7db34aea-b54b-4f4c-a778-f7aed2638288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809269595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1809269595
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4267425114
Short name T368
Test name
Test status
Simulation time 489805250148 ps
CPU time 318.11 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:40:52 PM PDT 24
Peak memory 201224 kb
Host smart-03bb933e-c15e-413f-9a65-62e0392f8939
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267425114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4267425114
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4061778929
Short name T566
Test name
Test status
Simulation time 209356181258 ps
CPU time 455.78 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:43:13 PM PDT 24
Peak memory 201080 kb
Host smart-5d1a6a36-c806-4da2-8e05-d8080dd7dc81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061778929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4061778929
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.402179174
Short name T523
Test name
Test status
Simulation time 27591377526 ps
CPU time 62.95 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:36:38 PM PDT 24
Peak memory 201040 kb
Host smart-6d7cbe57-84b8-4e1d-9a53-529e2e086786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402179174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.402179174
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1628593851
Short name T131
Test name
Test status
Simulation time 3908126091 ps
CPU time 8.58 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:35:44 PM PDT 24
Peak memory 201024 kb
Host smart-135d978d-817a-46f0-bd18-0af50114fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628593851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1628593851
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2406510464
Short name T129
Test name
Test status
Simulation time 5760504423 ps
CPU time 4.04 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:35:38 PM PDT 24
Peak memory 201056 kb
Host smart-ff6f8c94-fb8a-4ba5-9e2e-342c5696d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406510464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2406510464
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1154439866
Short name T555
Test name
Test status
Simulation time 357538483 ps
CPU time 0.82 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:35:46 PM PDT 24
Peak memory 201000 kb
Host smart-4f594481-d1ae-4ca5-b8e9-db3ff9d032c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154439866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1154439866
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.4256849832
Short name T215
Test name
Test status
Simulation time 453157824115 ps
CPU time 918.84 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:50:58 PM PDT 24
Peak memory 201292 kb
Host smart-a287b175-ffab-4e14-bee2-f7ebccd347d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256849832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.4256849832
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2245473083
Short name T95
Test name
Test status
Simulation time 493594652273 ps
CPU time 1102.76 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:53:57 PM PDT 24
Peak memory 201224 kb
Host smart-01c1457d-0d27-4a17-804e-4608a4d6f729
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245473083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2245473083
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2204669254
Short name T713
Test name
Test status
Simulation time 494008894244 ps
CPU time 1103.58 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:53:58 PM PDT 24
Peak memory 201264 kb
Host smart-b9360083-75cf-4854-842d-9d408632ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204669254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2204669254
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.892404979
Short name T432
Test name
Test status
Simulation time 166770802591 ps
CPU time 394.54 seconds
Started Jul 27 06:35:45 PM PDT 24
Finished Jul 27 06:42:19 PM PDT 24
Peak memory 201212 kb
Host smart-f9a02d98-c706-4891-a0dd-4fdbfb460a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=892404979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.892404979
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4165233566
Short name T380
Test name
Test status
Simulation time 199083102161 ps
CPU time 422.29 seconds
Started Jul 27 06:35:34 PM PDT 24
Finished Jul 27 06:42:37 PM PDT 24
Peak memory 201140 kb
Host smart-51c85525-59c5-4a66-a5ea-fab686105419
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165233566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4165233566
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1648937729
Short name T773
Test name
Test status
Simulation time 94115215090 ps
CPU time 362.82 seconds
Started Jul 27 06:35:36 PM PDT 24
Finished Jul 27 06:41:39 PM PDT 24
Peak memory 201696 kb
Host smart-7b673835-21e7-4f97-80c6-f699272a6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648937729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1648937729
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2538204902
Short name T186
Test name
Test status
Simulation time 40920921445 ps
CPU time 58.8 seconds
Started Jul 27 06:35:39 PM PDT 24
Finished Jul 27 06:36:38 PM PDT 24
Peak memory 201120 kb
Host smart-ed677d5b-faee-414c-8dbb-e565bad52139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538204902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2538204902
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1352653748
Short name T708
Test name
Test status
Simulation time 5429108117 ps
CPU time 6.33 seconds
Started Jul 27 06:35:38 PM PDT 24
Finished Jul 27 06:35:45 PM PDT 24
Peak memory 201012 kb
Host smart-05ab4f68-2dbe-4202-86c5-ac1e44dce616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352653748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1352653748
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2613945105
Short name T595
Test name
Test status
Simulation time 5887793526 ps
CPU time 7.86 seconds
Started Jul 27 06:35:35 PM PDT 24
Finished Jul 27 06:35:43 PM PDT 24
Peak memory 201032 kb
Host smart-e0c6aa12-ec65-49e6-ae3d-3fa164e974d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613945105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2613945105
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.287395664
Short name T62
Test name
Test status
Simulation time 44114426100 ps
CPU time 125.79 seconds
Started Jul 27 06:35:37 PM PDT 24
Finished Jul 27 06:37:43 PM PDT 24
Peak memory 210976 kb
Host smart-0589b1d9-8292-43e0-85a1-27eb7f9767aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287395664 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.287395664
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1714074574
Short name T488
Test name
Test status
Simulation time 377378406 ps
CPU time 1.48 seconds
Started Jul 27 06:35:50 PM PDT 24
Finished Jul 27 06:35:52 PM PDT 24
Peak memory 201020 kb
Host smart-cdbb3ad3-67e7-465c-aecb-d1cc47c278be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714074574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1714074574
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1095364003
Short name T783
Test name
Test status
Simulation time 209206267483 ps
CPU time 114.83 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:37:36 PM PDT 24
Peak memory 201168 kb
Host smart-a845f943-68bf-4d29-a647-ebd42d98db27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095364003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1095364003
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2586747579
Short name T291
Test name
Test status
Simulation time 173996170725 ps
CPU time 110.88 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:37:40 PM PDT 24
Peak memory 201232 kb
Host smart-95b8d972-bdde-4d47-8d5a-689d89427697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586747579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2586747579
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2473982645
Short name T663
Test name
Test status
Simulation time 489916507955 ps
CPU time 1112.39 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:54:14 PM PDT 24
Peak memory 201172 kb
Host smart-fed8957b-6b48-44d7-bd35-dbd43abb3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473982645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2473982645
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3059136445
Short name T398
Test name
Test status
Simulation time 323667273592 ps
CPU time 178.85 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:38:48 PM PDT 24
Peak memory 201212 kb
Host smart-268aa5b3-f0e8-4108-a7d2-fcbaa544a215
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059136445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3059136445
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.146773665
Short name T591
Test name
Test status
Simulation time 329689838315 ps
CPU time 99.32 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:37:28 PM PDT 24
Peak memory 201240 kb
Host smart-6b6b3525-8b79-4ee4-991b-a4bb2f1e84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146773665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.146773665
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1125848093
Short name T476
Test name
Test status
Simulation time 161595319887 ps
CPU time 370.82 seconds
Started Jul 27 06:35:43 PM PDT 24
Finished Jul 27 06:41:54 PM PDT 24
Peak memory 201172 kb
Host smart-24e71a74-5c0b-433f-bc38-1d67ca05cb36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125848093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1125848093
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1653550973
Short name T289
Test name
Test status
Simulation time 190373040719 ps
CPU time 195.42 seconds
Started Jul 27 06:35:48 PM PDT 24
Finished Jul 27 06:39:04 PM PDT 24
Peak memory 201224 kb
Host smart-6a3b07bb-a7c4-4ce3-96d8-0f7207de1c35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653550973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1653550973
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3604074256
Short name T609
Test name
Test status
Simulation time 413013061740 ps
CPU time 836.54 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:49:45 PM PDT 24
Peak memory 201236 kb
Host smart-b69ea942-dabf-48b6-baea-b421ad87fe3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604074256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3604074256
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3066180862
Short name T351
Test name
Test status
Simulation time 116459088000 ps
CPU time 431.43 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:42:52 PM PDT 24
Peak memory 201716 kb
Host smart-325632ce-f550-43ea-a137-81333891f1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066180862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3066180862
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2451578897
Short name T558
Test name
Test status
Simulation time 26748412566 ps
CPU time 10.84 seconds
Started Jul 27 06:35:43 PM PDT 24
Finished Jul 27 06:35:54 PM PDT 24
Peak memory 201080 kb
Host smart-6416b6de-25d4-440c-b83e-44d79a2c8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451578897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2451578897
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1920482376
Short name T441
Test name
Test status
Simulation time 4651967883 ps
CPU time 10.55 seconds
Started Jul 27 06:35:40 PM PDT 24
Finished Jul 27 06:35:51 PM PDT 24
Peak memory 201028 kb
Host smart-a8af96a0-7692-4233-ac2d-7829d5754195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920482376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1920482376
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3974162761
Short name T698
Test name
Test status
Simulation time 5689210537 ps
CPU time 2.63 seconds
Started Jul 27 06:35:41 PM PDT 24
Finished Jul 27 06:35:44 PM PDT 24
Peak memory 201044 kb
Host smart-9c154a8a-d84e-4aed-8302-c0ea3a07c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974162761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3974162761
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2377385596
Short name T50
Test name
Test status
Simulation time 240644930759 ps
CPU time 376.9 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:42:06 PM PDT 24
Peak memory 211288 kb
Host smart-3926e05e-22a9-47d1-8911-2c36f7c2bc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377385596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2377385596
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3311406451
Short name T331
Test name
Test status
Simulation time 23719960157 ps
CPU time 58.32 seconds
Started Jul 27 06:35:49 PM PDT 24
Finished Jul 27 06:36:48 PM PDT 24
Peak memory 209596 kb
Host smart-d79eb0c1-de13-48df-9d33-fa9d914bc43d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311406451 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3311406451
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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