Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7048	1			T1	35		T2	20		T7	50
testmodes[AdcCtrlTestmodeNormal]	5639	1			T1	53		T2	1		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5752	1			T1	36		T2	13		T3	21
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3728	1			T1	12		T2	19		T7	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1822	1			T1	15		T7	21		T36	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1391	1			T1	8		T2	1		T7	8
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1811	1			T1	16		T7	14		T36	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2059	1			T1	20		T6	2		T7	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1426	1			T1	16		T7	16		T33	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1392	1			T1	7		T7	16		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1422	1			T1	17		T2	1		T3	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2688	1			T1	12		T2	12		T3	20