Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23001

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3528

1

T7

14

T8

21

T11

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20443

1

T1

124

T2

35

T3

23

auto[1]

6086

1

T3

14

T6

25

T7

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T188	1		-	-		-	-
values[0]	45	1			T8	1		T133	1		T237	14
values[1]	677	1			T2	1		T11	3		T33	13
values[2]	872	1			T3	3		T7	3		T8	20
values[3]	630	1			T9	23		T178	6		T128	1
values[4]	662	1			T134	25		T127	28		T146	9
values[5]	636	1			T23	7		T29	35		T125	1
values[6]	797	1			T3	14		T5	22		T7	8
values[7]	644	1			T30	6		T135	12		T168	14
values[8]	2965	1			T6	25		T7	3		T10	9
values[9]	1104	1			T8	16		T13	2		T135	12
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	967	1			T2	1		T8	1		T11	3
values[1]	810	1			T3	3		T7	3		T8	20
values[2]	619	1			T33	8		T178	6		T128	1
values[3]	574	1			T9	23		T134	25		T168	28
values[4]	706	1			T3	14		T7	8		T23	7
values[5]	719	1			T5	22		T9	18		T40	20
values[6]	3005	1			T6	25		T7	3		T10	9
values[7]	638	1			T8	16		T129	22		T139	29
values[8]	806	1			T13	2		T135	12		T126	1
values[9]	176	1			T126	1		T188	1		T238	14
minimum	17509	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	1		T33	1		T29	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	1		T11	3		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T14	8		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T7	2		T8	20		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	7		T128	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T178	1		T158	1		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	12		T134	9		T146	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T134	4		T168	12		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	8		T29	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	3		T23	7		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	12		T9	14		T168	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	10		T27	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T6	3		T10	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	2		T33	2		T135	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	16		T129	12		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	1		T198	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T135	12		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T178	1		T187	15		T142	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T126	1		T238	10		T94	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T188	1		T239	1		T240	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17368	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	12		T29	14		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T125	12		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	2		T14	1		T16	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T134	9		T41	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	1		T34	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T178	5		T158	2		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	11		T134	8		T158	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	4		T168	16		T197	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	6		T29	22		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	5		T127	11		T168	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	10		T9	4		T168	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	10		T153	10		T241	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T6	22		T10	8		T37	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	1		T33	1		T177	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T129	10		T139	6		T159	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T139	14		T198	2		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	1		T16	4		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T178	10		T142	9		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T238	4		T94	13		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T245	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T33	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T188	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T246	1		T247	6		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T8	1		T133	1		T237	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T33	1		T29	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	3		T101	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T33	7		T14	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	2		T8	20		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	12		T128	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T178	1		T158	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T134	9		T146	9		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T134	4		T127	17		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	13		T197	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T23	7		T125	1		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	8		T5	12		T9	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	3		T40	10		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	1		T168	3		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	12		T128	1		T177	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T6	3		T10	1		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	2		T33	2		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T8	16		T13	1		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T178	1		T187	15		T236	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T247	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T237	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T33	12		T29	14		T125	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T125	12		T127	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	2		T33	1		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T134	9		T41	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	11		T16	10		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T178	5		T158	2		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T134	8		T34	1		T210	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	4		T127	11		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	22		T197	12		T158	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T168	16		T137	9		T197	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	6		T5	10		T9	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	5		T40	10		T168	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	5		T168	11		T249	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T177	11		T18	1		T250	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T6	22		T10	8		T37	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	1		T33	1		T139	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T13	1		T16	4		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T178	10		T236	9		T142	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T2	1		T33	13		T29	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	1		T11	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	3		T14	4		T16	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	3		T8	1		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	5		T128	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T178	6		T158	3		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	12		T134	9		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	5		T168	17		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	7		T29	23		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	6		T23	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	11		T9	5		T168	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	11		T27	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T6	25		T10	9		T37	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	2		T33	2		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T129	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T139	15		T198	3		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	2		T135	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T178	11		T187	1		T142	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T126	1		T238	5		T94	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T188	1		T239	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17509	1			T1	124		T2	34		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	15		T125	12		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	2		T13	1		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	5		T251	14		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	19		T134	9		T41	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	3		T17	2		T210	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	3		T251	7		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	11		T134	8		T146	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	3		T168	11		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	7		T29	12		T160	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	2		T23	6		T127	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	11		T9	13		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	9		T179	3		T153	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T103	28		T136	8		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T33	1		T135	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	15		T129	11		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T198	9		T242	11		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T135	11		T16	1		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T187	14		T142	4		T254	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T238	9		T94	2		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T240	12		T255	12		T245	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T188	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T246	1		T247	7		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T8	1		T133	1		T237	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T33	13		T29	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T101	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	3		T33	5		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	3		T8	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	12		T128	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T178	6		T158	3		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T134	9		T146	1		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T134	5		T127	12		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	23		T197	13		T158	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T23	1		T125	1		T168	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	7		T5	11		T9	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	6		T40	11		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	6		T168	12		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T135	1		T128	1		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T6	25		T10	9		T37	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	2		T33	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T8	1		T13	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T178	11		T187	1		T236	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T247	5		T214	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T237	11		T22	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T29	15		T125	12		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	2		T13	1		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	3		T14	5		T251	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	19		T134	9		T41	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	11		T17	2		T210	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	3		T130	14		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T134	8		T146	8		T210	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T134	3		T127	16		T130	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T29	12		T189	8		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T23	6		T168	11		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	7		T5	11		T9	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	2		T40	9		T168	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T168	2		T146	10		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	11		T177	8		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T103	28		T136	8		T257	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T33	1		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	15		T135	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T187	14		T236	7		T142	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22950

1

T1

124

T2

35

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3579

1

T3

3

T5

22

T7

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20648

1

T1

124

T2

34

T3

23

auto[1]

5881

1

T2

1

T3

14

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T175	1		T258	1		-	-
values[0]	32	1			T259	1		T260	9		T261	9
values[1]	685	1			T7	3		T127	2		T158	12
values[2]	544	1			T7	8		T11	3		T125	27
values[3]	745	1			T8	16		T13	2		T134	19
values[4]	2943	1			T3	3		T6	25		T8	20
values[5]	931	1			T13	3		T126	1		T127	14
values[6]	609	1			T3	14		T5	22		T8	1
values[7]	836	1			T7	3		T14	9		T30	6
values[8]	525	1			T29	65		T135	13		T126	1
values[9]	1181	1			T2	1		T9	23		T33	8
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T7	3		T125	27		T127	30
values[1]	596	1			T7	8		T8	16		T11	3
values[2]	811	1			T3	3		T8	20		T13	2
values[3]	2991	1			T6	25		T10	9		T33	13
values[4]	719	1			T5	22		T9	18		T30	3
values[5]	639	1			T3	14		T8	1		T33	3
values[6]	709	1			T14	9		T30	6		T134	25
values[7]	694	1			T7	3		T29	65		T125	1
values[8]	806	1			T9	23		T33	8		T40	20
values[9]	189	1			T2	1		T198	12		T159	8
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T127	1		T17	5		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	2		T125	15		T127	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	3		T11	3		T251	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	16		T138	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T135	12		T158	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T3	1		T8	20		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T33	1		T101	1		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	14		T30	1		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	12		T168	3		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	8		T8	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T34	3		T197	1		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	8		T30	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	4		T126	1		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T29	13		T41	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	2		T29	16		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	12		T40	10		T23	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	7		T125	13		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T2	1		T198	7		T242	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T159	1		T262	6		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T127	1		T17	1		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	1		T125	12		T127	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	5		T238	4		T263	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	7		T142	2		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	1		T158	5		T98	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	2		T134	9		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T33	12		T13	1		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	4		T30	2		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	10		T168	11		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	6		T33	1		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	1		T197	12		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T30	5		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	4		T16	4		T139	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	22		T41	10		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	1		T29	14		T176	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	11		T40	10		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T33	1		T125	11		T168	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T198	5		T242	8		T264	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T159	7		T262	1		T265	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T175	1		T258	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	1		T267	4		T268	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	1		T260	3		T261	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T127	1		T17	5		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	2		T158	1		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	3		T11	3		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T125	15		T127	17		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T135	12		T158	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T8	16		T134	10		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T6	3		T10	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	1		T8	20		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T127	12		T139	1		T269	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	2		T126	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	8		T8	1		T9	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	12		T168	3		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	8		T30	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	2		T134	4		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	13		T137	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T29	16		T135	13		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T2	1		T9	12		T40	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T33	7		T125	14		T168	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T266	2		T267	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T260	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T127	1		T17	1		T253	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T158	11		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T7	5		T270	7		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T125	12		T127	11		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T158	5		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	9		T178	5		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T6	22		T10	8		T37	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	2		T33	12		T271	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T127	2		T269	11		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T178	10		T272	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	6		T9	4		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	10		T168	11		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	1		T30	5		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T134	4		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	22		T137	10		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T29	14		T152	2		T273	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	11		T40	10		T41	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	1		T125	11		T168	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1