Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23025

1

T1

124

T2

35

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3504

1

T3

14

T7

11

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20625

1

T1

124

T2

34

T3

23

auto[1]

5904

1

T2

1

T3

14

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T7	3		T33	11		T27	1
values[0]	46	1			T338	22		T339	12		T319	12
values[1]	578	1			T5	22		T9	18		T11	3
values[2]	669	1			T101	1		T13	2		T127	28
values[3]	648	1			T2	1		T30	3		T146	9
values[4]	705	1			T23	7		T29	30		T135	12
values[5]	2894	1			T3	14		T6	25		T7	3
values[6]	785	1			T3	3		T8	16		T29	35
values[7]	611	1			T33	13		T135	12		T168	30
values[8]	708	1			T7	8		T8	1		T40	20
values[9]	1104	1			T9	23		T13	3		T125	27
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	531	1			T5	22		T9	18		T14	9
values[1]	657	1			T2	1		T13	2		T127	28
values[2]	658	1			T101	1		T30	3		T146	9
values[3]	2938	1			T6	25		T10	9		T37	23
values[4]	657	1			T3	14		T7	3		T8	36
values[5]	754	1			T3	3		T29	35		T126	1
values[6]	650	1			T33	13		T30	6		T135	12
values[7]	711	1			T7	8		T8	1		T40	20
values[8]	991	1			T7	3		T9	23		T33	11
values[9]	226	1			T134	17		T127	14		T158	12
minimum	17756	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	12		T9	14		T14	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	3		T187	6		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T137	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T127	17		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T139	13		T131	1		T210	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T101	1		T30	1		T146	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T178	1		T208	1		T253	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	2		T8	16		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	8		T8	20		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T126	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	13		T127	1		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	1		T197	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T33	1		T135	12		T168	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	1		T125	13		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	3		T40	10		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	12		T125	15		T134	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T7	2		T33	9		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T127	12		T133	1		T153	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	9		T158	1		T160	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17450	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T146	11		T130	11		T308	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	10		T9	4		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T34	1		T237	12		T323	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T137	9		T158	3		T322	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	1		T127	11		T16	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T139	15		T238	4		T94	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T30	2		T139	14		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T178	5		T253	7		T252	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T134	9		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	6		T168	16		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T159	7		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	22		T127	1		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	5		T197	2		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T33	12		T168	16		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T125	11		T178	10		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	5		T40	10		T41	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	11		T125	12		T134	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	1		T33	2		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T127	2		T153	10		T290	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T134	8		T158	11		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T308	7		T262	1		T340	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T134	4		T127	12		T271	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T7	2		T33	9		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T338	11		T339	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T319	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	12		T9	14		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	11		T130	11		T236	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T137	1		T251	15		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T101	1		T13	1		T127	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T158	1		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T146	9		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T23	7		T29	16		T135	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T178	1		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T6	3		T7	2		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	8		T8	20		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T8	16		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	13		T127	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T197	1		T159	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T33	1		T135	12		T168	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T30	1		T125	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	3		T40	10		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	12		T125	15		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T13	2		T41	11		T243	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T134	4		T127	2		T271	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T7	1		T33	2		T134	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T338	11		T339	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	10		T9	4		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T236	9		T237	12		T323	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T137	9		T35	5		T322	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T127	11		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T158	3		T139	15		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T30	2		T16	14		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	14		T142	9		T150	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T178	5		T253	7		T252	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T6	22		T7	1		T10	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	6		T168	16		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	2		T134	9		T159	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	22		T127	1		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T197	2		T159	10		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	12		T168	16		T305	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	5		T125	11		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	5		T40	10		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	11		T125	12		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T13	1		T41	10		T243	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	11		T9	5		T14	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T34	4		T187	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T137	10		T158	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	2		T127	12		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T139	16		T131	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T101	1		T30	3		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T178	6		T208	1		T253	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	2		T8	1		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	7		T8	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	3		T126	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T29	23		T127	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	6		T197	3		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	13		T135	1		T168	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T125	12		T178	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	6		T40	11		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	12		T125	13		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T7	3		T33	7		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T127	3		T133	1		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T134	9		T158	12		T160	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17594	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T146	1		T130	1		T308	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	11		T9	13		T14	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T187	5		T259	7		T323	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T251	14		T170	16		T322	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T127	16		T16	1		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T139	12		T210	2		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	8		T147	11		T177	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T23	6		T29	15		T103	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T253	4		T252	11		T270	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T8	15		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	7		T8	19		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T242	4		T210	14		T250	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	12		T198	6		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T242	11		T249	10		T313	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	11		T168	13		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T125	12		T15	1		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	2		T40	9		T41	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	11		T125	14		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T33	4		T13	1		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T127	11		T153	2		T290	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T134	8		T160	17		T308	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T11	2		T139	7		T274	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T146	10		T130	10		T308	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T134	5		T127	3		T271	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	3		T33	7		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T338	12		T339	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T319	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	11		T9	5		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T146	1		T130	1		T236	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	10		T251	1		T35	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T101	1		T13	2		T127	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	1		T158	4		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	3		T146	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T23	1		T29	15		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T178	6		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T6	25		T7	2		T10	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	7		T8	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	3		T8	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	23		T127	2		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T197	3		T159	11		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T33	13		T135	1		T168	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	1		T30	6		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	6		T40	11		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	12		T125	13		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T13	2		T41	11		T243	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	3		T127	11		T19	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T33	4		T134	8		T269	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T338	10		T339	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	11		T9	13		T11	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T146	10		T130	10		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T251	14		T170	16		T322	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	16		T187	19		T142	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T139	12		T210	2		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T146	8		T16	1		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T23	6		T29	15		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T253	4		T252	11		T74	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T7	1		T103	28		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	7		T8	19		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	15		T134	9		T242	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	12		T198	6		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T242	11		T250	9		T313	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	11		T168	13		T141	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T125	12		T15	1		T160	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	2		T40	9		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	11		T125	14		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T13	1		T41	10		T243	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3