Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22983

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3546

1

T5

22

T7

3

T8

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20713

1

T1

124

T2

34

T3

37

auto[1]

5816

1

T2

1

T6

25

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T41	21		T271	5		T34	4
values[0]	23	1			T341	1		T317	1		T266	3
values[1]	683	1			T7	3		T9	23		T11	3
values[2]	656	1			T33	3		T23	7		T27	1
values[3]	726	1			T3	14		T7	3		T9	18
values[4]	754	1			T8	1		T125	24		T139	1
values[5]	682	1			T2	1		T126	2		T127	2
values[6]	886	1			T8	16		T13	2		T30	6
values[7]	615	1			T33	8		T40	20		T125	1
values[8]	597	1			T8	20		T101	1		T13	3
values[9]	3182	1			T3	3		T5	22		T6	25
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	621	1			T7	3		T9	23		T11	3
values[1]	690	1			T33	3		T23	7		T27	1
values[2]	835	1			T3	14		T7	3		T9	18
values[3]	650	1			T8	1		T126	1		T138	1
values[4]	815	1			T2	1		T13	2		T126	1
values[5]	736	1			T8	16		T40	20		T30	6
values[6]	2874	1			T6	25		T10	9		T33	8
values[7]	586	1			T8	20		T33	13		T101	1
values[8]	935	1			T3	3		T5	22		T7	8
values[9]	102	1			T250	10		T151	17		T259	7
minimum	17685	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	2		T11	3		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	12		T137	1		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	2		T23	7		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T27	1		T135	25		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	8		T14	8		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	2		T9	14		T125	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T160	18		T238	10		T124	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	1		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	1		T13	1		T243	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T126	1		T127	1		T168	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	16		T40	10		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T30	1		T168	12		T146	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T6	3		T10	1		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	10		T126	1		T168	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	4		T158	1		T170	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	20		T33	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T7	3		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	12		T29	16		T41	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T260	3		T318	3		T284	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T250	10		T151	17		T259	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17396	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T146	11		T16	4		T274	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T178	10		T158	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	11		T137	10		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	1		T178	5		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	14		T35	5		T177	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	6		T14	1		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	1		T9	4		T125	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T160	2		T238	4		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T287	12		T188	13		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T243	9		T269	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	1		T168	11		T272	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	10		T127	2		T16	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	5		T168	16		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T6	22		T10	8		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	9		T168	16		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T134	4		T158	11		T294	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T33	12		T13	1		T29	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	2		T7	5		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	10		T29	14		T41	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T260	6		T318	10		T284	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T16	4		T330	11		T338	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T241	1		T260	3		T318	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T41	11		T271	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T321	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T341	1		T317	1		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	2		T11	3		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	12		T146	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T33	2		T23	7		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	1		T135	25		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	8		T14	8		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	2		T9	14		T127	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T243	8		T270	11		T328	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T125	13		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T251	8		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T126	2		T127	1		T168	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T8	16		T13	1		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T30	1		T168	12		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	7		T40	10		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T126	1		T168	14		T146	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	4		T128	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	20		T101	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T3	1		T6	3		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	12		T33	1		T29	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T241	10		T260	6		T318	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T41	10		T271	4		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T266	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T178	10		T158	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	11		T137	10		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	1		T178	5		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T177	11		T210	2		T91	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	6		T14	1		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T9	4		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T243	9		T270	3		T328	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T125	11		T287	12		T188	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T147	9		T160	2		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	1		T168	11		T272	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	1		T127	2		T269	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	5		T168	16		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	1		T40	10		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T168	16		T139	6		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T134	4		T158	11		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T29	22		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T3	2		T6	22		T7	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	10		T33	12		T29	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	3		T11	1		T178	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	12		T137	11		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T33	2		T23	1		T178	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	1		T135	2		T139	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	7		T14	4		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	2		T9	5		T125	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T160	3		T238	5		T124	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	1		T13	2		T243	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T126	1		T127	2		T168	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T40	11		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	6		T168	17		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T6	25		T10	9		T33	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T134	10		T126	1		T168	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T134	5		T158	12		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T33	13		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	3		T7	6		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	11		T29	15		T41	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T260	9		T318	11		T284	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T250	1		T151	1		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T146	1		T16	7		T274	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	2		T297	4		T152	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	11		T198	9		T242	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	1		T23	6		T139	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T135	23		T177	8		T94	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	7		T14	5		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	1		T9	13		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T160	17		T238	9		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T287	9		T188	8		T150	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T243	7		T269	13		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T168	2		T17	2		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	15		T40	9		T127	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T168	11		T146	8		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T33	3		T103	28		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T134	9		T168	13		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T134	3		T170	16		T294	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	19		T13	1		T29	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	2		T135	11		T210	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	11		T29	15		T41	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T318	2		T324	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T250	9		T151	16		T259	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T264	11		T342	10		T321	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T146	10		T16	1		T274	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T241	11		T260	9		T318	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T41	11		T271	5		T34	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T321	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T341	1		T317	1		T266	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	3		T11	1		T178	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	12		T146	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T33	2		T23	1		T178	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T27	1		T135	2		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	7		T14	4		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	2		T9	5		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T243	10		T270	4		T328	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T125	12		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T251	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T126	2		T127	2		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	1		T13	2		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T30	6		T168	17		T158	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	5		T40	11		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T126	1		T168	17		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T134	5		T128	1		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	1		T101	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T3	3		T6	25		T7	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	11		T33	13		T29	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T318	2		T286	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T41	10		T274	9		T151	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T321	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	2		T152	9		T323	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	11		T146	10		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	1		T23	6		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T135	23		T177	8		T309	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	7		T14	5		T125	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T9	13		T127	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T243	7		T270	10		T273	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T125	12		T287	9		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T251	7		T147	11		T160	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T168	2		T17	2		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	15		T127	11		T269	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T168	11		T129	11		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T33	3		T40	9		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T168	13		T146	8		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	3		T35	1		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	19		T13	1		T29	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T7	2		T103	28		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	11		T29	15		T130	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3