Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22972

1

T1

124

T2

35

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3557

1

T3

3

T5

22

T7

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20637

1

T1

124

T2

34

T3

23

auto[1]

5892

1

T2

1

T3

14

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T2	1		T126	1		T15	6
values[0]	42	1			T259	1		T260	9		T71	10
values[1]	626	1			T7	3		T127	2		T158	12
values[2]	620	1			T7	8		T11	3		T125	27
values[3]	681	1			T8	16		T13	2		T134	19
values[4]	3042	1			T3	3		T6	25		T8	20
values[5]	865	1			T13	3		T126	1		T127	14
values[6]	641	1			T3	14		T5	22		T8	1
values[7]	724	1			T14	9		T30	6		T134	25
values[8]	644	1			T7	3		T29	65		T135	13
values[9]	885	1			T9	23		T33	8		T40	20
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T7	3		T125	27		T127	30
values[1]	684	1			T7	8		T8	16		T11	3
values[2]	746	1			T8	20		T13	2		T134	19
values[3]	2967	1			T3	3		T6	25		T10	9
values[4]	758	1			T5	22		T9	18		T30	3
values[5]	657	1			T3	14		T8	1		T33	3
values[6]	742	1			T7	3		T14	9		T30	6
values[7]	621	1			T29	65		T125	1		T135	13
values[8]	909	1			T2	1		T9	23		T33	8
values[9]	101	1			T159	8		T242	20		T264	24
minimum	17715	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T127	1		T17	5		T253	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	2		T125	15		T127	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	3		T11	3		T251	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	16		T138	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T135	12		T158	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T8	20		T134	10		T135	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T33	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	14		T30	1		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	12		T126	1		T168	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	8		T8	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T34	3		T197	1		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	8		T30	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	2		T134	4		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T29	13		T41	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	16		T125	1		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	1		T9	12		T40	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	7		T125	13		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T242	12		T264	12		T77	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T159	1		T262	6		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17422	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T259	1		T260	3		T307	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T127	1		T17	1		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T125	12		T127	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	5		T238	4		T270	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	7		T142	2		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T13	1		T158	5		T98	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	9		T129	10		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	2		T33	12		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	4		T30	2		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	10		T168	11		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	6		T33	1		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	1		T197	12		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T30	5		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	1		T134	4		T16	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T29	22		T41	10		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	14		T152	2		T273	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	11		T40	10		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T33	1		T125	11		T168	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T242	8		T264	12		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T159	7		T262	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T260	6		T307	1		T291	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	1		T126	1		T15	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T262	6		T181	1		T343	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T71	1		T266	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	1		T260	3		T344	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	1		T17	5		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	2		T158	1		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	3		T11	3		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T125	15		T127	17		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T135	12		T158	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	16		T134	10		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T6	3		T10	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	1		T8	20		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T127	12		T139	1		T243	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	2		T126	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	8		T8	1		T9	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	12		T168	3		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	8		T30	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T134	4		T16	4		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T29	13		T137	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	2		T29	16		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	12		T40	10		T23	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T33	7		T125	14		T168	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	1		T16	10		T155	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T262	1		T343	3		T345	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T71	9		T266	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T260	6		T344	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	1		T17	1		T253	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T158	11		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	5		T270	7		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T125	12		T127	11		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T158	5		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T134	9		T178	5		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T6	22		T10	8		T37	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	2		T33	12		T271	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T127	2		T243	9		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T178	10		T272	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	6		T9	4		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	10		T168	11		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	1		T30	5		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	4		T16	4		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	22		T137	10		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	1		T29	14		T152	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	11		T40	10		T41	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	1		T125	11		T168	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T127	2		T17	3		T253	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	2		T125	13		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	6		T11	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T138	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	2		T135	1		T158	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	1		T134	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	3		T33	13		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	5		T30	3		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	11		T126	1		T168	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	7		T8	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T34	4		T197	13		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	4		T30	6		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	3		T134	5		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	23		T41	11		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	15		T125	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T2	1		T9	12		T40	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	5		T125	12		T168	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T242	9		T264	13		T77	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T159	8		T262	6		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17560	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T259	1		T260	9		T307	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T17	3		T253	4		T274	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T125	14		T127	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T11	2		T251	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	15		T140	7		T142	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T135	11		T98	4		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	19		T134	9		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T103	28		T168	11		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T187	5		T170	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	13		T127	11		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	11		T168	2		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	7		T33	1		T146	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T198	9		T147	11		T160	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	5		T134	8		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	3		T16	1		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	12		T41	10		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	15		T135	12		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	11		T40	9		T23	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	3		T125	12		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T242	11		T264	11		T77	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T262	1		T275	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T19	3		T342	7		T265	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T307	1		T291	12		T346	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	1		T126	1		T15	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T262	6		T181	1		T343	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T71	10		T266	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T259	1		T260	9		T344	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T127	2		T17	3		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	2		T158	12		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	6		T11	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T125	13		T127	12		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	2		T135	1		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T134	10		T178	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T6	25		T10	9		T37	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	3		T8	1		T33	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T127	3		T139	1		T243	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	2		T126	1		T178	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	7		T8	1		T9	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	11		T168	12		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	4		T30	6		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	5		T16	7		T139	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	23		T137	11		T197	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	3		T29	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T9	12		T40	11		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T33	5		T125	13		T168	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	1		T151	16		T155	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T262	1		T343	2		T345	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T344	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T17	3		T253	4		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	1		T17	2		T210	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	2		T11	2		T274	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T125	14		T127	16		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	11		T251	7		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	15		T134	9		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T103	28		T168	11		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	19		T135	11		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T127	11		T243	7		T269	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T35	1		T297	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	7		T9	13		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	11		T168	2		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	5		T134	8		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	3		T16	1		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	12		T139	7		T277	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	15		T135	12		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	11		T40	9		T23	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	3		T125	12		T168	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3