Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23190

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3339

1

T7

3

T8

16

T9

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20658

1

T1

124

T2

35

T3

37

auto[1]

5871

1

T5

22

T6

25

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	388	1			T5	22		T9	23		T125	27
values[0]	9	1			T3	3		T347	6		-	-
values[1]	720	1			T7	3		T30	3		T126	1
values[2]	2775	1			T2	1		T6	25		T8	16
values[3]	720	1			T125	1		T168	28		T178	6
values[4]	872	1			T8	1		T13	2		T29	30
values[5]	593	1			T8	20		T40	20		T23	7
values[6]	589	1			T7	11		T11	3		T33	24
values[7]	752	1			T3	14		T29	35		T30	6
values[8]	671	1			T9	18		T134	19		T135	12
values[9]	944	1			T101	1		T14	9		T134	8
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	589	1			T3	3		T7	3		T30	3
values[1]	2839	1			T2	1		T6	25		T8	16
values[2]	714	1			T13	2		T125	1		T135	12
values[3]	752	1			T8	1		T29	30		T138	1
values[4]	706	1			T8	20		T11	3		T40	20
values[5]	611	1			T7	11		T33	24		T13	3
values[6]	650	1			T3	14		T30	6		T125	24
values[7]	726	1			T9	18		T135	12		T126	1
values[8]	975	1			T5	22		T101	1		T14	9
values[9]	214	1			T9	23		T134	8		T17	4
minimum	17753	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T30	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	2		T127	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T2	1		T6	3		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	16		T27	1		T170	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T125	1		T135	12		T168	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T16	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T242	12		T312	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	16		T138	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	20		T11	3		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T168	3		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	5		T33	9		T29	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T33	1		T13	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	8		T125	13		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T30	1		T41	11		T129	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T137	1		T139	8		T243	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	14		T135	12		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T5	12		T14	8		T134	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T101	1		T125	15		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T134	4		T236	8		T94	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T9	12		T17	3		T160	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17405	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T177	9		T124	7		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	2		T30	2		T272	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T127	1		T139	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T6	22		T10	8		T37	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T263	15		T311	14		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T168	16		T178	5		T35	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T16	4		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T242	8		T312	9		T241	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T29	14		T15	1		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	10		T16	10		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T168	11		T252	12		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	6		T33	2		T29	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T33	12		T13	1		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	6		T125	11		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	5		T41	10		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T137	9		T139	6		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	4		T210	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	10		T14	1		T134	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T125	12		T158	13		T279	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T134	4		T236	9		T94	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T9	11		T17	1		T160	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T177	11		T124	3		T348	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	12		T134	9		T127	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	12		T125	15		T160	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T3	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T347	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T30	1		T126	1		T168	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	2		T127	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	1		T6	3		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	16		T27	1		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T125	1		T168	12		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	1		T147	12		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T135	25		T242	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T29	16		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	20		T40	10		T23	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T168	3		T138	1		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	5		T11	3		T33	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T33	1		T13	2		T198	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	8		T29	13		T125	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	1		T41	11		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T134	10		T178	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	14		T135	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	8		T134	4		T127	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T101	1		T126	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	10		T134	8		T127	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T9	11		T125	12		T160	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T3	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T347	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T168	16		T272	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T127	1		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T6	22		T10	8		T37	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T311	14		T282	9		T349	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T168	16		T178	5		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T147	9		T263	15		T288	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T242	8		T312	9		T254	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T29	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T40	10		T16	10		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T168	11		T198	2		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	6		T33	2		T197	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T33	12		T13	1		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	6		T29	22		T125	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	5		T41	10		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T134	9		T178	10		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	4		T250	9		T189	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	1		T134	4		T127	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T158	13		T17	1		T210	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	3		T30	3		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	3		T127	2		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	1		T6	25		T10	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	1		T27	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T125	1		T135	1		T168	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	2		T16	7		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	1		T242	9		T312	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T29	15		T138	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	1		T11	1		T40	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T168	12		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	8		T33	7		T29	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T33	13		T13	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	7		T125	12		T178	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	6		T41	11		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	10		T139	7		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	5		T135	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	11		T14	4		T134	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T101	1		T125	13		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T134	5		T236	10		T94	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T9	12		T17	2		T160	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17555	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T177	12		T124	10		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T141	21		T211	13		T155	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T251	7		T253	4		T249	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T103	28		T136	8		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	15		T170	16		T311	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T135	11		T168	11		T146	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T147	11		T287	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T242	11		T312	7		T171	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	15		T15	1		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	19		T11	2		T40	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T168	2		T252	11		T313	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	3		T33	4		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T13	1		T198	6		T276	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	7		T125	12		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	10		T129	11		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	7		T243	7		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	13		T135	11		T210	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	11		T14	5		T134	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T125	14		T187	14		T279	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T134	3		T236	7		T94	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T9	11		T17	2		T160	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T168	13		T270	10		T350	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T177	8		T259	6		T77	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	11		T134	9		T127	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	12		T125	13		T160	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T3	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T347	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	3		T126	1		T168	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	3		T127	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	1		T6	25		T10	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T27	1		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T125	1		T168	17		T178	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T131	1		T147	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T135	2		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T13	2		T29	15		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T40	11		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T168	12		T138	1		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	8		T11	1		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T33	13		T13	2		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	7		T29	23		T125	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	6		T41	11		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T134	10		T178	11		T137	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	5		T135	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T14	4		T134	5		T127	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T101	1		T126	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	11		T134	8		T127	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T9	11		T125	14		T160	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T347	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T168	13		T141	21		T270	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T251	7		T177	8		T253	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T103	28		T136	8		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	15		T311	11		T351	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T168	11		T146	8		T130	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T147	11		T141	9		T170	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T135	23		T242	11		T312	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	15		T15	1		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	19		T40	9		T23	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T168	2		T198	9		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T11	2		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T13	1		T198	6		T276	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	7		T29	12		T125	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	10		T129	11		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T134	9		T139	7		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	13		T135	11		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	5		T134	3		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T17	2		T187	14		T210	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3