Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23025

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3504

1

T7

11

T8

20

T33

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20881

1

T1

124

T2

34

T3

23

auto[1]

5648

1

T2

1

T3

14

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	77	1			T290	21		T307	6		T282	16
values[0]	81	1			T5	22		T274	10		T338	22
values[1]	541	1			T11	3		T14	9		T125	1
values[2]	620	1			T9	18		T101	1		T13	2
values[3]	705	1			T2	1		T127	28		T128	1
values[4]	672	1			T23	7		T29	30		T30	3
values[5]	2961	1			T6	25		T7	3		T8	20
values[6]	678	1			T3	17		T8	16		T134	19
values[7]	756	1			T33	13		T30	6		T135	12
values[8]	639	1			T7	8		T8	1		T40	20
values[9]	1303	1			T7	3		T9	23		T33	11
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T5	22		T9	18		T11	3
values[1]	695	1			T2	1		T101	1		T13	2
values[2]	674	1			T23	7		T30	3		T146	9
values[3]	2912	1			T6	25		T10	9		T37	23
values[4]	690	1			T3	14		T7	3		T8	20
values[5]	702	1			T3	3		T8	16		T29	35
values[6]	626	1			T33	13		T135	12		T168	30
values[7]	786	1			T7	8		T8	1		T40	20
values[8]	873	1			T7	3		T33	11		T13	3
values[9]	307	1			T9	23		T134	17		T127	14
minimum	17504	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T5	12		T9	14		T11	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	11		T34	3		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T125	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T101	1		T13	1		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	1		T146	9		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	7		T208	1		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T168	12		T178	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	8		T7	2		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	20		T135	13		T130	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	1		T8	16		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	13		T127	1		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T197	1		T159	1		T242	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	1		T135	12		T168	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	1		T30	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	3		T40	10		T125	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T125	15		T134	4		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T7	2		T33	9		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T9	12		T127	12		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T134	9		T158	1		T160	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T262	6		T352	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	10		T9	4		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T34	1		T237	12		T308	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T137	9		T158	3		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T127	11		T16	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	2		T147	9		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	29		T177	11		T91	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T168	16		T178	5		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	6		T7	1		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T94	9		T98	4		T296	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	2		T197	2		T159	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	22		T127	1		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T197	12		T159	10		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T33	12		T168	16		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	5		T178	10		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	5		T40	10		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T125	12		T134	4		T271	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	1		T33	2		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T9	11		T127	2		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T134	8		T158	11		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T290	11		T307	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T282	7		T181	1		T353	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	12		T274	10		T338	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T339	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	3		T14	8		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T146	11		T130	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	14		T137	1		T251	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T101	1		T13	1		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	1		T128	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T127	17		T16	5		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	16		T30	1		T135	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	7		T178	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T6	3		T7	2		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	20		T29	13		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	9		T8	16		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T127	1		T197	1		T198	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	1		T197	1		T159	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T33	1		T135	12		T168	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	1		T178	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	3		T40	10		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T9	12		T125	15		T134	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	421	1			T7	2		T33	9		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T290	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T282	9		T353	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T5	10		T338	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T339	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	1		T139	6		T297	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T237	12		T308	7		T262	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	4		T137	9		T35	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T34	1		T210	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T158	3		T147	9		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T127	11		T16	14		T139	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	14		T30	2		T272	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T178	5		T253	7		T252	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T6	22		T7	1		T10	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	22		T168	16		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	8		T134	9		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T127	1		T198	5		T250	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	5		T197	2		T159	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	12		T168	16		T305	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T178	10		T15	1		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	5		T40	10		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	11		T125	12		T134	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T7	1		T33	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	11		T9	5		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T146	1		T34	4		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T125	1		T137	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T101	1		T13	2		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T30	3		T146	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T23	1		T208	1		T139	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T168	17		T178	6		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	7		T7	2		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	1		T135	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	3		T8	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	23		T127	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T197	13		T159	11		T242	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	13		T135	1		T168	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T30	6		T178	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	6		T40	11		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T125	13		T134	5		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	3		T33	7		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T9	12		T127	3		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T134	9		T158	12		T160	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T262	6		T352	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	11		T9	13		T11	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	10		T130	10		T187	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T251	14		T236	7		T170	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T127	16		T16	1		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T146	8		T147	11		T210	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T23	6		T139	12		T177	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T29	15		T103	28		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T168	11		T253	4		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	7		T7	1		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	19		T135	12		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	15		T242	4		T210	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	12		T198	6		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T242	11		T249	10		T313	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T135	11		T168	13		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	1		T160	8		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	2		T40	9		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T125	14		T134	3		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T33	4		T13	1		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T9	11		T127	11		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T134	8		T160	17		T274	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T290	11		T307	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T282	10		T181	1		T353	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T5	11		T274	1		T338	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T339	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T14	4		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T146	1		T130	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	5		T137	10		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T101	1		T13	2		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T128	1		T158	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T127	12		T16	18		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	15		T30	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T23	1		T178	6		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T6	25		T7	2		T10	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T29	23		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	10		T8	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	2		T197	1		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	6		T197	3		T159	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T33	13		T135	1		T168	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T178	11		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	6		T40	11		T125	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T9	12		T125	13		T134	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T7	3		T33	7		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T290	10		T307	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T282	6		T353	9		T283	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T5	11		T274	9		T338	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T339	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T14	5		T139	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	10		T130	10		T259	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	13		T251	14		T170	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T187	19		T313	10		T281	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T147	11		T210	2		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T127	16		T16	1		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	15		T135	11		T146	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T23	6		T253	4		T252	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T7	1		T103	28		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	19		T29	12		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	7		T8	15		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T198	6		T130	12		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T242	22		T250	9		T249	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T135	11		T168	13		T141	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T15	1		T160	8		T188	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	2		T40	9		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	11		T125	14		T134	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T33	4		T13	1		T134	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3