Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22970

1

T1

124

T2

35

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3559

1

T3

3

T7

11

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20727

1

T1

124

T2

34

T3

37

auto[1]

5802

1

T2

1

T5

22

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	75	1			T238	14		T337	15		T354	6
values[0]	68	1			T158	12		T130	15		T143	11
values[1]	614	1			T7	11		T8	1		T9	41
values[2]	552	1			T7	3		T11	3		T27	1
values[3]	865	1			T33	13		T29	30		T134	19
values[4]	650	1			T3	3		T41	21		T178	11
values[5]	2981	1			T6	25		T10	9		T37	23
values[6]	616	1			T3	14		T33	8		T101	1
values[7]	779	1			T5	22		T30	3		T125	1
values[8]	592	1			T126	1		T208	1		T139	28
values[9]	1241	1			T2	1		T8	36		T33	3
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	820	1			T7	8		T8	1		T9	41
values[1]	754	1			T7	6		T11	3		T178	6
values[2]	690	1			T3	3		T33	13		T29	30
values[3]	2934	1			T6	25		T10	9		T37	23
values[4]	577	1			T101	1		T126	1		T146	9
values[5]	752	1			T3	14		T5	22		T33	8
values[6]	680	1			T30	3		T135	12		T168	30
values[7]	689	1			T33	3		T134	8		T168	14
values[8]	891	1			T2	1		T8	20		T125	27
values[9]	214	1			T8	16		T14	9		T127	14
minimum	17528	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T9	14		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	3		T9	12		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	2		T178	1		T198	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	2		T11	3		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	1		T29	16		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	1		T134	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	13		T41	11		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T101	1		T126	1		T146	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T137	1		T139	1		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	8		T5	12		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	7		T23	7		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	1		T135	12		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T168	14		T137	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	4		T139	13		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	2		T168	3		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	1		T125	15		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T8	20		T135	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T8	16		T271	1		T243	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T14	8		T127	12		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17366	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T158	1		T331	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	4		T13	1		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	5		T9	11		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	1		T178	5		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T176	13		T177	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	12		T29	14		T198	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	2		T134	9		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	22		T41	10		T178	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T158	2		T159	10		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T137	9		T98	4		T270	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	6		T5	10		T40	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	1		T30	5		T287	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	2		T272	6		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T168	16		T137	10		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T134	4		T139	15		T277	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	1		T168	11		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T125	12		T34	1		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T127	11		T197	2		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T271	4		T243	9		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T14	1		T127	2		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T158	11		T331	6		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T238	10		T354	4		T355	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T337	13		T356	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T143	1		T307	6		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T158	1		T130	15		T331	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	2		T8	1		T9	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	3		T9	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T178	1		T269	14		T160	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	2		T11	3		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T33	1		T29	16		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T134	10		T126	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	1		T16	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T41	11		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T6	3		T10	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	13		T137	1		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	8		T101	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	7		T23	7		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	12		T30	1		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T125	1		T168	14		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T139	13		T130	11		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T126	1		T208	1		T17	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T2	1		T8	16		T125	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T8	20		T33	2		T14	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T238	4		T354	2		T355	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T337	2		T356	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T143	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T158	11		T331	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	1		T9	4		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	5		T9	11		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T178	5		T269	11		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T125	11		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	12		T29	14		T198	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	9		T139	14		T176	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	10		T159	10		T279	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	2		T41	10		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T6	22		T10	8		T37	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	22		T137	9		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	6		T134	8		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	1		T30	5		T287	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	10		T30	2		T168	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T168	16		T137	10		T139	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T139	15		T277	8		T312	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	2		T35	5		T210	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T125	12		T134	4		T271	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T33	1		T14	1		T127	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	1		T9	5		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	6		T9	12		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T178	6		T198	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	2		T11	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	13		T29	15		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	3		T134	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	23		T41	11		T178	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T101	1		T126	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T137	10		T139	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	7		T5	11		T40	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T33	5		T23	1		T30	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	3		T135	1		T272	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T168	17		T137	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T134	5		T139	16		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T33	2		T168	12		T197	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T125	13		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	1		T135	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T8	1		T271	5		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T14	4		T127	3		T296	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17507	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T158	12		T331	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	13		T146	10		T269	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	2		T9	11		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T198	9		T141	21		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T11	2		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	15		T198	6		T279	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T134	9		T129	11		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T103	28		T136	8		T257	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	12		T41	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	8		T140	7		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T130	12		T98	4		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	7		T5	11		T40	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	3		T23	6		T287	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T135	11		T188	8		T276	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T168	13		T139	7		T256	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T134	3		T139	12		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T33	1		T168	2		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T125	14		T147	11		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T8	19		T135	11		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T8	15		T243	7		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T14	5		T127	11		T74	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T331	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T238	5		T354	6		T355	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T337	3		T356	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T143	11		T307	5		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T158	12		T130	1		T331	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	3		T8	1		T9	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	6		T9	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T178	6		T269	12		T160	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	2		T11	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T33	13		T29	15		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T134	10		T126	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	1		T16	11		T159	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	3		T41	11		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T6	25		T10	9		T37	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	23		T137	10		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	7		T101	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	5		T23	1		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	11		T30	3		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T125	1		T168	17		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T139	16		T130	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T126	1		T208	1		T17	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	1		T8	1		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T8	1		T33	2		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T238	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T337	12		T356	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T307	1		T357	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T130	14		T331	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	13		T146	10		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	2		T9	11		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T269	13		T160	17		T313	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	1		T11	2		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T29	15		T198	6		T141	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T134	9		T253	4		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T279	10		T179	4		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	10		T129	11		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T40	9		T103	28		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	12		T15	1		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	7		T134	8		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	3		T23	6		T287	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	11		T135	11		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T168	13		T139	7		T151	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T139	12		T130	10		T277	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	5		T187	5		T210	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	15		T125	14		T134	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T8	19		T33	1		T14	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3