Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T127	2		T17	3		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	2		T125	13		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	6		T11	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T138	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	2		T135	1		T158	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	3		T8	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T33	13		T101	1		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	5		T30	3		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	11		T168	12		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	7		T8	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T34	4		T197	13		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	4		T30	6		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	5		T126	1		T16	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T29	23		T41	11		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	3		T29	15		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T9	12		T40	11		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T33	5		T125	12		T168	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T2	1		T198	6		T242	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T159	8		T262	6		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	3		T253	4		T274	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T125	14		T127	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T7	2		T11	2		T251	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	15		T140	7		T142	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T135	11		T98	4		T270	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	19		T134	9		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T103	28		T168	11		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T187	5		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	13		T127	11		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	11		T168	2		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	7		T33	1		T146	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T198	9		T147	11		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	5		T134	8		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	3		T16	1		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	12		T41	10		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	15		T135	12		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	11		T40	9		T23	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T33	3		T125	12		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T198	6		T242	11		T264	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T262	1		T265	7		T275	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T175	1		T258	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T266	3		T267	5		T268	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	1		T260	9		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T127	2		T17	3		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	2		T158	12		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	6		T11	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T125	13		T127	12		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	2		T135	1		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T134	10		T178	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T6	25		T10	9		T37	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	3		T8	1		T33	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T127	3		T139	1		T269	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	2		T126	1		T178	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	7		T8	1		T9	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	11		T168	12		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	4		T30	6		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	3		T134	5		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	23		T137	11		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T29	15		T135	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	423	1			T2	1		T9	12		T40	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	5		T125	13		T168	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T267	1		T268	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T17	3		T253	4		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T17	2		T210	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T7	2		T11	2		T274	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T125	14		T127	16		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T135	11		T251	7		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	15		T134	9		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T103	28		T168	11		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	19		T135	11		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T127	11		T269	13		T130	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T35	1		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	7		T9	13		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	11		T168	2		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	5		T134	8		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T134	3		T16	1		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	12		T139	7		T277	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T29	15		T135	12		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T9	11		T40	9		T23	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	3		T125	12		T168	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3