Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22992

1

T1

124

T2

34

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3537

1

T2

1

T5

22

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20445

1

T1

122

T2

34

T3

34

auto[1]

6084

1

T1

2

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	476	1			T1	2		T7	5		T13	1
values[0]	89	1			T198	12		T130	13		T278	1
values[1]	703	1			T7	8		T27	1		T125	27
values[2]	2930	1			T6	25		T10	9		T37	23
values[3]	763	1			T5	22		T8	1		T29	30
values[4]	585	1			T8	20		T11	3		T33	13
values[5]	744	1			T13	3		T271	5		T16	11
values[6]	538	1			T9	23		T33	3		T14	9
values[7]	579	1			T3	3		T8	16		T101	1
values[8]	747	1			T3	14		T7	3		T9	18
values[9]	1343	1			T2	1		T7	3		T33	8
minimum	17032	1			T1	122		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	949	1			T7	8		T27	1		T125	27
values[1]	2963	1			T6	25		T10	9		T37	23
values[2]	753	1			T8	21		T23	7		T29	30
values[3]	527	1			T5	22		T11	3		T33	13
values[4]	717	1			T9	23		T13	3		T147	21
values[5]	577	1			T8	16		T33	3		T101	1
values[6]	726	1			T3	3		T13	2		T30	6
values[7]	577	1			T2	1		T3	14		T7	3
values[8]	1060	1			T7	3		T33	8		T29	35
values[9]	172	1			T17	4		T251	15		T187	15
minimum	17508	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T7	3		T125	15		T135	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T27	1		T135	12		T168	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T6	3		T10	1		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T134	10		T138	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	1		T23	7		T41	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	20		T29	16		T134	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	3		T33	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	12		T40	10		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	12		T279	11		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	2		T147	12		T160	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	16		T33	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	8		T30	1		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T30	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T168	14		T146	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	8		T7	2		T9	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T128	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T126	1		T127	17		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	2		T33	7		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T251	15		T143	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T17	3		T187	15		T253	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17372	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	5		T125	12		T277	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T168	16		T178	10		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T6	22		T10	8		T37	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T134	9		T34	1		T176	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	10		T137	10		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T29	14		T134	4		T178	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T33	12		T142	2		T280	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	10		T40	10		T16	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	11		T279	11		T250	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T147	9		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T33	1		T271	4		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	1		T30	2		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	2		T30	5		T127	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T168	16		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	6		T7	1		T9	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T140	7		T281	9		T171	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T127	11		T158	11		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T7	1		T33	1		T29	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T143	2		T235	3		T282	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T17	1		T253	7		T124	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	1		T33	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T1	2		T7	5		T13	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T283	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T198	7		T130	13		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T278	1		T285	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	3		T125	15		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	1		T176	1		T160	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T6	3		T10	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	10		T135	12		T168	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	1		T41	11		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	12		T29	16		T134	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	3		T33	1		T23	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	20		T40	10		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T271	1		T133	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	2		T16	1		T210	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	12		T33	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	8		T30	1		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T8	16		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T168	14		T146	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	8		T7	2		T9	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T129	12		T139	2		T269	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T126	1		T127	17		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T2	1		T7	2		T33	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16901	1			T1	122		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T198	5		T284	12		T286	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T285	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	5		T125	12		T277	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T176	2		T160	10		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T6	22		T10	8		T37	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T134	9		T168	16		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	10		T137	10		T197	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	10		T29	14		T134	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T33	12		T210	2		T279	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	10		T178	5		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T271	4		T250	1		T142	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T16	10		T236	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T9	11		T33	1		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	1		T30	2		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T30	5		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T13	1		T168	16		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	6		T7	1		T9	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T129	10		T139	14		T269	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T127	11		T272	6		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T7	1		T33	1		T29	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T7	6		T125	13		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T27	1		T135	1		T168	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T6	25		T10	9		T37	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	10		T138	1		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	1		T23	1		T41	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	1		T29	15		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	1		T33	13		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	11		T40	11		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	12		T279	12		T250	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	2		T147	10		T160	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T33	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	4		T30	3		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	3		T30	6		T127	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	2		T168	17		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	7		T7	2		T9	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T128	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T126	1		T127	12		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T7	3		T33	5		T29	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T251	1		T143	3		T235	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T17	2		T187	1		T253	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17502	1			T1	124		T2	34		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	2		T125	14		T135	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	11		T168	11		T160	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T103	28		T136	8		T257	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T134	9		T35	1		T287	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T23	6		T41	10		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	19		T29	15		T134	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T11	2		T142	15		T256	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	11		T40	9		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	11		T279	10		T94	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T147	11		T160	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	15		T33	1		T242	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	5		T127	11		T242	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	1		T139	7		T288	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T168	13		T146	8		T129	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	7		T7	1		T9	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	14		T140	7		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T127	16		T139	12		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T33	3		T29	12		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T251	14		T282	8		T289	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T17	2		T187	14		T253	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T198	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T1	2		T7	5		T13	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T198	6		T130	1		T284	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T278	1		T285	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	6		T125	13		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T27	1		T176	3		T160	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T6	25		T10	9		T37	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T134	10		T135	1		T168	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T41	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	11		T29	15		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	1		T33	13		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T40	11		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T271	5		T133	1		T250	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	2		T16	11		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	12		T33	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	4		T30	3		T127	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	3		T8	1		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	2		T168	17		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	7		T7	2		T9	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T129	11		T139	16		T269	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T126	1		T127	12		T272	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	477	1			T2	1		T7	3		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17032	1			T1	122		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T198	6		T130	12		T286	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T285	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	2		T125	14		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T160	8		T188	8		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T103	28		T136	8		T257	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T134	9		T135	11		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T41	10		T146	10		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	11		T29	15		T134	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T11	2		T23	6		T279	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	19		T40	9		T135	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	15		T94	2		T290	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T210	2		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	11		T33	1		T242	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	5		T127	11		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	15		T288	10		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T168	13		T146	8		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	7		T7	1		T9	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	11		T269	13		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T127	16		T139	12		T251	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T33	3		T29	12		T134	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3