Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20743

1

T1

124

T2

34

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

5786

1

T2

1

T3

3

T6

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20928

1

T1

124

T2

34

T3

34

auto[1]

5601

1

T2

1

T3

3

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T259	8		T291	17		-	-
values[0]	71	1			T178	6		T188	22		T292	1
values[1]	697	1			T30	3		T138	2		T272	7
values[2]	712	1			T2	1		T3	14		T7	3
values[3]	431	1			T8	21		T13	2		T29	30
values[4]	725	1			T7	3		T8	16		T33	8
values[5]	779	1			T7	8		T14	9		T127	28
values[6]	717	1			T30	6		T125	27		T126	1
values[7]	764	1			T5	22		T33	13		T101	1
values[8]	688	1			T9	23		T11	3		T23	7
values[9]	3424	1			T3	3		T6	25		T9	18
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	920	1			T2	1		T29	35		T127	2
values[1]	2895	1			T3	14		T6	25		T7	3
values[2]	493	1			T7	3		T8	21		T33	8
values[3]	756	1			T8	16		T27	1		T126	1
values[4]	762	1			T7	8		T40	20		T14	9
values[5]	631	1			T101	1		T30	6		T125	27
values[6]	845	1			T5	22		T33	13		T134	19
values[7]	677	1			T9	23		T11	3		T23	7
values[8]	831	1			T9	18		T33	3		T13	3
values[9]	212	1			T3	3		T135	12		T138	1
minimum	17507	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T168	3		T197	1		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T29	13		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	8		T139	13		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1596	1			T6	3		T7	2		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	2		T8	21		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	7		T13	1		T134	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	16		T27	1		T271	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T126	1		T137	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	3		T127	17		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	10		T14	8		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T101	1		T30	1		T129	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T125	15		T126	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	12		T33	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T168	26		T176	1		T177	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	3		T23	7		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	12		T125	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	2		T125	13		T146	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	14		T13	2		T135	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T135	12		T287	10		T293	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T3	1		T138	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T30	1		T183	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T168	11		T197	12		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T29	22		T127	1		T178	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	6		T139	15		T250	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1027	1			T6	22		T7	1		T10	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	1		T134	8		T158	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T33	1		T13	1		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T271	4		T16	4		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	9		T15	1		T269	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	5		T127	11		T139	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	10		T14	1		T198	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T30	5		T129	10		T210	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T125	12		T34	1		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	10		T33	12		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T168	32		T176	11		T177	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T159	7		T147	9		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	11		T279	11		T294	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T33	1		T125	11		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	4		T13	1		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T287	12		T293	9		T295	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T3	2		T159	10		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T30	2		T183	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T259	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T291	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T93	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T178	1		T188	9		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T197	1		T208	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	1		T138	2		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	8		T168	3		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T7	2		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	21		T134	9		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	1		T29	16		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	2		T8	16		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	7		T40	10		T134	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	3		T127	17		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	8		T137	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	1		T126	1		T129	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T125	15		T34	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	12		T33	1		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T126	1		T168	14		T177	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	3		T23	7		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	12		T125	1		T168	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T33	2		T125	13		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1705	1			T3	1		T6	3		T9	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T178	5		T188	13		T264	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T197	12		T139	14		T242	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	2		T272	6		T150	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	6		T168	11		T16	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T29	22		T127	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	8		T210	2		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T13	1		T29	14		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T271	4		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	1		T40	10		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	5		T127	11		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	1		T137	9		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	5		T129	10		T139	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T125	12		T34	1		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	10		T33	12		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T168	16		T177	11		T294	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T159	7		T147	9		T297	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	11		T168	16		T176	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T33	1		T125	11		T287	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1174	1			T3	2		T6	22		T9	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T168	12		T197	13		T16	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	1		T29	23		T127	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	7		T139	16		T250	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1379	1			T6	25		T7	3		T10	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	2		T8	2		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T33	5		T13	2		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T27	1		T271	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T126	1		T137	10		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	6		T127	12		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T40	11		T14	4		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T101	1		T30	6		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	13		T126	1		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	11		T33	13		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T168	34		T176	12		T177	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	1		T23	1		T159	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	12		T125	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	2		T125	12		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	5		T13	2		T135	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T135	1		T287	13		T293	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T3	3		T138	1		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T30	3		T183	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T168	2		T242	11		T298	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	12		T198	6		T130	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T3	7		T139	12		T249	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1244	1			T29	15		T103	28		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T8	19		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T33	3		T134	3		T41	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	15		T16	1		T251	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T269	13		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	2		T127	16		T139	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	9		T14	5		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	11		T210	14		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T125	14		T17	3		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	11		T134	9		T243	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T168	24		T177	8		T299	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T23	6		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	11		T279	10		T281	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	1		T125	12		T146	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	13		T13	1		T135	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T135	11		T287	9		T293	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T237	6		T155	11		T300	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T259	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T291	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T93	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T178	6		T188	14		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T197	13		T208	1		T139	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	3		T138	2		T272	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	7		T168	12		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T7	3		T29	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	2		T134	9		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	2		T29	15		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	2		T8	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T33	5		T40	11		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	6		T127	12		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	4		T137	10		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	6		T126	1		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	13		T34	4		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	11		T33	13		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T126	1		T168	17		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T23	1		T159	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	12		T125	1		T168	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T33	2		T125	12		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1537	1			T3	3		T6	25		T9	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T259	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T188	8		T264	11		T301	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T242	11		T298	12		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	12		T187	5		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	7		T168	2		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	12		T127	11		T198	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T8	19		T134	8		T142	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T29	15		T146	10		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T8	15		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	3		T40	9		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	2		T127	16		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	5		T15	1		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T129	11		T139	7		T210	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T125	14		T17	3		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	11		T134	9		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T168	13		T177	8		T294	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	2		T23	6		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	11		T168	11		T279	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T33	1		T125	12		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1342	1			T9	13		T13	1		T103	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3