Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22744

1

T1

124

T2

34

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3785

1

T2

1

T5

22

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20408

1

T1

122

T2

34

T3

34

auto[1]

6121

1

T1

2

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	733	1			T1	2		T7	5		T13	1
values[0]	25	1			T198	12		T284	13		-	-
values[1]	747	1			T7	8		T27	1		T125	27
values[2]	2955	1			T6	25		T10	9		T37	23
values[3]	731	1			T5	22		T8	1		T29	30
values[4]	662	1			T8	20		T11	3		T33	13
values[5]	685	1			T9	23		T13	3		T271	5
values[6]	532	1			T33	3		T101	1		T14	9
values[7]	639	1			T3	3		T8	16		T13	2
values[8]	724	1			T3	14		T7	3		T9	18
values[9]	1064	1			T2	1		T7	3		T33	8
minimum	17032	1			T1	122		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T7	8		T27	1		T135	25
values[1]	2976	1			T6	25		T10	9		T37	23
values[2]	765	1			T5	22		T8	21		T23	7
values[3]	629	1			T11	3		T33	13		T40	20
values[4]	618	1			T9	23		T13	3		T271	5
values[5]	607	1			T8	16		T33	3		T101	1
values[6]	701	1			T3	3		T13	2		T30	6
values[7]	610	1			T2	1		T3	14		T7	3
values[8]	1062	1			T7	3		T33	8		T29	35
values[9]	137	1			T17	4		T187	15		T143	3
minimum	17806	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	3		T135	13		T187	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	1		T135	12		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T6	3		T10	1		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	10		T168	12		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	1		T23	7		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	12		T8	20		T29	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	3		T131	1		T160	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	1		T40	10		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	12		T238	10		T94	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	2		T271	1		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	16		T33	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	1		T126	1		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T30	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T168	14		T146	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	8		T7	2		T9	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T208	1		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	2		T29	13		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T33	7		T134	9		T126	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T143	1		T235	1		T302	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T17	3		T187	15		T282	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17461	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T160	9		T188	9		T141	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	5		T277	8		T273	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T178	10		T276	15		T281	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T6	22		T10	8		T37	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	9		T168	16		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T178	5		T137	10		T177	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	10		T29	14		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T160	2		T303	4		T304	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T33	12		T40	10		T16	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	11		T238	4		T94	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T271	4		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T33	1		T14	1		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	2		T127	2		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	2		T30	5		T127	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T168	16		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	6		T7	1		T9	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T140	7		T270	3		T281	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T29	22		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T33	1		T134	8		T127	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T143	2		T235	3		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T17	1		T282	6		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T160	10		T188	13		T150	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	493	1			T1	2		T7	5		T13	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T187	15		T305	1		T151	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T198	7		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	3		T125	15		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T27	1		T130	13		T160	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T6	3		T10	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T134	10		T135	12		T168	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	1		T146	11		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	12		T29	16		T134	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	3		T23	7		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	20		T33	1		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	12		T94	3		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	2		T271	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T33	2		T101	1		T14	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	1		T127	12		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	1		T8	16		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T126	1		T168	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	8		T7	2		T9	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T129	12		T269	14		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	2		T29	13		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T2	1		T33	7		T134	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16901	1			T1	122		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T22	3		T306	6		T174	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T305	13		T273	11		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T198	5		T284	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	5		T125	12		T176	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T160	10		T188	13		T150	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T6	22		T10	8		T37	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	9		T168	16		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T137	10		T197	2		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	10		T29	14		T134	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T178	5		T160	2		T189	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	12		T40	10		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	11		T94	13		T308	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T271	4		T16	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T33	1		T14	1		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	2		T127	2		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	2		T30	5		T127	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	1		T168	16		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	6		T7	1		T9	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T129	10		T269	11		T176	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	1		T29	22		T272	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T33	1		T134	8		T127	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	6		T135	1		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T27	1		T135	1		T178	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T6	25		T10	9		T37	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	10		T168	17		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T23	1		T178	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	11		T8	1		T29	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T131	1		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T33	13		T40	11		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	12		T238	5		T94	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	2		T271	5		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T33	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	3		T126	1		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	3		T30	6		T127	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	2		T168	17		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	7		T7	2		T9	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	1		T208	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	3		T29	23		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T33	5		T134	9		T126	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T143	3		T235	4		T302	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T17	2		T187	1		T282	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17596	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T160	11		T188	14		T141	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	2		T135	12		T187	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T135	11		T130	12		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T103	28		T136	8		T257	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	9		T168	11		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	6		T146	10		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	11		T8	19		T29	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	2		T160	17		T256	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	9		T135	11		T279	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	11		T238	9		T94	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T147	11		T210	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	15		T33	1		T14	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T127	11		T242	11		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	1		T139	7		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T168	13		T146	8		T129	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	7		T7	1		T9	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	14		T140	7		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	12		T139	12		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T33	3		T134	8		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T289	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T17	2		T187	14		T282	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T125	14		T198	6		T254	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T160	8		T188	8		T141	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	502	1			T1	2		T7	5		T13	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T187	1		T305	14		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T198	6		T284	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	6		T125	13		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T27	1		T130	1		T160	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T6	25		T10	9		T37	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	10		T135	1		T168	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	1		T146	1		T137	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	11		T29	15		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	1		T23	1		T178	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T33	13		T40	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	12		T94	14		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	2		T271	5		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T33	2		T101	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	3		T127	3		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	3		T8	1		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	2		T126	1		T168	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	7		T7	2		T9	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T129	11		T269	12		T176	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	3		T29	23		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T2	1		T33	5		T134	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17032	1			T1	122		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T179	3		T22	4		T268	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T187	14		T151	9		T273	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T198	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T125	14		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	12		T160	8		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T103	28		T136	8		T257	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T134	9		T135	11		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	10		T177	8		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	11		T29	15		T134	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T23	6		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	19		T40	9		T135	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	11		T94	2		T309	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T210	2		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T33	1		T14	5		T242	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T127	11		T147	11		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	15		T151	14		T98	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T168	13		T146	8		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	7		T7	1		T9	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	11		T269	13		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	12		T139	12		T251	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T33	3		T134	8		T127	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3