Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23044

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3485

1

T7

14

T8

21

T11

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20529

1

T1

124

T2

34

T3

23

auto[1]

6000

1

T2

1

T3

14

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	183	1			T13	2		T126	1		T178	11
values[0]	6	1			T133	1		T246	1		T22	4
values[1]	775	1			T2	1		T8	1		T11	3
values[2]	830	1			T3	3		T7	3		T8	20
values[3]	626	1			T9	23		T33	8		T178	6
values[4]	631	1			T134	8		T146	9		T138	1
values[5]	660	1			T23	7		T29	35		T125	1
values[6]	791	1			T3	14		T5	22		T7	8
values[7]	663	1			T7	3		T33	3		T30	6
values[8]	2916	1			T6	25		T8	16		T10	9
values[9]	952	1			T135	12		T126	1		T16	8
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	788	1			T2	1		T8	1		T11	3
values[1]	734	1			T3	3		T7	3		T8	20
values[2]	748	1			T9	23		T33	8		T178	6
values[3]	531	1			T134	25		T168	28		T146	9
values[4]	687	1			T3	14		T7	8		T23	7
values[5]	750	1			T5	22		T40	20		T27	1
values[6]	2985	1			T6	25		T7	3		T9	18
values[7]	629	1			T8	16		T129	22		T139	29
values[8]	888	1			T13	2		T135	12		T126	2
values[9]	92	1			T188	1		T238	14		T94	16
minimum	17697	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T33	1		T125	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T11	3		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T14	8		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	2		T8	20		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	12		T33	7		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T178	1		T158	1		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T134	9		T146	9		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	4		T168	12		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	8		T29	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	3		T23	7		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	12		T27	1		T168	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	10		T128	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T6	3		T9	14		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	2		T33	2		T135	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	16		T129	12		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	1		T132	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	1		T135	12		T126	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T178	1		T16	4		T198	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T238	10		T94	3		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T188	1		T310	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17427	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T259	7		T311	12		T309	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	12		T125	11		T137	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	1		T125	12		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	2		T14	1		T271	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T134	9		T41	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	11		T33	1		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T178	5		T158	2		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T134	8		T158	3		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T134	4		T168	16		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	6		T29	22		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	5		T127	11		T168	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	10		T168	11		T272	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	10		T312	9		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T6	22		T9	4		T10	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	1		T33	1		T177	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T129	10		T139	6		T159	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T139	14		T242	8		T236	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	1		T243	9		T198	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T178	10		T16	4		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T238	4		T94	13		T303	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T311	14		T286	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T13	1		T126	1		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T178	1		T188	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T133	1		T22	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T33	1		T29	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T11	3		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T14	8		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	2		T8	20		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	12		T33	7		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T178	1		T158	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	9		T34	3		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	4		T138	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	13		T134	9		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	7		T125	1		T127	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	8		T5	12		T9	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	3		T40	10		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	1		T146	11		T250	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	2		T33	2		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T6	3		T8	16		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T135	13		T138	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T135	12		T126	1		T243	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T16	4		T139	1		T198	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T13	1		T290	10		T265	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T178	10		T152	11		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T33	12		T29	14		T125	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T125	12		T127	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	2		T14	1		T271	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T134	9		T41	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	11		T33	1		T16	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T178	5		T158	2		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T34	1		T158	3		T210	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	4		T147	9		T253	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T29	22		T134	8		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T127	11		T168	32		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	6		T5	10		T9	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	5		T40	10		T312	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	5		T249	11		T296	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T33	1		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T6	22		T10	8		T37	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T242	8		T236	9		T277	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T243	9		T198	5		T238	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	4		T139	14		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	1		T33	13		T125	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T11	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	3		T14	4		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	3		T8	1		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	12		T33	5		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T178	6		T158	3		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T134	9		T146	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T134	5		T168	17		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	7		T29	23		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	6		T23	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	11		T27	1		T168	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	11		T128	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T6	25		T9	5		T10	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	2		T33	2		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T129	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	15		T132	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T13	2		T135	1		T126	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T178	11		T16	7		T198	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T238	5		T94	14		T303	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T188	1		T310	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17584	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T259	1		T311	15		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T125	12		T15	1		T298	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	2		T13	1		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	5		T251	14		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	19		T134	9		T41	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	11		T33	3		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	3		T130	14		T251	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T134	8		T146	8		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	3		T168	11		T130	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	7		T29	12		T160	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	2		T23	6		T127	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	11		T168	2		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	9		T313	10		T312	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T9	13		T103	28		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T33	1		T135	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	15		T129	11		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T242	11		T236	7		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T135	11		T243	7		T198	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T198	9		T187	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T238	9		T94	2		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T74	12		T314	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T29	15		T297	4		T315	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T259	6		T311	11		T309	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T13	2		T126	1		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T178	11		T188	1		T152	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T133	1		T22	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	1		T33	13		T29	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T11	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	3		T14	4		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	3		T8	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	12		T33	5		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T178	6		T158	3		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T146	1		T34	4		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	5		T138	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T29	23		T134	9		T197	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T23	1		T125	1		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	7		T5	11		T9	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	6		T40	11		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	6		T146	1		T250	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	2		T33	2		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T6	25		T8	1		T10	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T135	1		T138	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T135	1		T126	1		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T16	7		T139	15		T198	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T290	10		T265	3		T268	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T171	8		T316	8		T74	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T22	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	15		T125	12		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	2		T13	1		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	5		T251	14		T274	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	19		T134	9		T41	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	11		T33	3		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	3		T130	14		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T146	8		T210	14		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	3		T130	12		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T29	12		T134	8		T189	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T23	6		T127	16		T168	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	7		T5	11		T9	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	2		T40	9		T313	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	10		T250	9		T249	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T33	1		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T8	15		T103	28		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T135	12		T242	11		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T135	11		T243	7		T198	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	1		T198	9		T187	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3