Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23213

1

T1

124

T2

35

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3316

1

T7

3

T8

16

T9

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20646

1

T1

124

T2

35

T3

37

auto[1]

5883

1

T5

22

T6

25

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T179	4		T326	12		-	-
values[0]	74	1			T3	3		T127	2		T155	29
values[1]	646	1			T7	3		T30	3		T126	1
values[2]	2796	1			T2	1		T6	25		T8	16
values[3]	730	1			T125	1		T168	28		T178	6
values[4]	897	1			T8	1		T13	2		T29	30
values[5]	531	1			T8	20		T40	20		T23	7
values[6]	526	1			T7	11		T11	3		T33	24
values[7]	835	1			T3	14		T29	35		T30	6
values[8]	653	1			T9	18		T125	24		T134	19
values[9]	1329	1			T5	22		T9	23		T101	1
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	818	1			T3	3		T7	3		T30	3
values[1]	2839	1			T2	1		T6	25		T8	16
values[2]	772	1			T13	2		T125	1		T135	12
values[3]	731	1			T8	1		T40	20		T29	30
values[4]	640	1			T8	20		T11	3		T135	13
values[5]	654	1			T7	11		T33	24		T13	3
values[6]	637	1			T3	14		T30	6		T125	24
values[7]	756	1			T9	18		T135	12		T126	1
values[8]	891	1			T101	1		T14	9		T125	27
values[9]	275	1			T5	22		T9	23		T17	4
minimum	17516	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T30	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	2		T127	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T2	1		T6	3		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	16		T27	1		T253	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T125	1		T135	12		T168	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T16	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T40	10		T242	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	16		T138	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	20		T11	3		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T168	3		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	5		T33	9		T23	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T33	1		T13	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T125	13		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T41	11		T129	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T137	1		T139	8		T243	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	14		T135	12		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T14	8		T134	23		T127	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T101	1		T125	15		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T5	12		T94	11		T327	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T9	12		T17	3		T160	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T177	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T30	2		T168	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T127	1		T139	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T6	22		T10	8		T37	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T253	7		T263	15		T311	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T168	16		T178	5		T35	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T16	4		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	10		T242	8		T270	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T29	14		T15	1		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	10		T159	10		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T168	11		T328	13		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	6		T33	2		T29	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T33	12		T13	1		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	6		T125	11		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	5		T41	10		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	9		T139	6		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	4		T210	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T134	21		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T125	12		T158	13		T238	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T5	10		T94	9		T327	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T9	11		T17	1		T160	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T177	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T179	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T326	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T3	1		T155	12		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T127	1		T286	11		T329	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	1		T126	1		T168	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	2		T128	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T2	1		T6	3		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	16		T27	1		T249	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T125	1		T168	12		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T131	1		T147	12		T141	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	1		T135	25		T256	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	1		T29	16		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	20		T40	10		T23	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T168	3		T138	1		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	5		T11	3		T33	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T33	1		T13	2		T198	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	8		T29	13		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	1		T41	11		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T125	13		T134	10		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	14		T135	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T5	12		T14	8		T134	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T9	12		T101	1		T125	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	2		T155	17		T213	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T127	1		T286	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T30	2		T168	16		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T139	14		T177	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T6	22		T10	8		T37	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T249	11		T311	14		T288	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T168	16		T178	5		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T147	9		T153	21		T263	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T312	9		T254	1		T241	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	1		T29	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	10		T16	10		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T168	11		T198	2		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	6		T33	2		T197	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T33	12		T13	1		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	6		T29	22		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	5		T41	10		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T125	11		T134	9		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	4		T250	9		T189	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	10		T14	1		T134	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	11		T125	12		T158	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	3		T30	3		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T7	3		T127	2		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	1		T6	25		T10	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	1		T27	1		T253	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T125	1		T135	1		T168	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	2		T16	7		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	1		T40	11		T242	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T29	15		T138	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T11	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T168	12		T208	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	8		T33	7		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T33	13		T13	2		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	7		T125	12		T178	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	6		T41	11		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T137	10		T139	7		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	5		T135	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	4		T134	24		T127	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T101	1		T125	13		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	11		T94	10		T327	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T9	12		T17	2		T160	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T177	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T168	13		T141	21		T270	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T251	7		T249	10		T254	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T103	28		T136	8		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	15		T253	4		T170	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T135	11		T168	11		T146	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T147	11		T287	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	9		T242	11		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	15		T15	1		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	19		T11	2		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T168	2		T313	10		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	3		T33	4		T23	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	1		T198	6		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	7		T125	12		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	10		T129	11		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	7		T243	7		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	13		T135	11		T210	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	5		T134	20		T127	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T125	14		T187	14		T238	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T5	11		T94	10		T330	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T9	11		T17	2		T160	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T177	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T179	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T3	3		T155	18		T213	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T127	2		T286	11		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	3		T126	1		T168	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	3		T128	1		T139	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T2	1		T6	25		T10	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T27	1		T249	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T125	1		T168	17		T178	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T131	1		T147	10		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	1		T135	2		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	2		T29	15		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T40	11		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T168	12		T138	1		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	8		T11	1		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T33	13		T13	2		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T3	7		T29	23		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	6		T41	11		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T125	12		T134	10		T178	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	5		T135	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T5	11		T14	4		T134	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T9	12		T101	1		T125	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T179	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T326	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T155	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T286	10		T329	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T168	13		T141	21		T270	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T251	7		T177	8		T253	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T103	28		T136	8		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	15		T249	10		T311	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T168	11		T146	8		T269	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T147	11		T141	19		T170	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T135	23		T256	12		T312	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	15		T15	1		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	19		T40	9		T23	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T168	2		T198	9		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	3		T11	2		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T13	1		T198	6		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	7		T29	12		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	10		T129	11		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T125	12		T134	9		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	13		T135	11		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	11		T14	5		T134	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T9	11		T125	14		T17	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3