Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26529

1

T1

124

T2

35

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22947

1

T1

124

T2

35

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3582

1

T3

3

T7

11

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20736

1

T1

124

T2

34

T3

37

auto[1]

5793

1

T2

1

T5

22

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22531

1

T1

124

T2

34

T3

29

auto[1]

3998

1

T2

1

T3

8

T5

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T2	1		T242	20		T150	25
values[0]	26	1			T130	15		T331	9		T332	1
values[1]	607	1			T7	8		T8	1		T9	41
values[2]	637	1			T7	6		T11	3		T27	1
values[3]	813	1			T33	13		T29	30		T134	19
values[4]	691	1			T3	3		T41	21		T178	11
values[5]	2973	1			T6	25		T10	9		T37	23
values[6]	627	1			T3	14		T5	22		T33	8
values[7]	711	1			T30	3		T125	1		T135	12
values[8]	591	1			T33	3		T126	1		T208	1
values[9]	1130	1			T8	36		T14	9		T125	27
minimum	17496	1			T1	124		T2	34		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	590	1			T7	11		T8	1		T9	41
values[1]	762	1			T7	3		T11	3		T178	6
values[2]	793	1			T3	3		T33	13		T29	30
values[3]	2857	1			T6	25		T10	9		T37	23
values[4]	667	1			T101	1		T40	20		T126	1
values[5]	698	1			T3	14		T5	22		T33	8
values[6]	637	1			T30	3		T135	12		T168	30
values[7]	691	1			T33	3		T134	8		T126	1
values[8]	949	1			T2	1		T8	20		T125	27
values[9]	188	1			T8	16		T14	9		T127	14
minimum	17697	1			T1	124		T2	34		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

4092

1

T3

7

T5

11

T7

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T9	14		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	5		T9	12		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	2		T178	1		T198	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	3		T128	1		T208	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T33	1		T29	16		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T134	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T6	3		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	13		T41	11		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T101	1		T40	10		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T139	1		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	8		T5	12		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	7		T23	7		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	1		T135	12		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T168	14		T137	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T134	4		T139	13		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T33	2		T126	1		T168	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T125	15		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T8	20		T135	12		T127	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T8	16		T271	1		T243	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	8		T127	12		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17407	1			T1	124		T2	33		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T13	2		T158	1		T130	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	4		T13	1		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	6		T9	11		T125	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T178	5		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T176	13		T177	11		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	12		T29	14		T198	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	2		T134	9		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T6	22		T10	8		T37	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	22		T41	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	10		T158	2		T159	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T137	9		T98	4		T270	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	6		T5	10		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	1		T30	5		T287	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T272	6		T188	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T168	16		T137	10		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	4		T139	15		T277	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T33	1		T168	11		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T125	12		T34	1		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T127	11		T197	2		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T271	4		T243	9		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T14	1		T127	2		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T33	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T13	1		T158	11		T211	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T2	1		T333	2		T152	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T242	12		T150	13		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T332	1		T334	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T130	15		T331	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T9	14		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T9	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	2		T178	1		T198	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	2		T11	3		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T33	1		T29	16		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	10		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T178	1		T138	1		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T41	11		T129	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T6	3		T10	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	13		T137	1		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	8		T5	12		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	7		T23	7		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T30	1		T135	12		T168	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T125	1		T168	14		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T139	13		T130	11		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T33	2		T126	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	16		T125	15		T134	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T8	20		T14	8		T135	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17365	1			T1	124		T2	33		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T152	2		T335	10		T336	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T242	8		T150	12		T296	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T331	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	4		T13	1		T127	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	5		T9	11		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T7	1		T178	5		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T125	11		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	12		T29	14		T198	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T134	9		T139	14		T176	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T178	10		T16	10		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	2		T41	10		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T6	22		T10	8		T37	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	22		T137	9		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	6		T5	10		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T33	1		T30	5		T287	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	2		T168	16		T272	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T168	16		T137	10		T139	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T139	15		T277	8		T322	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T33	1		T17	2		T35	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T125	12		T134	4		T271	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	1		T127	13		T168	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T33	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	1		T9	5		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	8		T9	12		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	3		T178	6		T198	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	1		T128	1		T208	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T33	13		T29	15		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	3		T134	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T6	25		T10	9		T37	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	23		T41	11		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T101	1		T40	11		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T137	10		T139	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	7		T5	11		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T33	5		T23	1		T30	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	3		T135	1		T272	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T168	17		T137	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T134	5		T139	16		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T33	2		T126	1		T168	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T125	13		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T8	1		T135	1		T127	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T8	1		T271	5		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T14	4		T127	3		T296	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17543	1			T1	124		T2	34		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	2		T158	12		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	13		T146	10		T160	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	3		T9	11		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T198	9		T269	13		T142	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	2		T177	8		T160	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	15		T198	6		T279	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T134	9		T129	11		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T103	28		T136	8		T257	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	12		T41	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T40	9		T146	8		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T130	12		T35	1		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	7		T5	11		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T33	3		T23	6		T287	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T135	11		T188	8		T276	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T168	13		T139	7		T151	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T134	3		T139	12		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T33	1		T168	2		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T125	14		T147	11		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	19		T135	11		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T8	15		T243	7		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T14	5		T127	11		T337	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T250	9		T94	2		T307	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	1		T130	14		T211	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T2	1		T333	2		T152	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T242	9		T150	13		T296	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T332	1		T334	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T130	1		T331	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	1		T9	5		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	6		T9	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	3		T178	6		T198	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	2		T11	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T33	13		T29	15		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T134	10		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T178	11		T138	1		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	3		T41	11		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T6	25		T10	9		T37	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	23		T137	10		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	7		T5	11		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	5		T23	1		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	3		T135	1		T168	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T125	1		T168	17		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T139	16		T130	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T33	2		T126	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T8	1		T125	13		T134	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T8	1		T14	4		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	124		T2	34		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T152	9		T318	11		T335	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T242	11		T150	12		T325	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T130	14		T331	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	13		T146	10		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	2		T9	11		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T198	9		T269	13		T160	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	1		T11	2		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T29	15		T198	6		T141	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	9		T253	4		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T279	10		T179	4		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	10		T129	11		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T40	9		T103	28		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	12		T15	1		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	7		T5	11		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T33	3		T23	6		T287	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T135	11		T168	11		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T168	13		T139	7		T151	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T139	12		T130	10		T277	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	1		T17	5		T187	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	15		T125	14		T134	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T8	19		T14	5		T135	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22437

1

T1

124

T2

35

T3

30

auto[1]

auto[0]

4092

1

T3

7

T5

11

T7

3