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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.54


Total test records in report: 920
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T795 /workspace/coverage/default/19.adc_ctrl_fsm_reset.3292748720 Jul 28 06:43:33 PM PDT 24 Jul 28 06:50:59 PM PDT 24 125452907956 ps
T796 /workspace/coverage/default/12.adc_ctrl_alert_test.1960062969 Jul 28 06:41:41 PM PDT 24 Jul 28 06:41:42 PM PDT 24 468493051 ps
T216 /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3951480861 Jul 28 06:43:31 PM PDT 24 Jul 28 06:45:24 PM PDT 24 82758552303 ps
T797 /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1646805530 Jul 28 06:45:59 PM PDT 24 Jul 28 06:49:28 PM PDT 24 595147840317 ps
T798 /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2258686165 Jul 28 06:47:31 PM PDT 24 Jul 28 06:50:41 PM PDT 24 165136900397 ps
T79 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2351410045 Jul 28 07:33:59 PM PDT 24 Jul 28 07:34:00 PM PDT 24 407967694 ps
T799 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2680357699 Jul 28 07:33:53 PM PDT 24 Jul 28 07:33:54 PM PDT 24 461775839 ps
T44 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3055063647 Jul 28 07:34:30 PM PDT 24 Jul 28 07:34:40 PM PDT 24 4020731406 ps
T800 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3438214190 Jul 28 07:34:39 PM PDT 24 Jul 28 07:34:40 PM PDT 24 511372763 ps
T119 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2994878294 Jul 28 07:34:10 PM PDT 24 Jul 28 07:34:12 PM PDT 24 416269926 ps
T801 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.194548810 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:30 PM PDT 24 505062802 ps
T120 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3234408554 Jul 28 07:34:24 PM PDT 24 Jul 28 07:34:26 PM PDT 24 523370097 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1767520287 Jul 28 07:34:30 PM PDT 24 Jul 28 07:34:31 PM PDT 24 338431319 ps
T52 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.511996624 Jul 28 07:34:37 PM PDT 24 Jul 28 07:34:39 PM PDT 24 566518971 ps
T80 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2534238320 Jul 28 07:34:41 PM PDT 24 Jul 28 07:34:43 PM PDT 24 443055666 ps
T123 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2778063809 Jul 28 07:33:53 PM PDT 24 Jul 28 07:33:57 PM PDT 24 1136895087 ps
T45 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3187867248 Jul 28 07:33:51 PM PDT 24 Jul 28 07:33:55 PM PDT 24 5304861200 ps
T53 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3899342334 Jul 28 07:34:40 PM PDT 24 Jul 28 07:34:42 PM PDT 24 683657362 ps
T803 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3987266489 Jul 28 07:34:38 PM PDT 24 Jul 28 07:34:39 PM PDT 24 549041521 ps
T804 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1578354062 Jul 28 07:34:38 PM PDT 24 Jul 28 07:34:39 PM PDT 24 427533843 ps
T121 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.95239508 Jul 28 07:34:11 PM PDT 24 Jul 28 07:34:12 PM PDT 24 525135798 ps
T61 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1169147184 Jul 28 07:34:28 PM PDT 24 Jul 28 07:34:29 PM PDT 24 439687767 ps
T48 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1563357766 Jul 28 07:33:54 PM PDT 24 Jul 28 07:34:04 PM PDT 24 4106683176 ps
T805 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2033389997 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:46 PM PDT 24 348312315 ps
T58 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3467158577 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:32 PM PDT 24 517287956 ps
T59 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3939595911 Jul 28 07:34:15 PM PDT 24 Jul 28 07:34:17 PM PDT 24 808432177 ps
T107 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4202435310 Jul 28 07:34:13 PM PDT 24 Jul 28 07:34:14 PM PDT 24 529022447 ps
T806 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2861791000 Jul 28 07:34:18 PM PDT 24 Jul 28 07:34:19 PM PDT 24 488674872 ps
T60 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3611061121 Jul 28 07:34:28 PM PDT 24 Jul 28 07:34:32 PM PDT 24 547513828 ps
T807 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.45863257 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:47 PM PDT 24 319462939 ps
T47 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1789786834 Jul 28 07:33:52 PM PDT 24 Jul 28 07:33:54 PM PDT 24 533762525 ps
T808 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2673921478 Jul 28 07:34:14 PM PDT 24 Jul 28 07:34:15 PM PDT 24 435154395 ps
T90 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3147419613 Jul 28 07:34:36 PM PDT 24 Jul 28 07:34:38 PM PDT 24 560350534 ps
T46 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2810060576 Jul 28 07:34:04 PM PDT 24 Jul 28 07:34:10 PM PDT 24 2156671848 ps
T809 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1215533055 Jul 28 07:34:18 PM PDT 24 Jul 28 07:34:19 PM PDT 24 604928517 ps
T49 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1531000662 Jul 28 07:34:36 PM PDT 24 Jul 28 07:34:43 PM PDT 24 8763082983 ps
T810 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.608944950 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:31 PM PDT 24 426589097 ps
T108 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4266452269 Jul 28 07:34:30 PM PDT 24 Jul 28 07:34:31 PM PDT 24 570732927 ps
T811 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1928239691 Jul 28 07:34:21 PM PDT 24 Jul 28 07:34:22 PM PDT 24 400909889 ps
T812 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.215750785 Jul 28 07:33:58 PM PDT 24 Jul 28 07:33:59 PM PDT 24 364187427 ps
T122 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3607163430 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:30 PM PDT 24 361268427 ps
T813 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3886490127 Jul 28 07:34:20 PM PDT 24 Jul 28 07:34:21 PM PDT 24 525790444 ps
T814 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3669482928 Jul 28 07:34:49 PM PDT 24 Jul 28 07:34:50 PM PDT 24 352042258 ps
T109 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2503518249 Jul 28 07:34:39 PM PDT 24 Jul 28 07:34:40 PM PDT 24 520737961 ps
T815 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1130278522 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:46 PM PDT 24 409257178 ps
T816 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1657840813 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:49 PM PDT 24 337338222 ps
T110 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3464063580 Jul 28 07:33:54 PM PDT 24 Jul 28 07:34:00 PM PDT 24 1007320313 ps
T817 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.193887584 Jul 28 07:34:22 PM PDT 24 Jul 28 07:34:24 PM PDT 24 539529392 ps
T818 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1982505914 Jul 28 07:34:10 PM PDT 24 Jul 28 07:37:03 PM PDT 24 53059728136 ps
T819 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3809303463 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:47 PM PDT 24 319645293 ps
T820 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.563295349 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:31 PM PDT 24 3827091314 ps
T50 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2749102348 Jul 28 07:34:10 PM PDT 24 Jul 28 07:34:32 PM PDT 24 8530889644 ps
T821 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2596094875 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:46 PM PDT 24 523913252 ps
T63 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3009281396 Jul 28 07:34:15 PM PDT 24 Jul 28 07:34:17 PM PDT 24 473872478 ps
T822 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2858485180 Jul 28 07:34:14 PM PDT 24 Jul 28 07:34:15 PM PDT 24 435419950 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.679354570 Jul 28 07:33:51 PM PDT 24 Jul 28 07:33:53 PM PDT 24 526317698 ps
T824 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3956882577 Jul 28 07:34:34 PM PDT 24 Jul 28 07:34:43 PM PDT 24 4592810180 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2380136922 Jul 28 07:33:58 PM PDT 24 Jul 28 07:34:01 PM PDT 24 487265113 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1338609044 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:29 PM PDT 24 784810985 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.896036866 Jul 28 07:34:13 PM PDT 24 Jul 28 07:34:15 PM PDT 24 408359001 ps
T827 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2590709090 Jul 28 07:34:48 PM PDT 24 Jul 28 07:34:49 PM PDT 24 526487051 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3032283146 Jul 28 07:34:03 PM PDT 24 Jul 28 07:34:06 PM PDT 24 1159602434 ps
T829 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3772647518 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:35 PM PDT 24 686335512 ps
T358 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2611427025 Jul 28 07:33:54 PM PDT 24 Jul 28 07:34:12 PM PDT 24 8227636955 ps
T111 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1771046837 Jul 28 07:33:58 PM PDT 24 Jul 28 07:34:33 PM PDT 24 45991800264 ps
T830 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1407873274 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:47 PM PDT 24 507295060 ps
T831 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.712709708 Jul 28 07:34:40 PM PDT 24 Jul 28 07:34:42 PM PDT 24 393310884 ps
T832 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3197987081 Jul 28 07:34:14 PM PDT 24 Jul 28 07:34:16 PM PDT 24 2814532110 ps
T833 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.883790891 Jul 28 07:33:53 PM PDT 24 Jul 28 07:34:13 PM PDT 24 27235418782 ps
T834 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3493810097 Jul 28 07:34:06 PM PDT 24 Jul 28 07:34:08 PM PDT 24 825903103 ps
T54 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1951876861 Jul 28 07:34:26 PM PDT 24 Jul 28 07:34:29 PM PDT 24 4922539640 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3334601628 Jul 28 07:34:40 PM PDT 24 Jul 28 07:34:41 PM PDT 24 518690077 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3647500127 Jul 28 07:34:37 PM PDT 24 Jul 28 07:34:37 PM PDT 24 316723644 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.986791931 Jul 28 07:34:37 PM PDT 24 Jul 28 07:34:39 PM PDT 24 328512929 ps
T838 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.27731345 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:49 PM PDT 24 428490702 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1162328312 Jul 28 07:34:05 PM PDT 24 Jul 28 07:34:06 PM PDT 24 504937213 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4139957333 Jul 28 07:33:59 PM PDT 24 Jul 28 07:34:00 PM PDT 24 1919846216 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.533690113 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:33 PM PDT 24 383508620 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2295346297 Jul 28 07:34:09 PM PDT 24 Jul 28 07:34:11 PM PDT 24 431224951 ps
T65 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1293487313 Jul 28 07:34:28 PM PDT 24 Jul 28 07:34:40 PM PDT 24 7700768568 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2548112380 Jul 28 07:34:15 PM PDT 24 Jul 28 07:34:17 PM PDT 24 2799868986 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.432999518 Jul 28 07:34:06 PM PDT 24 Jul 28 07:34:08 PM PDT 24 476630056 ps
T112 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.375527839 Jul 28 07:34:33 PM PDT 24 Jul 28 07:34:34 PM PDT 24 358578502 ps
T360 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.270501262 Jul 28 07:34:15 PM PDT 24 Jul 28 07:34:37 PM PDT 24 8471815294 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1874873996 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:54 PM PDT 24 2574609079 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.379022048 Jul 28 07:34:30 PM PDT 24 Jul 28 07:34:32 PM PDT 24 840828689 ps
T847 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1870489907 Jul 28 07:34:30 PM PDT 24 Jul 28 07:34:31 PM PDT 24 372010069 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3722879627 Jul 28 07:34:10 PM PDT 24 Jul 28 07:34:12 PM PDT 24 482499613 ps
T848 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3939717087 Jul 28 07:34:34 PM PDT 24 Jul 28 07:34:39 PM PDT 24 2561177256 ps
T849 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3789619757 Jul 28 07:34:08 PM PDT 24 Jul 28 07:34:28 PM PDT 24 7932357267 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3833496153 Jul 28 07:34:08 PM PDT 24 Jul 28 07:34:13 PM PDT 24 1297968319 ps
T851 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.831022642 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:46 PM PDT 24 380642866 ps
T852 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3380901840 Jul 28 07:34:44 PM PDT 24 Jul 28 07:34:45 PM PDT 24 333999784 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3612800833 Jul 28 07:33:58 PM PDT 24 Jul 28 07:34:02 PM PDT 24 854428828 ps
T854 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.254585645 Jul 28 07:34:17 PM PDT 24 Jul 28 07:34:19 PM PDT 24 477672606 ps
T855 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1641408710 Jul 28 07:34:42 PM PDT 24 Jul 28 07:34:44 PM PDT 24 387348169 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1263113596 Jul 28 07:34:15 PM PDT 24 Jul 28 07:34:16 PM PDT 24 467946380 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3667853919 Jul 28 07:34:37 PM PDT 24 Jul 28 07:34:41 PM PDT 24 4324984111 ps
T858 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4042234944 Jul 28 07:34:44 PM PDT 24 Jul 28 07:34:45 PM PDT 24 396303491 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3669291042 Jul 28 07:34:03 PM PDT 24 Jul 28 07:34:20 PM PDT 24 24251124363 ps
T859 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2422785396 Jul 28 07:34:26 PM PDT 24 Jul 28 07:34:28 PM PDT 24 413016576 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2119327052 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:48 PM PDT 24 5322356654 ps
T861 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3909660375 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:29 PM PDT 24 488705568 ps
T862 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.867371289 Jul 28 07:34:28 PM PDT 24 Jul 28 07:34:29 PM PDT 24 534830637 ps
T863 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4150346580 Jul 28 07:34:49 PM PDT 24 Jul 28 07:34:51 PM PDT 24 459350688 ps
T864 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4028292673 Jul 28 07:34:09 PM PDT 24 Jul 28 07:34:15 PM PDT 24 4391917862 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3255544599 Jul 28 07:34:08 PM PDT 24 Jul 28 07:34:09 PM PDT 24 376971723 ps
T866 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2581767634 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:31 PM PDT 24 4831652396 ps
T867 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2854584574 Jul 28 07:34:18 PM PDT 24 Jul 28 07:34:22 PM PDT 24 2215938845 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1255071402 Jul 28 07:34:34 PM PDT 24 Jul 28 07:34:35 PM PDT 24 1217677451 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3652940861 Jul 28 07:34:05 PM PDT 24 Jul 28 07:34:07 PM PDT 24 563725917 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2269016891 Jul 28 07:34:38 PM PDT 24 Jul 28 07:34:40 PM PDT 24 467918192 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1920015376 Jul 28 07:34:17 PM PDT 24 Jul 28 07:34:26 PM PDT 24 4452314216 ps
T871 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3979775646 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:47 PM PDT 24 472541498 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2226779381 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:34 PM PDT 24 326463176 ps
T873 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1557635592 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:40 PM PDT 24 3341255568 ps
T361 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2291267474 Jul 28 07:33:58 PM PDT 24 Jul 28 07:34:05 PM PDT 24 4214907697 ps
T874 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3580022893 Jul 28 07:34:42 PM PDT 24 Jul 28 07:34:43 PM PDT 24 433161326 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2209215073 Jul 28 07:34:14 PM PDT 24 Jul 28 07:34:34 PM PDT 24 8078614457 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2563068968 Jul 28 07:33:58 PM PDT 24 Jul 28 07:34:00 PM PDT 24 742832230 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2584374119 Jul 28 07:34:19 PM PDT 24 Jul 28 07:34:22 PM PDT 24 394960806 ps
T877 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1939408518 Jul 28 07:34:41 PM PDT 24 Jul 28 07:34:43 PM PDT 24 377705820 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3323010331 Jul 28 07:33:58 PM PDT 24 Jul 28 07:33:59 PM PDT 24 589280785 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2194324439 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:31 PM PDT 24 316639635 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3504782319 Jul 28 07:33:48 PM PDT 24 Jul 28 07:33:51 PM PDT 24 610446911 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.928639601 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:31 PM PDT 24 613237730 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3808986804 Jul 28 07:34:04 PM PDT 24 Jul 28 07:34:06 PM PDT 24 471288454 ps
T882 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3655105357 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:36 PM PDT 24 4489499589 ps
T883 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3392130272 Jul 28 07:34:48 PM PDT 24 Jul 28 07:34:49 PM PDT 24 281964546 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2693201643 Jul 28 07:34:08 PM PDT 24 Jul 28 07:34:11 PM PDT 24 1237321224 ps
T885 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3724505665 Jul 28 07:34:19 PM PDT 24 Jul 28 07:34:27 PM PDT 24 8096926944 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3013889249 Jul 28 07:34:37 PM PDT 24 Jul 28 07:34:45 PM PDT 24 2219471195 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2087476372 Jul 28 07:34:29 PM PDT 24 Jul 28 07:34:30 PM PDT 24 2697206891 ps
T888 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.277763771 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:48 PM PDT 24 365231108 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4260825326 Jul 28 07:34:14 PM PDT 24 Jul 28 07:34:19 PM PDT 24 3999057711 ps
T890 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.707199280 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:47 PM PDT 24 599593944 ps
T891 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2250022322 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:46 PM PDT 24 340189177 ps
T892 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.36543227 Jul 28 07:34:02 PM PDT 24 Jul 28 07:34:04 PM PDT 24 402949904 ps
T893 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4162367270 Jul 28 07:34:22 PM PDT 24 Jul 28 07:34:29 PM PDT 24 4622742798 ps
T894 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4161046187 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:33 PM PDT 24 452483282 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3452384547 Jul 28 07:34:28 PM PDT 24 Jul 28 07:34:29 PM PDT 24 636514715 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.77779777 Jul 28 07:34:04 PM PDT 24 Jul 28 07:34:06 PM PDT 24 817367100 ps
T359 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3072912038 Jul 28 07:34:34 PM PDT 24 Jul 28 07:34:38 PM PDT 24 10152594976 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2774168530 Jul 28 07:33:56 PM PDT 24 Jul 28 07:33:57 PM PDT 24 340148599 ps
T898 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3805898321 Jul 28 07:34:32 PM PDT 24 Jul 28 07:34:33 PM PDT 24 463923472 ps
T899 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3906368547 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:48 PM PDT 24 438897134 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3750204580 Jul 28 07:33:54 PM PDT 24 Jul 28 07:33:58 PM PDT 24 2118512011 ps
T901 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3666366495 Jul 28 07:34:44 PM PDT 24 Jul 28 07:34:46 PM PDT 24 390554540 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2753065873 Jul 28 07:34:04 PM PDT 24 Jul 28 07:34:09 PM PDT 24 9334896918 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.375844948 Jul 28 07:33:55 PM PDT 24 Jul 28 07:33:59 PM PDT 24 634568112 ps
T904 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.170891234 Jul 28 07:34:22 PM PDT 24 Jul 28 07:34:25 PM PDT 24 546594711 ps
T905 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.458959436 Jul 28 07:34:18 PM PDT 24 Jul 28 07:34:19 PM PDT 24 373015590 ps
T906 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.928449523 Jul 28 07:34:35 PM PDT 24 Jul 28 07:34:39 PM PDT 24 4748203423 ps
T907 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2351403720 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:33 PM PDT 24 4610654672 ps
T908 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2826696086 Jul 28 07:34:47 PM PDT 24 Jul 28 07:34:48 PM PDT 24 315101773 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4141407700 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:30 PM PDT 24 1071909726 ps
T910 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1839064163 Jul 28 07:34:11 PM PDT 24 Jul 28 07:34:12 PM PDT 24 361169119 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.628567613 Jul 28 07:34:03 PM PDT 24 Jul 28 07:34:06 PM PDT 24 491445781 ps
T912 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4170567824 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:48 PM PDT 24 319754026 ps
T913 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3772010190 Jul 28 07:34:40 PM PDT 24 Jul 28 07:34:49 PM PDT 24 4131448735 ps
T914 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.670862030 Jul 28 07:34:31 PM PDT 24 Jul 28 07:34:33 PM PDT 24 487741519 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.440597510 Jul 28 07:33:54 PM PDT 24 Jul 28 07:33:56 PM PDT 24 541903754 ps
T916 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.268967923 Jul 28 07:34:27 PM PDT 24 Jul 28 07:34:29 PM PDT 24 338348705 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2790349552 Jul 28 07:33:56 PM PDT 24 Jul 28 07:34:01 PM PDT 24 984574941 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3524580524 Jul 28 07:33:52 PM PDT 24 Jul 28 07:33:56 PM PDT 24 1276862231 ps
T918 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.426656459 Jul 28 07:34:45 PM PDT 24 Jul 28 07:34:45 PM PDT 24 369389137 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3629538914 Jul 28 07:33:52 PM PDT 24 Jul 28 07:33:54 PM PDT 24 1222965110 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.859623789 Jul 28 07:34:36 PM PDT 24 Jul 28 07:34:47 PM PDT 24 8597507620 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2788433435 Jul 28 07:34:17 PM PDT 24 Jul 28 07:34:18 PM PDT 24 480590936 ps
T920 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.780459548 Jul 28 07:34:38 PM PDT 24 Jul 28 07:34:39 PM PDT 24 548967421 ps

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.46567994
Short name T7
Test name
Test status
Simulation time 123779204333 ps
CPU time 253.78 seconds
Started Jul 28 06:46:01 PM PDT 24
Finished Jul 28 06:50:15 PM PDT 24
Peak memory 210348 kb
Host smart-f661c51f-d64f-4221-a6f0-510d6b541ec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46567994 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.46567994
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4149781455
Short name T33
Test name
Test status
Simulation time 464558866213 ps
CPU time 114.74 seconds
Started Jul 28 06:44:33 PM PDT 24
Finished Jul 28 06:46:28 PM PDT 24
Peak memory 211696 kb
Host smart-bea486f6-b341-4240-858f-604c3e9c2cc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149781455 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.4149781455
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.888843537
Short name T13
Test name
Test status
Simulation time 241065715130 ps
CPU time 315.11 seconds
Started Jul 28 06:48:41 PM PDT 24
Finished Jul 28 06:53:56 PM PDT 24
Peak memory 209984 kb
Host smart-e5937147-c11c-48c8-af3a-8a092fc7c446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888843537 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.888843537
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4276292958
Short name T134
Test name
Test status
Simulation time 488132531309 ps
CPU time 97.06 seconds
Started Jul 28 06:48:22 PM PDT 24
Finished Jul 28 06:49:59 PM PDT 24
Peak memory 201144 kb
Host smart-848ca03f-6497-4552-8651-1bd7214be57d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276292958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4276292958
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1253085981
Short name T168
Test name
Test status
Simulation time 518593103492 ps
CPU time 1127.84 seconds
Started Jul 28 06:45:18 PM PDT 24
Finished Jul 28 07:04:06 PM PDT 24
Peak memory 201176 kb
Host smart-0e08ed7b-cd62-451e-954f-00f0e4445d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253085981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1253085981
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3640272857
Short name T242
Test name
Test status
Simulation time 517945504103 ps
CPU time 646.16 seconds
Started Jul 28 06:44:16 PM PDT 24
Finished Jul 28 06:55:02 PM PDT 24
Peak memory 201128 kb
Host smart-0c65f2eb-574b-4007-94d7-1d4b926c9c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640272857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3640272857
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3859024402
Short name T139
Test name
Test status
Simulation time 657957530410 ps
CPU time 1546.98 seconds
Started Jul 28 06:40:14 PM PDT 24
Finished Jul 28 07:06:01 PM PDT 24
Peak memory 201176 kb
Host smart-58a3a242-eb9f-48ff-aa1c-616ae2a58732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859024402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3859024402
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.426833363
Short name T307
Test name
Test status
Simulation time 316690111762 ps
CPU time 161.79 seconds
Started Jul 28 06:45:40 PM PDT 24
Finished Jul 28 06:48:22 PM PDT 24
Peak memory 209960 kb
Host smart-8096817c-a0cf-489d-b67b-00ea1ee5f4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426833363 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.426833363
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1718276431
Short name T160
Test name
Test status
Simulation time 626167024062 ps
CPU time 490.35 seconds
Started Jul 28 06:45:22 PM PDT 24
Finished Jul 28 06:53:33 PM PDT 24
Peak memory 201580 kb
Host smart-12ae809d-4015-401f-ae5b-d92de8d17ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718276431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1718276431
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3939595911
Short name T59
Test name
Test status
Simulation time 808432177 ps
CPU time 2.38 seconds
Started Jul 28 07:34:15 PM PDT 24
Finished Jul 28 07:34:17 PM PDT 24
Peak memory 201776 kb
Host smart-0a5b4044-96f4-4533-86e6-8c0c9bdecbbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939595911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3939595911
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2086814992
Short name T130
Test name
Test status
Simulation time 551848151656 ps
CPU time 1301.9 seconds
Started Jul 28 06:43:58 PM PDT 24
Finished Jul 28 07:05:40 PM PDT 24
Peak memory 201152 kb
Host smart-367cb57f-0cd3-4e52-9588-eaba30a4c7ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086814992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2086814992
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1705244423
Short name T6
Test name
Test status
Simulation time 500866896372 ps
CPU time 320.58 seconds
Started Jul 28 06:48:32 PM PDT 24
Finished Jul 28 06:53:52 PM PDT 24
Peak memory 201220 kb
Host smart-0314cbad-2a6b-43db-98ef-2e552d8134db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705244423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1705244423
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.149179542
Short name T153
Test name
Test status
Simulation time 511769481647 ps
CPU time 1179.47 seconds
Started Jul 28 06:45:46 PM PDT 24
Finished Jul 28 07:05:25 PM PDT 24
Peak memory 201200 kb
Host smart-06990596-6461-43d4-b164-d5fdcb6ee6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149179542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.149179542
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.8316558
Short name T135
Test name
Test status
Simulation time 526451856389 ps
CPU time 604.54 seconds
Started Jul 28 06:42:13 PM PDT 24
Finished Jul 28 06:52:18 PM PDT 24
Peak memory 201156 kb
Host smart-b390e346-73bb-43ba-a080-215d38176289
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8316558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wa
keup.8316558
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3130105125
Short name T163
Test name
Test status
Simulation time 362150944 ps
CPU time 1.04 seconds
Started Jul 28 06:42:35 PM PDT 24
Finished Jul 28 06:42:36 PM PDT 24
Peak memory 200920 kb
Host smart-5517edf7-ab5f-4dc0-bbfe-92746d53c21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130105125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3130105125
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1338696144
Short name T94
Test name
Test status
Simulation time 368327503396 ps
CPU time 862.48 seconds
Started Jul 28 06:46:56 PM PDT 24
Finished Jul 28 07:01:18 PM PDT 24
Peak memory 201244 kb
Host smart-3dc1673f-a95f-4abf-8ed3-7a24c2eff726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338696144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1338696144
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2313604588
Short name T16
Test name
Test status
Simulation time 278811835214 ps
CPU time 136.6 seconds
Started Jul 28 06:46:17 PM PDT 24
Finished Jul 28 06:48:34 PM PDT 24
Peak memory 209900 kb
Host smart-a48e2bfa-d6cb-4ff7-84b8-813f1cc2656a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313604588 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2313604588
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1771046837
Short name T111
Test name
Test status
Simulation time 45991800264 ps
CPU time 34.39 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 201752 kb
Host smart-2de003cd-16ad-40af-8087-6e5a34e792a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771046837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1771046837
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.484750132
Short name T55
Test name
Test status
Simulation time 8054861926 ps
CPU time 9.75 seconds
Started Jul 28 06:38:51 PM PDT 24
Finished Jul 28 06:39:01 PM PDT 24
Peak memory 217856 kb
Host smart-829b2389-5715-40aa-8f8d-8ead705fea9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484750132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.484750132
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3144466459
Short name T155
Test name
Test status
Simulation time 497435656116 ps
CPU time 1022.75 seconds
Started Jul 28 06:45:59 PM PDT 24
Finished Jul 28 07:03:02 PM PDT 24
Peak memory 201164 kb
Host smart-b9474864-ec21-4654-9bca-866c04385465
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144466459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3144466459
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1902984527
Short name T187
Test name
Test status
Simulation time 377571383719 ps
CPU time 856.1 seconds
Started Jul 28 06:39:18 PM PDT 24
Finished Jul 28 06:53:35 PM PDT 24
Peak memory 201172 kb
Host smart-7fa13929-ef13-43af-a678-42ac8586492f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902984527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1902984527
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.293232816
Short name T146
Test name
Test status
Simulation time 357346305523 ps
CPU time 433.33 seconds
Started Jul 28 06:45:57 PM PDT 24
Finished Jul 28 06:53:10 PM PDT 24
Peak memory 201176 kb
Host smart-7522aa95-df1b-4d30-8b56-bab4a3c318c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293232816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.293232816
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2303781953
Short name T318
Test name
Test status
Simulation time 546888278438 ps
CPU time 330.03 seconds
Started Jul 28 06:47:27 PM PDT 24
Finished Jul 28 06:52:57 PM PDT 24
Peak memory 201148 kb
Host smart-f7025f2a-9849-41d1-b7cd-bada13a239a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303781953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2303781953
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3000479739
Short name T282
Test name
Test status
Simulation time 513946565858 ps
CPU time 247.82 seconds
Started Jul 28 06:45:27 PM PDT 24
Finished Jul 28 06:49:35 PM PDT 24
Peak memory 201104 kb
Host smart-edd7c976-ff90-4ef4-876e-637d3ebaa1ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000479739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3000479739
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2026011470
Short name T188
Test name
Test status
Simulation time 425793148084 ps
CPU time 301.32 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 06:53:53 PM PDT 24
Peak memory 201820 kb
Host smart-696972f3-8df2-4352-aee9-76f73509865f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026011470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2026011470
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2654919819
Short name T259
Test name
Test status
Simulation time 551303386427 ps
CPU time 1152.71 seconds
Started Jul 28 06:49:53 PM PDT 24
Finished Jul 28 07:09:06 PM PDT 24
Peak memory 201208 kb
Host smart-7241f3e7-b9a9-476a-a532-be157ae8ce5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654919819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2654919819
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.890215070
Short name T14
Test name
Test status
Simulation time 115661095489 ps
CPU time 277.53 seconds
Started Jul 28 06:47:32 PM PDT 24
Finished Jul 28 06:52:10 PM PDT 24
Peak memory 209980 kb
Host smart-62ab7f9a-7fd8-4049-a25d-8886fa8dcdec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890215070 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.890215070
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2957406340
Short name T198
Test name
Test status
Simulation time 329602692078 ps
CPU time 205.43 seconds
Started Jul 28 06:40:40 PM PDT 24
Finished Jul 28 06:44:06 PM PDT 24
Peak memory 201112 kb
Host smart-cef1a39f-1ae5-4fbf-b241-ef027a0dc03a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957406340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2957406340
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3861544656
Short name T3
Test name
Test status
Simulation time 463480541255 ps
CPU time 932.22 seconds
Started Jul 28 06:45:52 PM PDT 24
Finished Jul 28 07:01:24 PM PDT 24
Peak memory 201144 kb
Host smart-7b6fbc90-fa36-401e-bf53-69e21da79eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861544656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3861544656
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2451304356
Short name T262
Test name
Test status
Simulation time 159773641555 ps
CPU time 211.59 seconds
Started Jul 28 06:50:30 PM PDT 24
Finished Jul 28 06:54:02 PM PDT 24
Peak memory 217412 kb
Host smart-cf926b0b-9376-4766-97bb-1ba0b6319119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451304356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2451304356
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1567289028
Short name T319
Test name
Test status
Simulation time 599966107499 ps
CPU time 1304.87 seconds
Started Jul 28 06:41:18 PM PDT 24
Finished Jul 28 07:03:03 PM PDT 24
Peak memory 201220 kb
Host smart-5eb88b3b-7034-4c3b-8605-3de8c4528b9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567289028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1567289028
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4139645661
Short name T133
Test name
Test status
Simulation time 327910706565 ps
CPU time 123.24 seconds
Started Jul 28 06:45:25 PM PDT 24
Finished Jul 28 06:47:28 PM PDT 24
Peak memory 201164 kb
Host smart-572608ff-3cf4-49fb-bc72-e78f4bd985ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139645661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4139645661
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1531000662
Short name T49
Test name
Test status
Simulation time 8763082983 ps
CPU time 6.73 seconds
Started Jul 28 07:34:36 PM PDT 24
Finished Jul 28 07:34:43 PM PDT 24
Peak memory 201848 kb
Host smart-420a0980-d542-4395-8150-5bd31f573074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531000662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1531000662
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2572002109
Short name T19
Test name
Test status
Simulation time 123326505630 ps
CPU time 425.77 seconds
Started Jul 28 06:39:33 PM PDT 24
Finished Jul 28 06:46:38 PM PDT 24
Peak memory 217360 kb
Host smart-c5c300dc-82a7-4c44-8640-328adb6e5f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572002109 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2572002109
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3187867248
Short name T45
Test name
Test status
Simulation time 5304861200 ps
CPU time 3.95 seconds
Started Jul 28 07:33:51 PM PDT 24
Finished Jul 28 07:33:55 PM PDT 24
Peak memory 201896 kb
Host smart-4b969754-b14f-4884-976c-5b2b504e9cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187867248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3187867248
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4265960349
Short name T252
Test name
Test status
Simulation time 162430926535 ps
CPU time 310.54 seconds
Started Jul 28 06:38:57 PM PDT 24
Finished Jul 28 06:44:08 PM PDT 24
Peak memory 201156 kb
Host smart-cc997700-9e14-476d-9732-28fda35254ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265960349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4265960349
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3529617997
Short name T29
Test name
Test status
Simulation time 352199161085 ps
CPU time 415.26 seconds
Started Jul 28 06:47:29 PM PDT 24
Finished Jul 28 06:54:24 PM PDT 24
Peak memory 201176 kb
Host smart-03198348-7c62-4dd2-9d8b-62049a4e089e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529617997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3529617997
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1552668509
Short name T177
Test name
Test status
Simulation time 163542875284 ps
CPU time 100.61 seconds
Started Jul 28 06:46:28 PM PDT 24
Finished Jul 28 06:48:09 PM PDT 24
Peak memory 201160 kb
Host smart-1b013e7c-2a9f-4d13-b91d-7795546e1c5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552668509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1552668509
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.530537404
Short name T288
Test name
Test status
Simulation time 516282916912 ps
CPU time 1125.21 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:58:56 PM PDT 24
Peak memory 201260 kb
Host smart-d67a853b-b322-4e96-8229-ca08c4743ee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530537404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.530537404
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.647428683
Short name T321
Test name
Test status
Simulation time 360902994850 ps
CPU time 853.35 seconds
Started Jul 28 06:38:47 PM PDT 24
Finished Jul 28 06:53:01 PM PDT 24
Peak memory 201144 kb
Host smart-8049f649-1953-4f53-af10-702b5e57f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647428683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.647428683
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3562527345
Short name T267
Test name
Test status
Simulation time 57403203745 ps
CPU time 67.56 seconds
Started Jul 28 06:47:43 PM PDT 24
Finished Jul 28 06:48:51 PM PDT 24
Peak memory 217616 kb
Host smart-720e7b1a-0ff1-46df-a4ad-27976c8478c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562527345 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3562527345
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3376908913
Short name T127
Test name
Test status
Simulation time 529040809972 ps
CPU time 851.23 seconds
Started Jul 28 06:42:06 PM PDT 24
Finished Jul 28 06:56:17 PM PDT 24
Peak memory 201144 kb
Host smart-f332a9e2-6188-4da1-a4d4-e895fdd80f2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376908913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3376908913
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2649483882
Short name T22
Test name
Test status
Simulation time 210947811060 ps
CPU time 395.6 seconds
Started Jul 28 06:46:33 PM PDT 24
Finished Jul 28 06:53:09 PM PDT 24
Peak memory 210232 kb
Host smart-b5dec0fd-f920-4b55-8de9-729939d3d0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649483882 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2649483882
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3650974290
Short name T339
Test name
Test status
Simulation time 202026062737 ps
CPU time 440.34 seconds
Started Jul 28 06:49:14 PM PDT 24
Finished Jul 28 06:56:34 PM PDT 24
Peak memory 201172 kb
Host smart-35ffe64d-3b8f-40d1-8057-5fc232ca0488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650974290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3650974290
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2073670991
Short name T183
Test name
Test status
Simulation time 501170309948 ps
CPU time 310.12 seconds
Started Jul 28 06:42:35 PM PDT 24
Finished Jul 28 06:47:46 PM PDT 24
Peak memory 201288 kb
Host smart-ede4b0cd-dc6c-46ca-9dd6-904c4d00317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073670991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2073670991
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.416711303
Short name T337
Test name
Test status
Simulation time 594851278322 ps
CPU time 1035.82 seconds
Started Jul 28 06:47:41 PM PDT 24
Finished Jul 28 07:04:57 PM PDT 24
Peak memory 201124 kb
Host smart-6f27caf2-3dea-41c7-a670-46c05b852f78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416711303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.416711303
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1197038423
Short name T331
Test name
Test status
Simulation time 161062287570 ps
CPU time 236.7 seconds
Started Jul 28 06:44:20 PM PDT 24
Finished Jul 28 06:48:17 PM PDT 24
Peak memory 201152 kb
Host smart-5492515c-59e1-4a36-b21a-7486189410ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197038423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1197038423
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.838210338
Short name T274
Test name
Test status
Simulation time 391165660163 ps
CPU time 844.43 seconds
Started Jul 28 06:43:41 PM PDT 24
Finished Jul 28 06:57:46 PM PDT 24
Peak memory 201156 kb
Host smart-119da198-4093-4ade-a5e2-73ad946dceab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838210338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.838210338
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1541212287
Short name T266
Test name
Test status
Simulation time 163561945455 ps
CPU time 140.89 seconds
Started Jul 28 06:44:50 PM PDT 24
Finished Jul 28 06:47:11 PM PDT 24
Peak memory 201232 kb
Host smart-f3890a22-5f1d-47d4-9fdb-ad2d15281a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541212287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1541212287
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1480380406
Short name T235
Test name
Test status
Simulation time 330546587558 ps
CPU time 1189.04 seconds
Started Jul 28 06:49:31 PM PDT 24
Finished Jul 28 07:09:21 PM PDT 24
Peak memory 209776 kb
Host smart-627c44b8-99e2-4948-97a3-e96122e07ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480380406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1480380406
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.989018180
Short name T291
Test name
Test status
Simulation time 350818804228 ps
CPU time 862.3 seconds
Started Jul 28 06:50:05 PM PDT 24
Finished Jul 28 07:04:28 PM PDT 24
Peak memory 201128 kb
Host smart-991639d0-90bf-4f4a-9b8c-97d7dafaa3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989018180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.989018180
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1813290828
Short name T326
Test name
Test status
Simulation time 528100651183 ps
CPU time 610.57 seconds
Started Jul 28 06:38:48 PM PDT 24
Finished Jul 28 06:48:58 PM PDT 24
Peak memory 201144 kb
Host smart-60f3e9ef-9fd3-4d5f-b9db-64bcfe166e2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813290828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1813290828
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2418663339
Short name T238
Test name
Test status
Simulation time 177179990951 ps
CPU time 372.46 seconds
Started Jul 28 06:41:35 PM PDT 24
Finished Jul 28 06:47:47 PM PDT 24
Peak memory 201228 kb
Host smart-13c1b389-5d97-41e0-b554-606450230726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418663339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2418663339
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.649411601
Short name T246
Test name
Test status
Simulation time 489307161425 ps
CPU time 1045.9 seconds
Started Jul 28 06:45:05 PM PDT 24
Finished Jul 28 07:02:31 PM PDT 24
Peak memory 201212 kb
Host smart-27298c63-4bb8-4e62-b3d7-f2ecc87e1b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649411601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.649411601
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.430100048
Short name T347
Test name
Test status
Simulation time 88507005102 ps
CPU time 191.89 seconds
Started Jul 28 06:46:51 PM PDT 24
Finished Jul 28 06:50:03 PM PDT 24
Peak memory 209556 kb
Host smart-a1103bc0-7a68-47a4-9d8c-cf2118584d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430100048 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.430100048
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2824280545
Short name T285
Test name
Test status
Simulation time 541399826688 ps
CPU time 1158.66 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 07:09:53 PM PDT 24
Peak memory 201164 kb
Host smart-94c3e9cc-bc37-4cb8-a280-ea4c0f5f66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824280545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2824280545
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4133640027
Short name T675
Test name
Test status
Simulation time 276131697265 ps
CPU time 392.24 seconds
Started Jul 28 06:39:02 PM PDT 24
Finished Jul 28 06:45:34 PM PDT 24
Peak memory 209800 kb
Host smart-82a702a2-5b09-4c4d-8394-b0a8fc6ce827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133640027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4133640027
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3395679649
Short name T227
Test name
Test status
Simulation time 198332159291 ps
CPU time 757.69 seconds
Started Jul 28 06:42:00 PM PDT 24
Finished Jul 28 06:54:38 PM PDT 24
Peak memory 201660 kb
Host smart-2314b781-175c-4ce0-a035-2393c70f0fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395679649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3395679649
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3828889149
Short name T283
Test name
Test status
Simulation time 377790080448 ps
CPU time 230.26 seconds
Started Jul 28 06:42:06 PM PDT 24
Finished Jul 28 06:45:57 PM PDT 24
Peak memory 201216 kb
Host smart-fe8de2d9-4898-43b2-985e-38d3b27509da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828889149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3828889149
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.722315254
Short name T294
Test name
Test status
Simulation time 709542466016 ps
CPU time 1789.15 seconds
Started Jul 28 06:42:46 PM PDT 24
Finished Jul 28 07:12:35 PM PDT 24
Peak memory 209804 kb
Host smart-8e8bdcd7-3c82-4d74-8c12-8c83fc36437a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722315254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
722315254
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3965220202
Short name T304
Test name
Test status
Simulation time 536760947605 ps
CPU time 177.07 seconds
Started Jul 28 06:43:10 PM PDT 24
Finished Jul 28 06:46:07 PM PDT 24
Peak memory 201268 kb
Host smart-8d19a512-87de-4df6-b4a2-39145f1a59ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965220202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3965220202
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3209614183
Short name T286
Test name
Test status
Simulation time 500008234294 ps
CPU time 1135.49 seconds
Started Jul 28 06:47:48 PM PDT 24
Finished Jul 28 07:06:44 PM PDT 24
Peak memory 201172 kb
Host smart-35d89abe-2de5-4896-a830-35dbf046f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209614183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3209614183
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.719812603
Short name T258
Test name
Test status
Simulation time 166807224113 ps
CPU time 105.52 seconds
Started Jul 28 06:39:41 PM PDT 24
Finished Jul 28 06:41:26 PM PDT 24
Peak memory 201208 kb
Host smart-bf376e55-bb62-4155-9baf-08b8bf88e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719812603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.719812603
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.639877182
Short name T179
Test name
Test status
Simulation time 325505477184 ps
CPU time 144.74 seconds
Started Jul 28 06:48:41 PM PDT 24
Finished Jul 28 06:51:06 PM PDT 24
Peak memory 201176 kb
Host smart-174d49e5-2706-4448-acd0-8e61b14bc43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639877182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.639877182
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.859623789
Short name T67
Test name
Test status
Simulation time 8597507620 ps
CPU time 11.57 seconds
Started Jul 28 07:34:36 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201716 kb
Host smart-eae8441d-419c-4e68-9de8-259060397594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859623789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.859623789
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2694281830
Short name T206
Test name
Test status
Simulation time 409639472472 ps
CPU time 854.84 seconds
Started Jul 28 06:38:55 PM PDT 24
Finished Jul 28 06:53:10 PM PDT 24
Peak memory 201088 kb
Host smart-ce19c0d5-419b-452a-b318-5be9f84422e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694281830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2694281830
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1953947166
Short name T93
Test name
Test status
Simulation time 484781909637 ps
CPU time 1038.59 seconds
Started Jul 28 06:43:20 PM PDT 24
Finished Jul 28 07:00:39 PM PDT 24
Peak memory 201152 kb
Host smart-3f281179-2233-4d90-b2b6-29a6715fa460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953947166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1953947166
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3089010342
Short name T344
Test name
Test status
Simulation time 336436734139 ps
CPU time 803.93 seconds
Started Jul 28 06:44:17 PM PDT 24
Finished Jul 28 06:57:41 PM PDT 24
Peak memory 201156 kb
Host smart-db5163b7-bd8b-46b9-9cbf-0f3872369abb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089010342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3089010342
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3919931795
Short name T225
Test name
Test status
Simulation time 108547783434 ps
CPU time 544.68 seconds
Started Jul 28 06:44:20 PM PDT 24
Finished Jul 28 06:53:25 PM PDT 24
Peak memory 201612 kb
Host smart-d1372d57-9b7f-4dec-a43a-6f02632c9af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919931795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3919931795
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3503902980
Short name T245
Test name
Test status
Simulation time 572405580441 ps
CPU time 369.22 seconds
Started Jul 28 06:45:03 PM PDT 24
Finished Jul 28 06:51:12 PM PDT 24
Peak memory 201172 kb
Host smart-83ef3669-e38e-4b7b-a498-cd8e7060617f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503902980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3503902980
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3305236008
Short name T332
Test name
Test status
Simulation time 329145913723 ps
CPU time 201.92 seconds
Started Jul 28 06:45:59 PM PDT 24
Finished Jul 28 06:49:21 PM PDT 24
Peak memory 201220 kb
Host smart-6801f300-89b9-4117-bb27-620ed07c30a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305236008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3305236008
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.545075502
Short name T287
Test name
Test status
Simulation time 194225801985 ps
CPU time 120.41 seconds
Started Jul 28 06:49:05 PM PDT 24
Finished Jul 28 06:51:05 PM PDT 24
Peak memory 201156 kb
Host smart-256a415e-c24a-465f-8464-4f8e45b4151c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545075502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.545075502
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3486078244
Short name T247
Test name
Test status
Simulation time 132918620281 ps
CPU time 133.19 seconds
Started Jul 28 06:50:12 PM PDT 24
Finished Jul 28 06:52:25 PM PDT 24
Peak memory 210616 kb
Host smart-8cc70732-3144-4d0b-aa04-a86c171ca9b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486078244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3486078244
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.869062736
Short name T290
Test name
Test status
Simulation time 324507055389 ps
CPU time 391.3 seconds
Started Jul 28 06:40:25 PM PDT 24
Finished Jul 28 06:46:57 PM PDT 24
Peak memory 201140 kb
Host smart-9b1c79e9-e6d3-4067-b52e-af390da53871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869062736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.869062736
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1338609044
Short name T825
Test name
Test status
Simulation time 784810985 ps
CPU time 2.68 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 209928 kb
Host smart-41fe5d6b-b518-4c52-9c19-81e846ea4fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338609044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1338609044
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1986828549
Short name T176
Test name
Test status
Simulation time 330163681814 ps
CPU time 141.84 seconds
Started Jul 28 06:38:57 PM PDT 24
Finished Jul 28 06:41:19 PM PDT 24
Peak memory 201160 kb
Host smart-2feecc8f-a008-4b4c-b425-56117f42c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986828549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1986828549
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1171991837
Short name T780
Test name
Test status
Simulation time 106629958673 ps
CPU time 454.4 seconds
Started Jul 28 06:39:02 PM PDT 24
Finished Jul 28 06:46:37 PM PDT 24
Peak memory 201700 kb
Host smart-e333df88-cc27-4755-9081-d82d19eb9166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171991837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1171991837
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2570368339
Short name T5
Test name
Test status
Simulation time 179822931777 ps
CPU time 189.28 seconds
Started Jul 28 06:42:21 PM PDT 24
Finished Jul 28 06:45:30 PM PDT 24
Peak memory 201120 kb
Host smart-2c128bf9-555c-4265-9611-e814b8eb1c70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570368339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2570368339
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2601417721
Short name T178
Test name
Test status
Simulation time 329100599587 ps
CPU time 692.02 seconds
Started Jul 28 06:42:52 PM PDT 24
Finished Jul 28 06:54:24 PM PDT 24
Peak memory 201132 kb
Host smart-b9da6d7d-e935-41e2-a0a8-7e1fdfe104de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601417721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2601417721
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.968878692
Short name T365
Test name
Test status
Simulation time 109756056364 ps
CPU time 546.18 seconds
Started Jul 28 06:43:17 PM PDT 24
Finished Jul 28 06:52:23 PM PDT 24
Peak memory 201584 kb
Host smart-852cde7a-016c-475b-b833-16e120c316be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968878692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.968878692
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.483025531
Short name T655
Test name
Test status
Simulation time 159579648526 ps
CPU time 250.79 seconds
Started Jul 28 06:43:17 PM PDT 24
Finished Jul 28 06:47:28 PM PDT 24
Peak memory 217232 kb
Host smart-dd8a8b10-7f23-4788-aa51-d0b67bfbdf50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483025531 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.483025531
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2119352471
Short name T74
Test name
Test status
Simulation time 501607918827 ps
CPU time 1234.14 seconds
Started Jul 28 06:43:24 PM PDT 24
Finished Jul 28 07:03:59 PM PDT 24
Peak memory 201224 kb
Host smart-567c9bd9-f6e9-4701-8318-6c4277df5468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119352471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2119352471
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3576465943
Short name T237
Test name
Test status
Simulation time 534474404100 ps
CPU time 1323.9 seconds
Started Jul 28 06:39:13 PM PDT 24
Finished Jul 28 07:01:17 PM PDT 24
Peak memory 201172 kb
Host smart-94908b1b-ec5b-4eb0-a6aa-6e2a00d801cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576465943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3576465943
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.785118518
Short name T143
Test name
Test status
Simulation time 323878842712 ps
CPU time 397 seconds
Started Jul 28 06:39:07 PM PDT 24
Finished Jul 28 06:45:45 PM PDT 24
Peak memory 201176 kb
Host smart-6f60897f-599d-4cd8-b51b-2221885f8be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785118518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.785118518
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3793219755
Short name T234
Test name
Test status
Simulation time 111575483412 ps
CPU time 478.79 seconds
Started Jul 28 06:39:26 PM PDT 24
Finished Jul 28 06:47:25 PM PDT 24
Peak memory 201624 kb
Host smart-d985b1a8-7f06-45e9-8c1a-186a5fd77bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793219755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3793219755
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4039100902
Short name T289
Test name
Test status
Simulation time 173613912404 ps
CPU time 100.98 seconds
Started Jul 28 06:49:09 PM PDT 24
Finished Jul 28 06:50:50 PM PDT 24
Peak memory 201200 kb
Host smart-4401845d-06c6-4d81-aa15-d782355164e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039100902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4039100902
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.646877098
Short name T260
Test name
Test status
Simulation time 154329046014 ps
CPU time 278.44 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:44:49 PM PDT 24
Peak memory 210020 kb
Host smart-394bbc1e-db68-492c-9d46-cc001735ee0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646877098 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.646877098
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1081962202
Short name T261
Test name
Test status
Simulation time 529498907017 ps
CPU time 1301.38 seconds
Started Jul 28 06:40:19 PM PDT 24
Finished Jul 28 07:02:01 PM PDT 24
Peak memory 201164 kb
Host smart-e3f815e9-b98c-4d09-9aec-89947437f49c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081962202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1081962202
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2778063809
Short name T123
Test name
Test status
Simulation time 1136895087 ps
CPU time 3.79 seconds
Started Jul 28 07:33:53 PM PDT 24
Finished Jul 28 07:33:57 PM PDT 24
Peak memory 201700 kb
Host smart-d08e951a-4e3a-40b5-9617-bb0dd01023f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778063809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2778063809
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3464063580
Short name T110
Test name
Test status
Simulation time 1007320313 ps
CPU time 5.64 seconds
Started Jul 28 07:33:54 PM PDT 24
Finished Jul 28 07:34:00 PM PDT 24
Peak memory 201596 kb
Host smart-335c653f-029c-4912-a845-64d98e836a6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464063580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3464063580
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3629538914
Short name T118
Test name
Test status
Simulation time 1222965110 ps
CPU time 1.47 seconds
Started Jul 28 07:33:52 PM PDT 24
Finished Jul 28 07:33:54 PM PDT 24
Peak memory 201660 kb
Host smart-ecb6315c-dd9a-4694-a1cd-913bcc00d7bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629538914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3629538914
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.679354570
Short name T823
Test name
Test status
Simulation time 526317698 ps
CPU time 2.04 seconds
Started Jul 28 07:33:51 PM PDT 24
Finished Jul 28 07:33:53 PM PDT 24
Peak memory 201576 kb
Host smart-a09a3a06-04a0-4f33-9fc5-dc790185f702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679354570 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.679354570
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1789786834
Short name T47
Test name
Test status
Simulation time 533762525 ps
CPU time 2.1 seconds
Started Jul 28 07:33:52 PM PDT 24
Finished Jul 28 07:33:54 PM PDT 24
Peak memory 201432 kb
Host smart-fe408c58-5e0a-4bed-95b7-eaad62d58619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789786834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1789786834
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2774168530
Short name T897
Test name
Test status
Simulation time 340148599 ps
CPU time 0.73 seconds
Started Jul 28 07:33:56 PM PDT 24
Finished Jul 28 07:33:57 PM PDT 24
Peak memory 201448 kb
Host smart-1b99e89e-f4fe-4ee3-82a4-d0d2aff25fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774168530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2774168530
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3504782319
Short name T879
Test name
Test status
Simulation time 610446911 ps
CPU time 3.19 seconds
Started Jul 28 07:33:48 PM PDT 24
Finished Jul 28 07:33:51 PM PDT 24
Peak memory 201836 kb
Host smart-eb3ff0fe-20d6-419b-a06f-a62ecf4e4aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504782319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3504782319
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1563357766
Short name T48
Test name
Test status
Simulation time 4106683176 ps
CPU time 10.24 seconds
Started Jul 28 07:33:54 PM PDT 24
Finished Jul 28 07:34:04 PM PDT 24
Peak memory 201828 kb
Host smart-0fdf9359-1597-49a1-8f57-dff36e6bd4cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563357766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1563357766
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2790349552
Short name T117
Test name
Test status
Simulation time 984574941 ps
CPU time 4.7 seconds
Started Jul 28 07:33:56 PM PDT 24
Finished Jul 28 07:34:01 PM PDT 24
Peak memory 201684 kb
Host smart-baba39c3-ed3a-4d34-9a31-9ecab95f6d17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790349552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2790349552
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.883790891
Short name T833
Test name
Test status
Simulation time 27235418782 ps
CPU time 20.17 seconds
Started Jul 28 07:33:53 PM PDT 24
Finished Jul 28 07:34:13 PM PDT 24
Peak memory 201752 kb
Host smart-61e0a071-f498-41ef-bc6c-ffa87edf2ab8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883790891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.883790891
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3524580524
Short name T917
Test name
Test status
Simulation time 1276862231 ps
CPU time 3.77 seconds
Started Jul 28 07:33:52 PM PDT 24
Finished Jul 28 07:33:56 PM PDT 24
Peak memory 201660 kb
Host smart-dff32ab7-c3e9-4b6d-8169-c4416dece243
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524580524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3524580524
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2351410045
Short name T79
Test name
Test status
Simulation time 407967694 ps
CPU time 1.04 seconds
Started Jul 28 07:33:59 PM PDT 24
Finished Jul 28 07:34:00 PM PDT 24
Peak memory 201576 kb
Host smart-e09d5b11-82fc-4937-8645-01c795c45307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351410045 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2351410045
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.440597510
Short name T915
Test name
Test status
Simulation time 541903754 ps
CPU time 2.02 seconds
Started Jul 28 07:33:54 PM PDT 24
Finished Jul 28 07:33:56 PM PDT 24
Peak memory 201472 kb
Host smart-77ce8246-e133-483d-a64e-d5a8a6fb0f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440597510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.440597510
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2680357699
Short name T799
Test name
Test status
Simulation time 461775839 ps
CPU time 1.57 seconds
Started Jul 28 07:33:53 PM PDT 24
Finished Jul 28 07:33:54 PM PDT 24
Peak memory 201428 kb
Host smart-6b4ee5f5-f947-4e5f-a554-cf98808e9f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680357699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2680357699
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3750204580
Short name T900
Test name
Test status
Simulation time 2118512011 ps
CPU time 3.4 seconds
Started Jul 28 07:33:54 PM PDT 24
Finished Jul 28 07:33:58 PM PDT 24
Peak memory 201512 kb
Host smart-b9924575-be3b-4724-bc56-49520d563e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750204580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3750204580
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.375844948
Short name T903
Test name
Test status
Simulation time 634568112 ps
CPU time 3.3 seconds
Started Jul 28 07:33:55 PM PDT 24
Finished Jul 28 07:33:59 PM PDT 24
Peak memory 201712 kb
Host smart-46a8bd22-e172-48ce-942b-a8751d7b96a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375844948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.375844948
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2611427025
Short name T358
Test name
Test status
Simulation time 8227636955 ps
CPU time 17.82 seconds
Started Jul 28 07:33:54 PM PDT 24
Finished Jul 28 07:34:12 PM PDT 24
Peak memory 201772 kb
Host smart-ca40209d-6a4d-406b-ab1b-36e259a34db9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611427025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2611427025
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.170891234
Short name T904
Test name
Test status
Simulation time 546594711 ps
CPU time 2.27 seconds
Started Jul 28 07:34:22 PM PDT 24
Finished Jul 28 07:34:25 PM PDT 24
Peak memory 201588 kb
Host smart-0aabecc3-a99d-4f52-98c4-49fde644b523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170891234 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.170891234
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3234408554
Short name T120
Test name
Test status
Simulation time 523370097 ps
CPU time 1.85 seconds
Started Jul 28 07:34:24 PM PDT 24
Finished Jul 28 07:34:26 PM PDT 24
Peak memory 201368 kb
Host smart-e88dabec-5952-4296-9054-adfe7ecdbf2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234408554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3234408554
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1928239691
Short name T811
Test name
Test status
Simulation time 400909889 ps
CPU time 1.02 seconds
Started Jul 28 07:34:21 PM PDT 24
Finished Jul 28 07:34:22 PM PDT 24
Peak memory 201420 kb
Host smart-ac968e65-f79f-4f3b-8c47-69a4e859fa38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928239691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1928239691
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.563295349
Short name T820
Test name
Test status
Simulation time 3827091314 ps
CPU time 4.34 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201736 kb
Host smart-354cf1c0-4f3f-4972-898f-ee51ac018a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563295349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.563295349
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4162367270
Short name T893
Test name
Test status
Simulation time 4622742798 ps
CPU time 6.5 seconds
Started Jul 28 07:34:22 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201844 kb
Host smart-a9bf3ece-f380-4d4b-b028-f8698b2cc83b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162367270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4162367270
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1169147184
Short name T61
Test name
Test status
Simulation time 439687767 ps
CPU time 1.25 seconds
Started Jul 28 07:34:28 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201632 kb
Host smart-e1e7ded4-3853-4fab-905d-5abbac88bc16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169147184 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1169147184
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3607163430
Short name T122
Test name
Test status
Simulation time 361268427 ps
CPU time 1.02 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:30 PM PDT 24
Peak memory 201376 kb
Host smart-e06617ff-2732-40c1-b79f-e998209e0bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607163430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3607163430
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.268967923
Short name T916
Test name
Test status
Simulation time 338348705 ps
CPU time 1.36 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201480 kb
Host smart-4082e81b-7624-4f06-aaf0-91fc4751de68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268967923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.268967923
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3956882577
Short name T824
Test name
Test status
Simulation time 4592810180 ps
CPU time 8.74 seconds
Started Jul 28 07:34:34 PM PDT 24
Finished Jul 28 07:34:43 PM PDT 24
Peak memory 201736 kb
Host smart-ad18c95e-6698-48d6-99e2-298a49a448c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956882577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3956882577
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3611061121
Short name T60
Test name
Test status
Simulation time 547513828 ps
CPU time 3.54 seconds
Started Jul 28 07:34:28 PM PDT 24
Finished Jul 28 07:34:32 PM PDT 24
Peak memory 201760 kb
Host smart-9afdfc39-5253-43e7-a589-7ebcdb401ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611061121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3611061121
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1951876861
Short name T54
Test name
Test status
Simulation time 4922539640 ps
CPU time 2.89 seconds
Started Jul 28 07:34:26 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201800 kb
Host smart-51b3167d-e25e-464e-9c8b-d8f01e19319a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951876861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1951876861
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1870489907
Short name T847
Test name
Test status
Simulation time 372010069 ps
CPU time 1.04 seconds
Started Jul 28 07:34:30 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201604 kb
Host smart-93ae0526-be92-4f8d-8400-ee7c94566792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870489907 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1870489907
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4266452269
Short name T108
Test name
Test status
Simulation time 570732927 ps
CPU time 1.39 seconds
Started Jul 28 07:34:30 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201516 kb
Host smart-db133340-2fe4-42d1-95e1-773b1e53dc4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266452269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4266452269
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.867371289
Short name T862
Test name
Test status
Simulation time 534830637 ps
CPU time 1.26 seconds
Started Jul 28 07:34:28 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201452 kb
Host smart-60312b80-dc8e-4f48-b4d9-f5a755d4cc1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867371289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.867371289
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2087476372
Short name T887
Test name
Test status
Simulation time 2697206891 ps
CPU time 1.66 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:30 PM PDT 24
Peak memory 201588 kb
Host smart-613d9c64-02f3-41d1-89b3-542501afe0d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087476372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2087476372
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.928639601
Short name T880
Test name
Test status
Simulation time 613237730 ps
CPU time 1.76 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201788 kb
Host smart-f7e9e5e0-adfe-421f-82c5-c98e5ca3c788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928639601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.928639601
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1293487313
Short name T65
Test name
Test status
Simulation time 7700768568 ps
CPU time 11.41 seconds
Started Jul 28 07:34:28 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201740 kb
Host smart-ff7d9068-4c5b-4a3b-9858-8100dc4a262e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293487313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1293487313
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.608944950
Short name T810
Test name
Test status
Simulation time 426589097 ps
CPU time 1.76 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201584 kb
Host smart-8ff950c4-3813-4124-a870-cc21c03d6a08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608944950 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.608944950
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3909660375
Short name T861
Test name
Test status
Simulation time 488705568 ps
CPU time 1.83 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201440 kb
Host smart-7ebdf062-3570-4b3b-8ebd-d9d47c8853ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909660375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3909660375
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1767520287
Short name T802
Test name
Test status
Simulation time 338431319 ps
CPU time 0.84 seconds
Started Jul 28 07:34:30 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201496 kb
Host smart-f39add41-87ab-4537-a207-00a26c5f497c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767520287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1767520287
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3055063647
Short name T44
Test name
Test status
Simulation time 4020731406 ps
CPU time 9.7 seconds
Started Jul 28 07:34:30 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201848 kb
Host smart-763aab37-e534-42de-9b3e-6a8afaf0c8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055063647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3055063647
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3467158577
Short name T58
Test name
Test status
Simulation time 517287956 ps
CPU time 3.4 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:32 PM PDT 24
Peak memory 201872 kb
Host smart-377bf096-ac3e-4980-9749-2b1bc5edf33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467158577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3467158577
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2581767634
Short name T866
Test name
Test status
Simulation time 4831652396 ps
CPU time 4.1 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201908 kb
Host smart-981bac86-b6c6-4537-a35e-d35ed29b2fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581767634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2581767634
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.670862030
Short name T914
Test name
Test status
Simulation time 487741519 ps
CPU time 1.94 seconds
Started Jul 28 07:34:31 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 201584 kb
Host smart-ac243c42-5f93-476c-b6c0-bf663d0f7c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670862030 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.670862030
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2422785396
Short name T859
Test name
Test status
Simulation time 413016576 ps
CPU time 1.25 seconds
Started Jul 28 07:34:26 PM PDT 24
Finished Jul 28 07:34:28 PM PDT 24
Peak memory 201500 kb
Host smart-ca2dfa21-83c0-4d75-9914-b3b3711a3913
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422785396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2422785396
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.194548810
Short name T801
Test name
Test status
Simulation time 505062802 ps
CPU time 0.84 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:30 PM PDT 24
Peak memory 201396 kb
Host smart-8da36ba8-8a81-4cbb-a423-39f60a8d8f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194548810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.194548810
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2119327052
Short name T860
Test name
Test status
Simulation time 5322356654 ps
CPU time 15.69 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 201760 kb
Host smart-80cfc3a7-d275-453d-a353-ea9ebf1bfe85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119327052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2119327052
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4141407700
Short name T909
Test name
Test status
Simulation time 1071909726 ps
CPU time 3.27 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:30 PM PDT 24
Peak memory 210032 kb
Host smart-fbbbc436-82b0-41ba-a865-f0e1433f2f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141407700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4141407700
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2226779381
Short name T872
Test name
Test status
Simulation time 326463176 ps
CPU time 1.31 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:34 PM PDT 24
Peak memory 201588 kb
Host smart-5f71040d-80ec-4788-9e84-d3a4623000ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226779381 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2226779381
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2194324439
Short name T878
Test name
Test status
Simulation time 316639635 ps
CPU time 1.44 seconds
Started Jul 28 07:34:29 PM PDT 24
Finished Jul 28 07:34:31 PM PDT 24
Peak memory 201452 kb
Host smart-33a8a8db-b3d8-4ff0-a5d4-a312583ab9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194324439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2194324439
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3647500127
Short name T836
Test name
Test status
Simulation time 316723644 ps
CPU time 0.74 seconds
Started Jul 28 07:34:37 PM PDT 24
Finished Jul 28 07:34:37 PM PDT 24
Peak memory 201400 kb
Host smart-77c8cb76-cac4-4256-bca6-3068b4484eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647500127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3647500127
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3939717087
Short name T848
Test name
Test status
Simulation time 2561177256 ps
CPU time 5.44 seconds
Started Jul 28 07:34:34 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201524 kb
Host smart-ad3a373f-085f-4122-9262-13f88c9231ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939717087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3939717087
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3772647518
Short name T829
Test name
Test status
Simulation time 686335512 ps
CPU time 2.44 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:35 PM PDT 24
Peak memory 201892 kb
Host smart-0f5fa3e1-7383-44ef-9744-6f94af36fb37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772647518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3772647518
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3655105357
Short name T882
Test name
Test status
Simulation time 4489499589 ps
CPU time 4.1 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:36 PM PDT 24
Peak memory 201992 kb
Host smart-ddd375ae-9bef-44dd-bef2-8c04c8c40b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655105357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3655105357
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3805898321
Short name T898
Test name
Test status
Simulation time 463923472 ps
CPU time 1.18 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 210684 kb
Host smart-0f62e1b6-c259-4f4a-a62c-d6fdd6da0f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805898321 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3805898321
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.375527839
Short name T112
Test name
Test status
Simulation time 358578502 ps
CPU time 0.93 seconds
Started Jul 28 07:34:33 PM PDT 24
Finished Jul 28 07:34:34 PM PDT 24
Peak memory 201472 kb
Host smart-31e4be88-f3ee-421b-ba5f-e7f8072a742c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375527839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.375527839
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.533690113
Short name T841
Test name
Test status
Simulation time 383508620 ps
CPU time 0.98 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 201668 kb
Host smart-84ec3b37-cd64-4c80-b366-26eb019c70ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533690113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.533690113
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1557635592
Short name T873
Test name
Test status
Simulation time 3341255568 ps
CPU time 8.13 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201892 kb
Host smart-5ce5c9b7-ddc2-4f93-a53e-0f270c616772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557635592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1557635592
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.379022048
Short name T846
Test name
Test status
Simulation time 840828689 ps
CPU time 2.54 seconds
Started Jul 28 07:34:30 PM PDT 24
Finished Jul 28 07:34:32 PM PDT 24
Peak memory 201896 kb
Host smart-5b378146-a857-439f-b5f8-2ad29d431263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379022048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.379022048
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.928449523
Short name T906
Test name
Test status
Simulation time 4748203423 ps
CPU time 4.1 seconds
Started Jul 28 07:34:35 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201776 kb
Host smart-1cce176d-0376-4bc1-b7a8-2a09453d0e26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928449523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.928449523
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3147419613
Short name T90
Test name
Test status
Simulation time 560350534 ps
CPU time 2.19 seconds
Started Jul 28 07:34:36 PM PDT 24
Finished Jul 28 07:34:38 PM PDT 24
Peak memory 201624 kb
Host smart-de6a0d0d-2044-4352-8fe2-663f09b3b417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147419613 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3147419613
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.986791931
Short name T837
Test name
Test status
Simulation time 328512929 ps
CPU time 1.55 seconds
Started Jul 28 07:34:37 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201412 kb
Host smart-5574c917-bce2-41c9-b50f-06d097822a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986791931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.986791931
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4161046187
Short name T894
Test name
Test status
Simulation time 452483282 ps
CPU time 0.72 seconds
Started Jul 28 07:34:32 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 201500 kb
Host smart-428a7c1e-ef0e-4e26-973f-a649b999b30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161046187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4161046187
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3772010190
Short name T913
Test name
Test status
Simulation time 4131448735 ps
CPU time 8.82 seconds
Started Jul 28 07:34:40 PM PDT 24
Finished Jul 28 07:34:49 PM PDT 24
Peak memory 201824 kb
Host smart-d48de37a-527d-40b0-b69c-2463839c0d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772010190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3772010190
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1255071402
Short name T868
Test name
Test status
Simulation time 1217677451 ps
CPU time 1.64 seconds
Started Jul 28 07:34:34 PM PDT 24
Finished Jul 28 07:34:35 PM PDT 24
Peak memory 201752 kb
Host smart-985b4a0f-9d0f-4590-9226-7f4c0dc7ce9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255071402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1255071402
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3072912038
Short name T359
Test name
Test status
Simulation time 10152594976 ps
CPU time 3.98 seconds
Started Jul 28 07:34:34 PM PDT 24
Finished Jul 28 07:34:38 PM PDT 24
Peak memory 201836 kb
Host smart-7f0b2bc5-c07b-403c-90aa-0f9198003fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072912038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3072912038
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.780459548
Short name T920
Test name
Test status
Simulation time 548967421 ps
CPU time 1.42 seconds
Started Jul 28 07:34:38 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201528 kb
Host smart-8b3f887f-cba5-4c01-a558-d53161238887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780459548 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.780459548
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2503518249
Short name T109
Test name
Test status
Simulation time 520737961 ps
CPU time 1.19 seconds
Started Jul 28 07:34:39 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201436 kb
Host smart-8b08927d-f1d7-4dc9-99ce-8e199fdea271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503518249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2503518249
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1578354062
Short name T804
Test name
Test status
Simulation time 427533843 ps
CPU time 0.69 seconds
Started Jul 28 07:34:38 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201456 kb
Host smart-f634b5b1-104a-4b68-97e2-c932b55c8452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578354062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1578354062
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3013889249
Short name T886
Test name
Test status
Simulation time 2219471195 ps
CPU time 7.61 seconds
Started Jul 28 07:34:37 PM PDT 24
Finished Jul 28 07:34:45 PM PDT 24
Peak memory 201580 kb
Host smart-ba5ba0b7-a442-4e4e-8a42-dc6eec7a33d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013889249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3013889249
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.511996624
Short name T52
Test name
Test status
Simulation time 566518971 ps
CPU time 2.67 seconds
Started Jul 28 07:34:37 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201780 kb
Host smart-1af70be1-8fbc-4f5b-9eaf-3ebb319f50a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511996624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.511996624
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2534238320
Short name T80
Test name
Test status
Simulation time 443055666 ps
CPU time 2 seconds
Started Jul 28 07:34:41 PM PDT 24
Finished Jul 28 07:34:43 PM PDT 24
Peak memory 201628 kb
Host smart-cf205562-9738-4b4f-8a1e-13bdc96f6a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534238320 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2534238320
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2269016891
Short name T869
Test name
Test status
Simulation time 467918192 ps
CPU time 1.78 seconds
Started Jul 28 07:34:38 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201452 kb
Host smart-5bc8ee00-e27b-49d2-9fbd-8e10e3779ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269016891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2269016891
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3987266489
Short name T803
Test name
Test status
Simulation time 549041521 ps
CPU time 0.88 seconds
Started Jul 28 07:34:38 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 201428 kb
Host smart-6840f5e0-eff3-450c-8955-51e7cf8bd832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987266489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3987266489
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1874873996
Short name T845
Test name
Test status
Simulation time 2574609079 ps
CPU time 6.6 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 201564 kb
Host smart-57002587-9530-4dfa-9af2-6d4a2cb3d124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874873996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1874873996
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3899342334
Short name T53
Test name
Test status
Simulation time 683657362 ps
CPU time 1.95 seconds
Started Jul 28 07:34:40 PM PDT 24
Finished Jul 28 07:34:42 PM PDT 24
Peak memory 201852 kb
Host smart-81cac086-833f-4648-9285-b76ebdfe54cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899342334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3899342334
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3667853919
Short name T857
Test name
Test status
Simulation time 4324984111 ps
CPU time 4.01 seconds
Started Jul 28 07:34:37 PM PDT 24
Finished Jul 28 07:34:41 PM PDT 24
Peak memory 201836 kb
Host smart-e815456a-8760-4deb-a1eb-d62154c9b894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667853919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3667853919
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3612800833
Short name T853
Test name
Test status
Simulation time 854428828 ps
CPU time 3.87 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:34:02 PM PDT 24
Peak memory 201672 kb
Host smart-ef559317-95fc-470c-bffc-08b9e78ea99f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612800833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3612800833
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2563068968
Short name T875
Test name
Test status
Simulation time 742832230 ps
CPU time 2.44 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:34:00 PM PDT 24
Peak memory 201504 kb
Host smart-53cd2e23-a180-4d18-8c9d-490c21708979
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563068968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2563068968
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3808986804
Short name T881
Test name
Test status
Simulation time 471288454 ps
CPU time 1.14 seconds
Started Jul 28 07:34:04 PM PDT 24
Finished Jul 28 07:34:06 PM PDT 24
Peak memory 201576 kb
Host smart-3ad10069-e42b-4612-a353-ec031b33e420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808986804 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3808986804
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3323010331
Short name T116
Test name
Test status
Simulation time 589280785 ps
CPU time 0.92 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:33:59 PM PDT 24
Peak memory 201472 kb
Host smart-14b033c7-d55b-47cc-8d80-05e6e303a1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323010331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3323010331
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.215750785
Short name T812
Test name
Test status
Simulation time 364187427 ps
CPU time 1.44 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:33:59 PM PDT 24
Peak memory 201400 kb
Host smart-905b40f2-671d-44bf-922c-7f8d9086ec13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215750785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.215750785
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4139957333
Short name T840
Test name
Test status
Simulation time 1919846216 ps
CPU time 1.66 seconds
Started Jul 28 07:33:59 PM PDT 24
Finished Jul 28 07:34:00 PM PDT 24
Peak memory 201532 kb
Host smart-fb2dde4f-64ae-422d-9dbf-069fb9c755aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139957333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4139957333
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2380136922
Short name T64
Test name
Test status
Simulation time 487265113 ps
CPU time 3.25 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:34:01 PM PDT 24
Peak memory 201812 kb
Host smart-84381c66-7682-42b5-9354-2a4226eaaf93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380136922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2380136922
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2291267474
Short name T361
Test name
Test status
Simulation time 4214907697 ps
CPU time 6.23 seconds
Started Jul 28 07:33:58 PM PDT 24
Finished Jul 28 07:34:05 PM PDT 24
Peak memory 201784 kb
Host smart-e93b26c0-1886-42c0-b452-358b163f1c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291267474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2291267474
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3380901840
Short name T852
Test name
Test status
Simulation time 333999784 ps
CPU time 1 seconds
Started Jul 28 07:34:44 PM PDT 24
Finished Jul 28 07:34:45 PM PDT 24
Peak memory 201376 kb
Host smart-7df2fbda-3e7f-4b92-8896-feb24e779499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380901840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3380901840
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1641408710
Short name T855
Test name
Test status
Simulation time 387348169 ps
CPU time 1.43 seconds
Started Jul 28 07:34:42 PM PDT 24
Finished Jul 28 07:34:44 PM PDT 24
Peak memory 201476 kb
Host smart-7a14ef77-d44f-48f8-956a-7d8032d72ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641408710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1641408710
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2590709090
Short name T827
Test name
Test status
Simulation time 526487051 ps
CPU time 0.92 seconds
Started Jul 28 07:34:48 PM PDT 24
Finished Jul 28 07:34:49 PM PDT 24
Peak memory 201428 kb
Host smart-7268d911-5049-4d7b-83bf-2c894dc8a732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590709090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2590709090
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1939408518
Short name T877
Test name
Test status
Simulation time 377705820 ps
CPU time 1.54 seconds
Started Jul 28 07:34:41 PM PDT 24
Finished Jul 28 07:34:43 PM PDT 24
Peak memory 201496 kb
Host smart-6a43162b-8c7d-481b-a669-36ff5d896235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939408518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1939408518
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3334601628
Short name T835
Test name
Test status
Simulation time 518690077 ps
CPU time 1.02 seconds
Started Jul 28 07:34:40 PM PDT 24
Finished Jul 28 07:34:41 PM PDT 24
Peak memory 201636 kb
Host smart-2be42602-4a0b-4f00-91c6-b54bf0b1359d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334601628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3334601628
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2250022322
Short name T891
Test name
Test status
Simulation time 340189177 ps
CPU time 1.19 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201472 kb
Host smart-06ac276e-45af-45b0-9d09-a33c867bb41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250022322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2250022322
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.712709708
Short name T831
Test name
Test status
Simulation time 393310884 ps
CPU time 1.57 seconds
Started Jul 28 07:34:40 PM PDT 24
Finished Jul 28 07:34:42 PM PDT 24
Peak memory 201468 kb
Host smart-3c3aa9a3-ef13-4d53-89bb-c7cf17f51f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712709708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.712709708
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2826696086
Short name T908
Test name
Test status
Simulation time 315101773 ps
CPU time 1.05 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 201428 kb
Host smart-9b777bcb-6bbb-4fbd-91ff-13631abea5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826696086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2826696086
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.831022642
Short name T851
Test name
Test status
Simulation time 380642866 ps
CPU time 0.83 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201440 kb
Host smart-8086518f-0f3d-4678-b8f2-24af089cae1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831022642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.831022642
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3669482928
Short name T814
Test name
Test status
Simulation time 352042258 ps
CPU time 1.48 seconds
Started Jul 28 07:34:49 PM PDT 24
Finished Jul 28 07:34:50 PM PDT 24
Peak memory 201428 kb
Host smart-2e57aeba-66a2-459f-9e26-72dec2d70939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669482928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3669482928
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3032283146
Short name T828
Test name
Test status
Simulation time 1159602434 ps
CPU time 2.53 seconds
Started Jul 28 07:34:03 PM PDT 24
Finished Jul 28 07:34:06 PM PDT 24
Peak memory 201728 kb
Host smart-ca6f661d-9f4c-47f0-941b-e3f3eb710bb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032283146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3032283146
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3669291042
Short name T114
Test name
Test status
Simulation time 24251124363 ps
CPU time 16.74 seconds
Started Jul 28 07:34:03 PM PDT 24
Finished Jul 28 07:34:20 PM PDT 24
Peak memory 201656 kb
Host smart-d9b23a7f-5637-4540-bb12-34d7cdf73242
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669291042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3669291042
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.77779777
Short name T896
Test name
Test status
Simulation time 817367100 ps
CPU time 1.66 seconds
Started Jul 28 07:34:04 PM PDT 24
Finished Jul 28 07:34:06 PM PDT 24
Peak memory 201480 kb
Host smart-2129e957-a5e5-4675-8cd4-9998325f64db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77779777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_res
et.77779777
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.36543227
Short name T892
Test name
Test status
Simulation time 402949904 ps
CPU time 1.42 seconds
Started Jul 28 07:34:02 PM PDT 24
Finished Jul 28 07:34:04 PM PDT 24
Peak memory 209832 kb
Host smart-319e6380-3bc8-4d05-a595-9a0995096f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36543227 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.36543227
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3652940861
Short name T115
Test name
Test status
Simulation time 563725917 ps
CPU time 2.02 seconds
Started Jul 28 07:34:05 PM PDT 24
Finished Jul 28 07:34:07 PM PDT 24
Peak memory 201472 kb
Host smart-1d9d653c-8d9b-473e-88ae-1050d1af8933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652940861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3652940861
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1162328312
Short name T839
Test name
Test status
Simulation time 504937213 ps
CPU time 1.72 seconds
Started Jul 28 07:34:05 PM PDT 24
Finished Jul 28 07:34:06 PM PDT 24
Peak memory 201464 kb
Host smart-3ec8c0df-edd4-473b-9e37-7ff94a3e9927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162328312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1162328312
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2810060576
Short name T46
Test name
Test status
Simulation time 2156671848 ps
CPU time 6.8 seconds
Started Jul 28 07:34:04 PM PDT 24
Finished Jul 28 07:34:10 PM PDT 24
Peak memory 201592 kb
Host smart-b53cfa49-95fe-4093-9aaf-40aad09f7d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810060576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2810060576
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.432999518
Short name T844
Test name
Test status
Simulation time 476630056 ps
CPU time 1.85 seconds
Started Jul 28 07:34:06 PM PDT 24
Finished Jul 28 07:34:08 PM PDT 24
Peak memory 201840 kb
Host smart-ff5b14d2-17e4-4264-9a2b-27e95e192c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432999518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.432999518
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2753065873
Short name T902
Test name
Test status
Simulation time 9334896918 ps
CPU time 5.37 seconds
Started Jul 28 07:34:04 PM PDT 24
Finished Jul 28 07:34:09 PM PDT 24
Peak memory 201800 kb
Host smart-bff54d5d-b724-4094-8ff0-8aac243aea88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753065873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2753065873
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.426656459
Short name T918
Test name
Test status
Simulation time 369389137 ps
CPU time 0.81 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:45 PM PDT 24
Peak memory 201432 kb
Host smart-8161790d-f3fb-456b-adac-653826023e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426656459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.426656459
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2033389997
Short name T805
Test name
Test status
Simulation time 348312315 ps
CPU time 1.02 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201480 kb
Host smart-0e648927-d199-4507-808d-0fd63e514824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033389997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2033389997
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3438214190
Short name T800
Test name
Test status
Simulation time 511372763 ps
CPU time 1.16 seconds
Started Jul 28 07:34:39 PM PDT 24
Finished Jul 28 07:34:40 PM PDT 24
Peak memory 201508 kb
Host smart-f75ae16e-ea00-46ff-b157-2e7d8a205257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438214190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3438214190
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3666366495
Short name T901
Test name
Test status
Simulation time 390554540 ps
CPU time 1.17 seconds
Started Jul 28 07:34:44 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201444 kb
Host smart-48475fd0-7077-44de-aecb-a6e7a8067587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666366495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3666366495
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3580022893
Short name T874
Test name
Test status
Simulation time 433161326 ps
CPU time 1.13 seconds
Started Jul 28 07:34:42 PM PDT 24
Finished Jul 28 07:34:43 PM PDT 24
Peak memory 201396 kb
Host smart-8e322712-617a-4bca-a177-1d0e18aa90f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580022893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3580022893
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.27731345
Short name T838
Test name
Test status
Simulation time 428490702 ps
CPU time 1.03 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:49 PM PDT 24
Peak memory 201428 kb
Host smart-e028c45d-b487-4f5c-89e1-4f21b563e2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27731345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.27731345
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4042234944
Short name T858
Test name
Test status
Simulation time 396303491 ps
CPU time 1.47 seconds
Started Jul 28 07:34:44 PM PDT 24
Finished Jul 28 07:34:45 PM PDT 24
Peak memory 201392 kb
Host smart-75da3f9a-182c-4df5-beaf-848d33e20d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042234944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4042234944
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3392130272
Short name T883
Test name
Test status
Simulation time 281964546 ps
CPU time 1.32 seconds
Started Jul 28 07:34:48 PM PDT 24
Finished Jul 28 07:34:49 PM PDT 24
Peak memory 201404 kb
Host smart-71f488b0-5a90-4176-8b4a-d2a82af5f09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392130272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3392130272
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1657840813
Short name T816
Test name
Test status
Simulation time 337338222 ps
CPU time 1.46 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:49 PM PDT 24
Peak memory 201372 kb
Host smart-edeb81ab-44df-4f83-8035-6663f997d1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657840813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1657840813
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.707199280
Short name T890
Test name
Test status
Simulation time 599593944 ps
CPU time 0.74 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201516 kb
Host smart-0e57ed98-4de9-4e07-96b9-9105c006d9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707199280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.707199280
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3833496153
Short name T850
Test name
Test status
Simulation time 1297968319 ps
CPU time 5.06 seconds
Started Jul 28 07:34:08 PM PDT 24
Finished Jul 28 07:34:13 PM PDT 24
Peak memory 201688 kb
Host smart-3ed97f7d-57cb-445b-b8be-32f2f8ea688f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833496153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3833496153
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1982505914
Short name T818
Test name
Test status
Simulation time 53059728136 ps
CPU time 172.85 seconds
Started Jul 28 07:34:10 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 201716 kb
Host smart-59849795-d8ac-4f3f-a91c-914a885f3284
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982505914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1982505914
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2693201643
Short name T884
Test name
Test status
Simulation time 1237321224 ps
CPU time 2.28 seconds
Started Jul 28 07:34:08 PM PDT 24
Finished Jul 28 07:34:11 PM PDT 24
Peak memory 201504 kb
Host smart-93d8e210-39e6-4ae5-9b5a-2cc05af08c93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693201643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2693201643
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2295346297
Short name T842
Test name
Test status
Simulation time 431224951 ps
CPU time 1.76 seconds
Started Jul 28 07:34:09 PM PDT 24
Finished Jul 28 07:34:11 PM PDT 24
Peak memory 201576 kb
Host smart-b4f5b723-e58d-42bf-a2b4-d642e67ef9b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295346297 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2295346297
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3722879627
Short name T113
Test name
Test status
Simulation time 482499613 ps
CPU time 1.73 seconds
Started Jul 28 07:34:10 PM PDT 24
Finished Jul 28 07:34:12 PM PDT 24
Peak memory 201424 kb
Host smart-3bfa3a6f-2338-4b30-862e-d2456faad820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722879627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3722879627
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3255544599
Short name T865
Test name
Test status
Simulation time 376971723 ps
CPU time 0.65 seconds
Started Jul 28 07:34:08 PM PDT 24
Finished Jul 28 07:34:09 PM PDT 24
Peak memory 201432 kb
Host smart-8076b159-b1be-4ee5-af8e-a8ce73b9f040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255544599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3255544599
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4028292673
Short name T864
Test name
Test status
Simulation time 4391917862 ps
CPU time 5.32 seconds
Started Jul 28 07:34:09 PM PDT 24
Finished Jul 28 07:34:15 PM PDT 24
Peak memory 201780 kb
Host smart-3adfbc15-d3ec-4779-af0b-cadc3adbfe9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028292673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4028292673
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.628567613
Short name T911
Test name
Test status
Simulation time 491445781 ps
CPU time 3.45 seconds
Started Jul 28 07:34:03 PM PDT 24
Finished Jul 28 07:34:06 PM PDT 24
Peak memory 211220 kb
Host smart-881c354e-5206-4552-b624-26adc51b6519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628567613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.628567613
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3789619757
Short name T849
Test name
Test status
Simulation time 7932357267 ps
CPU time 19.98 seconds
Started Jul 28 07:34:08 PM PDT 24
Finished Jul 28 07:34:28 PM PDT 24
Peak memory 201784 kb
Host smart-167f0382-f71b-4bed-8656-65543680aa53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789619757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3789619757
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.45863257
Short name T807
Test name
Test status
Simulation time 319462939 ps
CPU time 1.04 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201524 kb
Host smart-53bc03c0-9a02-4b02-b0c1-b994e88e9a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45863257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.45863257
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3809303463
Short name T819
Test name
Test status
Simulation time 319645293 ps
CPU time 0.82 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201472 kb
Host smart-35bbcd52-5198-4ee7-8e75-e087539dfe71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809303463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3809303463
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3979775646
Short name T871
Test name
Test status
Simulation time 472541498 ps
CPU time 0.82 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201436 kb
Host smart-bc64d872-e337-44ab-a7a8-085a7217c328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979775646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3979775646
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2596094875
Short name T821
Test name
Test status
Simulation time 523913252 ps
CPU time 0.9 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201496 kb
Host smart-59655d10-a645-4def-a1b2-4226e5e66d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596094875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2596094875
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1407873274
Short name T830
Test name
Test status
Simulation time 507295060 ps
CPU time 1.82 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:47 PM PDT 24
Peak memory 201472 kb
Host smart-f79a4b23-ea3c-4939-9f09-48cc32a2dca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407873274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1407873274
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3906368547
Short name T899
Test name
Test status
Simulation time 438897134 ps
CPU time 1.49 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 201428 kb
Host smart-efcb0473-b8b2-4e99-9258-ab0920e1e8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906368547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3906368547
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4150346580
Short name T863
Test name
Test status
Simulation time 459350688 ps
CPU time 1.69 seconds
Started Jul 28 07:34:49 PM PDT 24
Finished Jul 28 07:34:51 PM PDT 24
Peak memory 201476 kb
Host smart-878695d1-823b-45e5-8aa1-4a72312cabbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150346580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4150346580
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1130278522
Short name T815
Test name
Test status
Simulation time 409257178 ps
CPU time 0.89 seconds
Started Jul 28 07:34:45 PM PDT 24
Finished Jul 28 07:34:46 PM PDT 24
Peak memory 201436 kb
Host smart-43bb5496-608c-4c02-aeff-2069b6b8c784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130278522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1130278522
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4170567824
Short name T912
Test name
Test status
Simulation time 319754026 ps
CPU time 1.29 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 201460 kb
Host smart-7247a2fc-aaa0-40bb-9af9-076e13a27bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170567824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.4170567824
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.277763771
Short name T888
Test name
Test status
Simulation time 365231108 ps
CPU time 1.48 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 201432 kb
Host smart-2fe9cb92-467b-4cd1-a00d-7fec907c9ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277763771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.277763771
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.896036866
Short name T826
Test name
Test status
Simulation time 408359001 ps
CPU time 1.85 seconds
Started Jul 28 07:34:13 PM PDT 24
Finished Jul 28 07:34:15 PM PDT 24
Peak memory 201648 kb
Host smart-f149ae4f-0280-42da-8767-84a0d339893b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896036866 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.896036866
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2994878294
Short name T119
Test name
Test status
Simulation time 416269926 ps
CPU time 1.58 seconds
Started Jul 28 07:34:10 PM PDT 24
Finished Jul 28 07:34:12 PM PDT 24
Peak memory 201460 kb
Host smart-3ae7e780-0fee-41de-ad31-6d5bf7343e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994878294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2994878294
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1839064163
Short name T910
Test name
Test status
Simulation time 361169119 ps
CPU time 1.49 seconds
Started Jul 28 07:34:11 PM PDT 24
Finished Jul 28 07:34:12 PM PDT 24
Peak memory 201396 kb
Host smart-efb41910-0828-4fb5-84b4-1c4a6a910213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839064163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1839064163
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4260825326
Short name T889
Test name
Test status
Simulation time 3999057711 ps
CPU time 4.68 seconds
Started Jul 28 07:34:14 PM PDT 24
Finished Jul 28 07:34:19 PM PDT 24
Peak memory 201764 kb
Host smart-540c6b56-455c-4e5d-be28-57e58171c80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260825326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4260825326
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3493810097
Short name T834
Test name
Test status
Simulation time 825903103 ps
CPU time 2.09 seconds
Started Jul 28 07:34:06 PM PDT 24
Finished Jul 28 07:34:08 PM PDT 24
Peak memory 201844 kb
Host smart-d5b738d4-b951-4d83-b262-95159e14a00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493810097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3493810097
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2749102348
Short name T50
Test name
Test status
Simulation time 8530889644 ps
CPU time 22.19 seconds
Started Jul 28 07:34:10 PM PDT 24
Finished Jul 28 07:34:32 PM PDT 24
Peak memory 201780 kb
Host smart-86dfaca4-928b-4bbb-9411-672e6e047b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749102348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2749102348
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1263113596
Short name T856
Test name
Test status
Simulation time 467946380 ps
CPU time 1.04 seconds
Started Jul 28 07:34:15 PM PDT 24
Finished Jul 28 07:34:16 PM PDT 24
Peak memory 201584 kb
Host smart-3a2654bc-3dce-452d-8ed9-47fa2548f0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263113596 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1263113596
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4202435310
Short name T107
Test name
Test status
Simulation time 529022447 ps
CPU time 1.11 seconds
Started Jul 28 07:34:13 PM PDT 24
Finished Jul 28 07:34:14 PM PDT 24
Peak memory 201468 kb
Host smart-8b710da8-9eaf-4cde-b90a-4ee2056051c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202435310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4202435310
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2858485180
Short name T822
Test name
Test status
Simulation time 435419950 ps
CPU time 0.92 seconds
Started Jul 28 07:34:14 PM PDT 24
Finished Jul 28 07:34:15 PM PDT 24
Peak memory 201444 kb
Host smart-bc6df013-a877-4d94-be53-a63e97c04291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858485180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2858485180
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3197987081
Short name T832
Test name
Test status
Simulation time 2814532110 ps
CPU time 1.87 seconds
Started Jul 28 07:34:14 PM PDT 24
Finished Jul 28 07:34:16 PM PDT 24
Peak memory 201564 kb
Host smart-0a211f81-f804-49c7-b204-00b4803aa871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197987081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3197987081
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2209215073
Short name T66
Test name
Test status
Simulation time 8078614457 ps
CPU time 19.98 seconds
Started Jul 28 07:34:14 PM PDT 24
Finished Jul 28 07:34:34 PM PDT 24
Peak memory 201880 kb
Host smart-ad592887-6f3f-4276-97f7-985aeee94138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209215073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2209215073
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1215533055
Short name T809
Test name
Test status
Simulation time 604928517 ps
CPU time 1.41 seconds
Started Jul 28 07:34:18 PM PDT 24
Finished Jul 28 07:34:19 PM PDT 24
Peak memory 201640 kb
Host smart-962518a1-320a-4e96-abf6-d854cb64a0b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215533055 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1215533055
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.95239508
Short name T121
Test name
Test status
Simulation time 525135798 ps
CPU time 1.15 seconds
Started Jul 28 07:34:11 PM PDT 24
Finished Jul 28 07:34:12 PM PDT 24
Peak memory 201492 kb
Host smart-465d02de-9125-4743-8202-88ff7b21be24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95239508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.95239508
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2673921478
Short name T808
Test name
Test status
Simulation time 435154395 ps
CPU time 1.13 seconds
Started Jul 28 07:34:14 PM PDT 24
Finished Jul 28 07:34:15 PM PDT 24
Peak memory 201652 kb
Host smart-121b94e7-598c-4935-bbdf-ef6d9350cc84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673921478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2673921478
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2548112380
Short name T843
Test name
Test status
Simulation time 2799868986 ps
CPU time 1.8 seconds
Started Jul 28 07:34:15 PM PDT 24
Finished Jul 28 07:34:17 PM PDT 24
Peak memory 201628 kb
Host smart-133161d1-7dfc-4473-b6dc-e0d854f13645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548112380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2548112380
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3009281396
Short name T63
Test name
Test status
Simulation time 473872478 ps
CPU time 2.68 seconds
Started Jul 28 07:34:15 PM PDT 24
Finished Jul 28 07:34:17 PM PDT 24
Peak memory 201776 kb
Host smart-212b61af-cf8d-48f1-ad3f-40c251922fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009281396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3009281396
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.270501262
Short name T360
Test name
Test status
Simulation time 8471815294 ps
CPU time 21.53 seconds
Started Jul 28 07:34:15 PM PDT 24
Finished Jul 28 07:34:37 PM PDT 24
Peak memory 201768 kb
Host smart-57aa4d71-fb41-43ea-9dfc-df47fa0bd13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270501262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.270501262
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.254585645
Short name T854
Test name
Test status
Simulation time 477672606 ps
CPU time 1.94 seconds
Started Jul 28 07:34:17 PM PDT 24
Finished Jul 28 07:34:19 PM PDT 24
Peak memory 201664 kb
Host smart-65cf50f0-9d03-42c5-88fe-9b00f713ee0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254585645 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.254585645
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2788433435
Short name T919
Test name
Test status
Simulation time 480590936 ps
CPU time 1.05 seconds
Started Jul 28 07:34:17 PM PDT 24
Finished Jul 28 07:34:18 PM PDT 24
Peak memory 201632 kb
Host smart-29c47414-9062-499a-8f8f-fc332176e8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788433435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2788433435
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2861791000
Short name T806
Test name
Test status
Simulation time 488674872 ps
CPU time 0.7 seconds
Started Jul 28 07:34:18 PM PDT 24
Finished Jul 28 07:34:19 PM PDT 24
Peak memory 201504 kb
Host smart-bbbc5a81-69b0-4069-8979-94cb2f107d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861791000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2861791000
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2854584574
Short name T867
Test name
Test status
Simulation time 2215938845 ps
CPU time 3.21 seconds
Started Jul 28 07:34:18 PM PDT 24
Finished Jul 28 07:34:22 PM PDT 24
Peak memory 201640 kb
Host smart-2aa0095c-4949-4ba8-93c3-43ebc1aa56ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854584574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2854584574
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.458959436
Short name T905
Test name
Test status
Simulation time 373015590 ps
CPU time 1.6 seconds
Started Jul 28 07:34:18 PM PDT 24
Finished Jul 28 07:34:19 PM PDT 24
Peak memory 210040 kb
Host smart-cc6e5ff4-9015-4f26-a772-15c724069834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458959436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.458959436
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1920015376
Short name T870
Test name
Test status
Simulation time 4452314216 ps
CPU time 9.11 seconds
Started Jul 28 07:34:17 PM PDT 24
Finished Jul 28 07:34:26 PM PDT 24
Peak memory 201800 kb
Host smart-56fff52d-c6dd-4f36-a39c-f5f48b07b9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920015376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1920015376
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3452384547
Short name T895
Test name
Test status
Simulation time 636514715 ps
CPU time 1.19 seconds
Started Jul 28 07:34:28 PM PDT 24
Finished Jul 28 07:34:29 PM PDT 24
Peak memory 201560 kb
Host smart-6b3ccf34-88c3-4142-b84d-b67bf63184af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452384547 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3452384547
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.193887584
Short name T817
Test name
Test status
Simulation time 539529392 ps
CPU time 1.97 seconds
Started Jul 28 07:34:22 PM PDT 24
Finished Jul 28 07:34:24 PM PDT 24
Peak memory 201456 kb
Host smart-a055e241-d1b4-48a5-b9be-ad0473c2b7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193887584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.193887584
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3886490127
Short name T813
Test name
Test status
Simulation time 525790444 ps
CPU time 1.21 seconds
Started Jul 28 07:34:20 PM PDT 24
Finished Jul 28 07:34:21 PM PDT 24
Peak memory 201384 kb
Host smart-5b5843c3-b57e-40cd-846a-16d3e8f93a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886490127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3886490127
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2351403720
Short name T907
Test name
Test status
Simulation time 4610654672 ps
CPU time 5.7 seconds
Started Jul 28 07:34:27 PM PDT 24
Finished Jul 28 07:34:33 PM PDT 24
Peak memory 201700 kb
Host smart-634b050c-13b8-4365-a745-7a59e13e7715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351403720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2351403720
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2584374119
Short name T876
Test name
Test status
Simulation time 394960806 ps
CPU time 2.62 seconds
Started Jul 28 07:34:19 PM PDT 24
Finished Jul 28 07:34:22 PM PDT 24
Peak memory 201772 kb
Host smart-c1ade6a1-a396-47b4-96d6-3a23a37203ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584374119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2584374119
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3724505665
Short name T885
Test name
Test status
Simulation time 8096926944 ps
CPU time 7.32 seconds
Started Jul 28 07:34:19 PM PDT 24
Finished Jul 28 07:34:27 PM PDT 24
Peak memory 201708 kb
Host smart-5402e3a7-3d35-4145-a38f-4d71086a6bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724505665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3724505665
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3835439281
Short name T587
Test name
Test status
Simulation time 316349382 ps
CPU time 1 seconds
Started Jul 28 06:38:52 PM PDT 24
Finished Jul 28 06:38:53 PM PDT 24
Peak memory 200956 kb
Host smart-2d3c3021-d776-4869-9241-b4b8db94dfe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835439281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3835439281
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2054738058
Short name T273
Test name
Test status
Simulation time 530563665840 ps
CPU time 1057.23 seconds
Started Jul 28 06:38:43 PM PDT 24
Finished Jul 28 06:56:21 PM PDT 24
Peak memory 201176 kb
Host smart-b0e67e5b-2c52-4f37-833b-dc4a92f7182c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054738058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2054738058
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1694816370
Short name T271
Test name
Test status
Simulation time 160567746357 ps
CPU time 94.26 seconds
Started Jul 28 06:38:39 PM PDT 24
Finished Jul 28 06:40:13 PM PDT 24
Peak memory 201232 kb
Host smart-1e816b6b-eae6-40f8-aeae-90c53dd96e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694816370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1694816370
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2556942015
Short name T692
Test name
Test status
Simulation time 483084239154 ps
CPU time 1081.92 seconds
Started Jul 28 06:38:40 PM PDT 24
Finished Jul 28 06:56:43 PM PDT 24
Peak memory 201156 kb
Host smart-214cba7e-21d8-4e89-ba32-67634c15b4e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556942015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2556942015
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4138450754
Short name T278
Test name
Test status
Simulation time 495241373492 ps
CPU time 1203.48 seconds
Started Jul 28 06:38:42 PM PDT 24
Finished Jul 28 06:58:45 PM PDT 24
Peak memory 201204 kb
Host smart-c4f953bd-57c4-453d-8b9d-f451858a163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138450754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4138450754
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2188880286
Short name T202
Test name
Test status
Simulation time 329145213257 ps
CPU time 344.56 seconds
Started Jul 28 06:38:43 PM PDT 24
Finished Jul 28 06:44:27 PM PDT 24
Peak memory 201200 kb
Host smart-088489bc-18ff-4f18-9389-341654688f7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188880286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2188880286
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2370804942
Short name T573
Test name
Test status
Simulation time 594438519834 ps
CPU time 701.55 seconds
Started Jul 28 06:38:47 PM PDT 24
Finished Jul 28 06:50:29 PM PDT 24
Peak memory 201160 kb
Host smart-80235f16-8fbd-42f8-8554-0500a41631d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370804942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2370804942
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1744991716
Short name T658
Test name
Test status
Simulation time 83533744539 ps
CPU time 274.8 seconds
Started Jul 28 06:38:51 PM PDT 24
Finished Jul 28 06:43:26 PM PDT 24
Peak memory 201612 kb
Host smart-f2501f85-57b8-4a78-8c37-2bb03f8f83f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744991716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1744991716
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.70198835
Short name T368
Test name
Test status
Simulation time 27408992250 ps
CPU time 33.41 seconds
Started Jul 28 06:38:45 PM PDT 24
Finished Jul 28 06:39:18 PM PDT 24
Peak memory 201004 kb
Host smart-fa8eef8d-5ec8-4d9a-8041-c08a9bd6cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70198835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.70198835
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4088356241
Short name T519
Test name
Test status
Simulation time 5488245665 ps
CPU time 14.42 seconds
Started Jul 28 06:38:47 PM PDT 24
Finished Jul 28 06:39:01 PM PDT 24
Peak memory 200976 kb
Host smart-4a6506c0-6450-4b11-b292-9f7e3649884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088356241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4088356241
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3611453232
Short name T751
Test name
Test status
Simulation time 6202142699 ps
CPU time 3.22 seconds
Started Jul 28 06:38:39 PM PDT 24
Finished Jul 28 06:38:43 PM PDT 24
Peak memory 201028 kb
Host smart-a81a2d2b-14a0-417a-8360-8ceadc50e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611453232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3611453232
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3155357213
Short name T600
Test name
Test status
Simulation time 491951484147 ps
CPU time 103.11 seconds
Started Jul 28 06:38:50 PM PDT 24
Finished Jul 28 06:40:33 PM PDT 24
Peak memory 201092 kb
Host smart-b06cbebc-a216-4f87-9b95-8319d0789eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155357213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3155357213
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1097128659
Short name T333
Test name
Test status
Simulation time 80374360043 ps
CPU time 94.35 seconds
Started Jul 28 06:38:50 PM PDT 24
Finished Jul 28 06:40:24 PM PDT 24
Peak memory 210004 kb
Host smart-bbf6457d-a351-4989-b30b-924492c87caf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097128659 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1097128659
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2759791652
Short name T734
Test name
Test status
Simulation time 468996941 ps
CPU time 1.17 seconds
Started Jul 28 06:39:03 PM PDT 24
Finished Jul 28 06:39:04 PM PDT 24
Peak memory 201016 kb
Host smart-c1a58b67-e345-4315-9ced-0b8044c94c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759791652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2759791652
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2131071840
Short name T614
Test name
Test status
Simulation time 344394611111 ps
CPU time 807.7 seconds
Started Jul 28 06:38:58 PM PDT 24
Finished Jul 28 06:52:26 PM PDT 24
Peak memory 201160 kb
Host smart-df38373c-06a9-4a00-90f2-ed595986725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131071840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2131071840
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3244586655
Short name T509
Test name
Test status
Simulation time 324236417270 ps
CPU time 286.4 seconds
Started Jul 28 06:38:58 PM PDT 24
Finished Jul 28 06:43:44 PM PDT 24
Peak memory 201232 kb
Host smart-4d438bc8-e6c1-4103-8697-b8bbba0abe68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244586655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3244586655
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.922070315
Short name T731
Test name
Test status
Simulation time 163894996782 ps
CPU time 381.99 seconds
Started Jul 28 06:38:57 PM PDT 24
Finished Jul 28 06:45:19 PM PDT 24
Peak memory 201160 kb
Host smart-b0bfc914-1f52-4397-88f2-c860ed0fe355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922070315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.922070315
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2466504457
Short name T531
Test name
Test status
Simulation time 331343530213 ps
CPU time 142.89 seconds
Started Jul 28 06:38:57 PM PDT 24
Finished Jul 28 06:41:20 PM PDT 24
Peak memory 201088 kb
Host smart-87ad3b7c-4e9a-4901-8c9c-ddd48b26f8d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466504457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2466504457
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2992474011
Short name T612
Test name
Test status
Simulation time 348148136196 ps
CPU time 175.64 seconds
Started Jul 28 06:38:58 PM PDT 24
Finished Jul 28 06:41:53 PM PDT 24
Peak memory 201152 kb
Host smart-2b15d8e5-1033-41d0-b4fd-ab33c60c0c50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992474011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2992474011
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.382387621
Short name T451
Test name
Test status
Simulation time 40080399385 ps
CPU time 87.6 seconds
Started Jul 28 06:39:03 PM PDT 24
Finished Jul 28 06:40:31 PM PDT 24
Peak memory 200996 kb
Host smart-f697430a-ca7a-4e42-b7a0-0da5cdb5f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382387621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.382387621
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3186785991
Short name T627
Test name
Test status
Simulation time 2897516285 ps
CPU time 7.42 seconds
Started Jul 28 06:38:56 PM PDT 24
Finished Jul 28 06:39:03 PM PDT 24
Peak memory 200956 kb
Host smart-e77c9083-3e08-48b4-84ae-0f8cc7156931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186785991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3186785991
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.820809911
Short name T56
Test name
Test status
Simulation time 8334048038 ps
CPU time 18.7 seconds
Started Jul 28 06:39:02 PM PDT 24
Finished Jul 28 06:39:20 PM PDT 24
Peak memory 217884 kb
Host smart-8973f8cb-d8f1-4aa1-90f4-55a6a238e4cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820809911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.820809911
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2984189448
Short name T166
Test name
Test status
Simulation time 6147333895 ps
CPU time 14.3 seconds
Started Jul 28 06:38:51 PM PDT 24
Finished Jul 28 06:39:05 PM PDT 24
Peak memory 200984 kb
Host smart-db702c8e-70ff-4c81-b292-534bc7d1b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984189448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2984189448
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1265975129
Short name T17
Test name
Test status
Simulation time 117518298267 ps
CPU time 189.21 seconds
Started Jul 28 06:39:03 PM PDT 24
Finished Jul 28 06:42:13 PM PDT 24
Peak memory 217628 kb
Host smart-024321cc-424e-4e60-affe-e799a8b644c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265975129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1265975129
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4231909065
Short name T475
Test name
Test status
Simulation time 418551358 ps
CPU time 1.57 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:41:12 PM PDT 24
Peak memory 201000 kb
Host smart-d1e5f697-b9ed-46ff-a5fd-adf0f7023164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231909065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4231909065
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.41051343
Short name T280
Test name
Test status
Simulation time 600151909312 ps
CPU time 1238.86 seconds
Started Jul 28 06:41:05 PM PDT 24
Finished Jul 28 07:01:44 PM PDT 24
Peak memory 201204 kb
Host smart-0073d5ae-bd8b-46b5-9c49-c36af64371eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41051343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gatin
g.41051343
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2674483547
Short name T150
Test name
Test status
Simulation time 499009217083 ps
CPU time 1073.55 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:59:04 PM PDT 24
Peak memory 201168 kb
Host smart-6f6e5aba-14a2-498c-839e-c13ed0bba5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674483547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2674483547
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1623221284
Short name T668
Test name
Test status
Simulation time 326066698812 ps
CPU time 138.69 seconds
Started Jul 28 06:41:04 PM PDT 24
Finished Jul 28 06:43:23 PM PDT 24
Peak memory 201184 kb
Host smart-60aec936-fd83-4b7c-b298-7b69d14cf8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623221284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1623221284
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1913342305
Short name T418
Test name
Test status
Simulation time 318478369376 ps
CPU time 780.28 seconds
Started Jul 28 06:41:04 PM PDT 24
Finished Jul 28 06:54:05 PM PDT 24
Peak memory 201152 kb
Host smart-a8913149-2876-4ada-b99f-e7477dbdca54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913342305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1913342305
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2990038160
Short name T132
Test name
Test status
Simulation time 497509334128 ps
CPU time 275.1 seconds
Started Jul 28 06:40:57 PM PDT 24
Finished Jul 28 06:45:32 PM PDT 24
Peak memory 201092 kb
Host smart-0ab91e14-bd07-407a-ae66-1bf22d81691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990038160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2990038160
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1582549270
Short name T463
Test name
Test status
Simulation time 499052848566 ps
CPU time 604.99 seconds
Started Jul 28 06:41:05 PM PDT 24
Finished Jul 28 06:51:10 PM PDT 24
Peak memory 201160 kb
Host smart-42afe74e-d3fd-46ee-9594-3c64bf97a2e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582549270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1582549270
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2666678806
Short name T75
Test name
Test status
Simulation time 183311180843 ps
CPU time 397.68 seconds
Started Jul 28 06:41:06 PM PDT 24
Finished Jul 28 06:47:43 PM PDT 24
Peak memory 201136 kb
Host smart-b2d67c7e-df2f-4523-81d0-dcb4fb840eed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666678806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2666678806
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1240141569
Short name T480
Test name
Test status
Simulation time 614339499084 ps
CPU time 114.22 seconds
Started Jul 28 06:41:05 PM PDT 24
Finished Jul 28 06:42:59 PM PDT 24
Peak memory 201232 kb
Host smart-2b5b2c43-f99a-414b-8c43-eda2bb870d22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240141569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1240141569
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1882754837
Short name T193
Test name
Test status
Simulation time 90864029122 ps
CPU time 275.92 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:45:46 PM PDT 24
Peak memory 201620 kb
Host smart-9624573f-ea84-4453-aac3-8e8c5e13d140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882754837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1882754837
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3603062885
Short name T757
Test name
Test status
Simulation time 36909447166 ps
CPU time 43.13 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:41:55 PM PDT 24
Peak memory 200996 kb
Host smart-9ce58210-536e-4134-8450-732c9fd84699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603062885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3603062885
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1976809772
Short name T420
Test name
Test status
Simulation time 3846028189 ps
CPU time 5.97 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:41:17 PM PDT 24
Peak memory 200992 kb
Host smart-5051234c-4353-4693-9894-fa42ee5a9bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976809772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1976809772
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3669363874
Short name T553
Test name
Test status
Simulation time 5785117126 ps
CPU time 3.86 seconds
Started Jul 28 06:40:58 PM PDT 24
Finished Jul 28 06:41:02 PM PDT 24
Peak memory 201040 kb
Host smart-fa48d476-ff6c-492b-9533-6719f95d8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669363874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3669363874
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2423585238
Short name T696
Test name
Test status
Simulation time 520352295007 ps
CPU time 330.81 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:46:41 PM PDT 24
Peak memory 201184 kb
Host smart-a4812cb0-6872-44fe-b417-64d554fe5a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423585238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2423585238
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1305247247
Short name T31
Test name
Test status
Simulation time 109814577545 ps
CPU time 69.37 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:42:21 PM PDT 24
Peak memory 209484 kb
Host smart-206843b4-7097-4422-bd0e-4ec2df565166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305247247 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1305247247
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2784335616
Short name T588
Test name
Test status
Simulation time 530632009 ps
CPU time 0.89 seconds
Started Jul 28 06:41:23 PM PDT 24
Finished Jul 28 06:41:24 PM PDT 24
Peak memory 200916 kb
Host smart-b5a09318-e4eb-4912-bf42-a8dc59ec431f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784335616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2784335616
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3789934766
Short name T342
Test name
Test status
Simulation time 491247598230 ps
CPU time 227.31 seconds
Started Jul 28 06:41:16 PM PDT 24
Finished Jul 28 06:45:04 PM PDT 24
Peak memory 201140 kb
Host smart-0bd40a2a-f4c2-4872-87c6-4ad2ecc39b7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789934766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3789934766
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1208793353
Short name T515
Test name
Test status
Simulation time 170622541712 ps
CPU time 373.85 seconds
Started Jul 28 06:41:15 PM PDT 24
Finished Jul 28 06:47:29 PM PDT 24
Peak memory 201164 kb
Host smart-b38b8252-473e-44bf-b5b4-9369d883bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208793353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1208793353
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2909623447
Short name T213
Test name
Test status
Simulation time 486497758173 ps
CPU time 534.47 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:50:04 PM PDT 24
Peak memory 201160 kb
Host smart-48f2fc99-e43c-4195-9dbf-f0e71d351afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909623447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2909623447
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3724370193
Short name T10
Test name
Test status
Simulation time 163722383087 ps
CPU time 366.59 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:47:17 PM PDT 24
Peak memory 201212 kb
Host smart-6af73d2b-af32-4ba9-a79f-841a88d05a93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724370193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3724370193
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2759494248
Short name T101
Test name
Test status
Simulation time 166503038518 ps
CPU time 29.57 seconds
Started Jul 28 06:41:11 PM PDT 24
Finished Jul 28 06:41:41 PM PDT 24
Peak memory 201144 kb
Host smart-991e2775-92c0-4bde-af2a-99bc3a6fab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759494248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2759494248
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1669962836
Short name T714
Test name
Test status
Simulation time 496173854768 ps
CPU time 594.22 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:51:04 PM PDT 24
Peak memory 201088 kb
Host smart-d2ee580b-924b-4599-b913-c9ff9260ed87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669962836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1669962836
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4123115451
Short name T753
Test name
Test status
Simulation time 202807621643 ps
CPU time 440.39 seconds
Started Jul 28 06:41:16 PM PDT 24
Finished Jul 28 06:48:37 PM PDT 24
Peak memory 201112 kb
Host smart-8e3665e6-3ec2-4633-8579-5f18a84aa308
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123115451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4123115451
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.635256311
Short name T648
Test name
Test status
Simulation time 142744210617 ps
CPU time 464.82 seconds
Started Jul 28 06:41:23 PM PDT 24
Finished Jul 28 06:49:08 PM PDT 24
Peak memory 201604 kb
Host smart-7c6fe1a2-e2ff-4e41-a52c-ac6553ae9bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635256311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.635256311
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2537346943
Short name T639
Test name
Test status
Simulation time 28845950960 ps
CPU time 66.12 seconds
Started Jul 28 06:41:24 PM PDT 24
Finished Jul 28 06:42:30 PM PDT 24
Peak memory 200996 kb
Host smart-856b9d25-01a3-4e61-a6aa-22460b4d41f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537346943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2537346943
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4152660455
Short name T771
Test name
Test status
Simulation time 3766257201 ps
CPU time 10.08 seconds
Started Jul 28 06:41:15 PM PDT 24
Finished Jul 28 06:41:25 PM PDT 24
Peak memory 201008 kb
Host smart-971ee723-2213-47ef-ba19-f99cbaa5aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152660455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4152660455
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3734330681
Short name T540
Test name
Test status
Simulation time 6039760975 ps
CPU time 4.47 seconds
Started Jul 28 06:41:10 PM PDT 24
Finished Jul 28 06:41:15 PM PDT 24
Peak memory 201032 kb
Host smart-4696b9a8-f3d4-409d-a6a8-a727faefeb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734330681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3734330681
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1683150951
Short name T711
Test name
Test status
Simulation time 7132035893 ps
CPU time 15.68 seconds
Started Jul 28 06:41:23 PM PDT 24
Finished Jul 28 06:41:39 PM PDT 24
Peak memory 201064 kb
Host smart-ab74fdb0-a06d-4023-ba96-f58deb22c66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683150951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1683150951
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1664986166
Short name T20
Test name
Test status
Simulation time 152137636258 ps
CPU time 124.48 seconds
Started Jul 28 06:41:24 PM PDT 24
Finished Jul 28 06:43:28 PM PDT 24
Peak memory 217600 kb
Host smart-5bffcc0a-dfb1-464c-bf05-413afd566769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664986166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1664986166
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1960062969
Short name T796
Test name
Test status
Simulation time 468493051 ps
CPU time 1.69 seconds
Started Jul 28 06:41:41 PM PDT 24
Finished Jul 28 06:41:42 PM PDT 24
Peak memory 200928 kb
Host smart-b7b2fe96-9de8-4a14-a058-8fa011e5aeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960062969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1960062969
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1287931972
Short name T277
Test name
Test status
Simulation time 162880360157 ps
CPU time 59.63 seconds
Started Jul 28 06:41:33 PM PDT 24
Finished Jul 28 06:42:33 PM PDT 24
Peak memory 201216 kb
Host smart-90cdb677-1149-4fbb-94bb-d5508aff90d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287931972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1287931972
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2650447683
Short name T530
Test name
Test status
Simulation time 327696035883 ps
CPU time 767.08 seconds
Started Jul 28 06:41:27 PM PDT 24
Finished Jul 28 06:54:14 PM PDT 24
Peak memory 201180 kb
Host smart-6286575d-7608-4f49-8cf0-b2e10afb2ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650447683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2650447683
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.282893564
Short name T491
Test name
Test status
Simulation time 329587319134 ps
CPU time 764.51 seconds
Started Jul 28 06:41:28 PM PDT 24
Finished Jul 28 06:54:13 PM PDT 24
Peak memory 201164 kb
Host smart-baf0ec7e-73a5-4276-b819-d14a2988ce58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=282893564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.282893564
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.620673826
Short name T199
Test name
Test status
Simulation time 493936723366 ps
CPU time 273.78 seconds
Started Jul 28 06:41:23 PM PDT 24
Finished Jul 28 06:45:57 PM PDT 24
Peak memory 201128 kb
Host smart-5f740b2e-a4be-491c-9e0f-03544b49e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620673826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.620673826
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1291059209
Short name T99
Test name
Test status
Simulation time 161659516461 ps
CPU time 241.25 seconds
Started Jul 28 06:41:28 PM PDT 24
Finished Jul 28 06:45:29 PM PDT 24
Peak memory 201424 kb
Host smart-83d89581-9584-4bc4-9535-3b764a4539c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291059209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1291059209
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.736232545
Short name T615
Test name
Test status
Simulation time 348801071667 ps
CPU time 189.89 seconds
Started Jul 28 06:41:27 PM PDT 24
Finished Jul 28 06:44:37 PM PDT 24
Peak memory 201160 kb
Host smart-3133e02f-ed78-4943-8acb-49dd0a7e7f31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736232545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.736232545
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.22504731
Short name T660
Test name
Test status
Simulation time 605142591441 ps
CPU time 654.31 seconds
Started Jul 28 06:41:33 PM PDT 24
Finished Jul 28 06:52:27 PM PDT 24
Peak memory 201160 kb
Host smart-5f771e4c-0e49-4f2a-801f-a8fdad8c5cce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.22504731
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.906990410
Short name T607
Test name
Test status
Simulation time 102930912007 ps
CPU time 332.61 seconds
Started Jul 28 06:41:40 PM PDT 24
Finished Jul 28 06:47:13 PM PDT 24
Peak memory 201644 kb
Host smart-3d843a59-2883-4a7c-9cfb-3ab078790f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906990410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.906990410
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.128155145
Short name T102
Test name
Test status
Simulation time 32036245132 ps
CPU time 36.68 seconds
Started Jul 28 06:41:39 PM PDT 24
Finished Jul 28 06:42:16 PM PDT 24
Peak memory 201004 kb
Host smart-8e19845a-8640-4901-8004-47977101eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128155145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.128155145
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2659518916
Short name T643
Test name
Test status
Simulation time 4934028860 ps
CPU time 5.89 seconds
Started Jul 28 06:41:34 PM PDT 24
Finished Jul 28 06:41:40 PM PDT 24
Peak memory 200992 kb
Host smart-ee42bfe3-962f-423a-ad32-c266be5e3a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659518916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2659518916
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.795429462
Short name T713
Test name
Test status
Simulation time 6034890286 ps
CPU time 4.07 seconds
Started Jul 28 06:41:23 PM PDT 24
Finished Jul 28 06:41:27 PM PDT 24
Peak memory 201064 kb
Host smart-d63cba25-b707-4e57-b61f-0d93af83cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795429462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.795429462
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2222037247
Short name T184
Test name
Test status
Simulation time 8900024741 ps
CPU time 22.64 seconds
Started Jul 28 06:41:40 PM PDT 24
Finished Jul 28 06:42:03 PM PDT 24
Peak memory 201020 kb
Host smart-d88c4b74-012c-41f7-b5f1-fb3fdcef74fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222037247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2222037247
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.971468146
Short name T268
Test name
Test status
Simulation time 446496334406 ps
CPU time 74.09 seconds
Started Jul 28 06:41:41 PM PDT 24
Finished Jul 28 06:42:55 PM PDT 24
Peak memory 209928 kb
Host smart-57f60231-9ed3-44d4-8b31-ed233dc5ae10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971468146 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.971468146
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3473999476
Short name T452
Test name
Test status
Simulation time 310362287 ps
CPU time 0.77 seconds
Started Jul 28 06:41:58 PM PDT 24
Finished Jul 28 06:41:58 PM PDT 24
Peak memory 200968 kb
Host smart-407367d4-9402-4a38-8890-d5e70defaee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473999476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3473999476
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.148111227
Short name T281
Test name
Test status
Simulation time 333000397428 ps
CPU time 744.14 seconds
Started Jul 28 06:41:53 PM PDT 24
Finished Jul 28 06:54:18 PM PDT 24
Peak memory 201168 kb
Host smart-a23d041e-b758-40ef-b32f-31139d3fc83a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148111227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.148111227
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.61944146
Short name T322
Test name
Test status
Simulation time 185811945591 ps
CPU time 109.59 seconds
Started Jul 28 06:41:55 PM PDT 24
Finished Jul 28 06:43:45 PM PDT 24
Peak memory 201160 kb
Host smart-d7c352dd-de1d-48b5-8149-5ec9bc149317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61944146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.61944146
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2264310645
Short name T677
Test name
Test status
Simulation time 331049569996 ps
CPU time 405.14 seconds
Started Jul 28 06:41:48 PM PDT 24
Finished Jul 28 06:48:34 PM PDT 24
Peak memory 200528 kb
Host smart-a6265d61-2864-4a8e-9ce4-9cd4374ff622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264310645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2264310645
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1550033122
Short name T24
Test name
Test status
Simulation time 158515529400 ps
CPU time 195.87 seconds
Started Jul 28 06:41:48 PM PDT 24
Finished Jul 28 06:45:04 PM PDT 24
Peak memory 201156 kb
Host smart-8cc17366-6933-4c1f-99ee-33965b315d4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550033122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1550033122
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2052670143
Short name T483
Test name
Test status
Simulation time 326692127486 ps
CPU time 574.99 seconds
Started Jul 28 06:41:47 PM PDT 24
Finished Jul 28 06:51:22 PM PDT 24
Peak memory 201120 kb
Host smart-6715b75e-c415-43ac-91fa-4060648ab2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052670143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2052670143
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2412879743
Short name T145
Test name
Test status
Simulation time 329128246951 ps
CPU time 722.59 seconds
Started Jul 28 06:41:47 PM PDT 24
Finished Jul 28 06:53:50 PM PDT 24
Peak memory 201160 kb
Host smart-5bb04643-d1d6-4ae1-96fa-aa7863dfa3bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412879743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2412879743
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3665512392
Short name T444
Test name
Test status
Simulation time 168352763617 ps
CPU time 43.96 seconds
Started Jul 28 06:41:52 PM PDT 24
Finished Jul 28 06:42:36 PM PDT 24
Peak memory 201112 kb
Host smart-ffb1828d-ebf9-44c6-8fed-7017179b8f66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665512392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3665512392
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2899107482
Short name T423
Test name
Test status
Simulation time 198383823613 ps
CPU time 117.97 seconds
Started Jul 28 06:41:54 PM PDT 24
Finished Jul 28 06:43:52 PM PDT 24
Peak memory 201184 kb
Host smart-58683a57-8c9a-47d9-8ce4-a24758e2a7db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899107482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2899107482
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1264084089
Short name T650
Test name
Test status
Simulation time 79833041155 ps
CPU time 467.35 seconds
Started Jul 28 06:41:52 PM PDT 24
Finished Jul 28 06:49:40 PM PDT 24
Peak memory 201600 kb
Host smart-86145853-6df9-436e-bea3-e22ca61f68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264084089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1264084089
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4042351828
Short name T389
Test name
Test status
Simulation time 25239269961 ps
CPU time 30.49 seconds
Started Jul 28 06:41:53 PM PDT 24
Finished Jul 28 06:42:23 PM PDT 24
Peak memory 201024 kb
Host smart-29449521-c97e-482f-b7c7-b91c916e0a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042351828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4042351828
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3586235183
Short name T646
Test name
Test status
Simulation time 2944081711 ps
CPU time 7.53 seconds
Started Jul 28 06:41:55 PM PDT 24
Finished Jul 28 06:42:02 PM PDT 24
Peak memory 201008 kb
Host smart-94f29166-9c69-4f3b-af1b-fae638f1a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586235183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3586235183
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2025887075
Short name T165
Test name
Test status
Simulation time 5860842596 ps
CPU time 4.11 seconds
Started Jul 28 06:41:48 PM PDT 24
Finished Jul 28 06:41:53 PM PDT 24
Peak memory 200380 kb
Host smart-964d9a4f-e210-4869-9417-3f192e6e7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025887075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2025887075
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4096668839
Short name T78
Test name
Test status
Simulation time 70962498368 ps
CPU time 308.99 seconds
Started Jul 28 06:41:58 PM PDT 24
Finished Jul 28 06:47:07 PM PDT 24
Peak memory 209868 kb
Host smart-dcee3dee-5794-460e-8102-0cf427379925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096668839 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4096668839
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3429159448
Short name T754
Test name
Test status
Simulation time 382082306 ps
CPU time 0.8 seconds
Started Jul 28 06:42:09 PM PDT 24
Finished Jul 28 06:42:10 PM PDT 24
Peak memory 200980 kb
Host smart-11bb710c-dac8-4629-b542-3f573b616c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429159448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3429159448
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.442247818
Short name T657
Test name
Test status
Simulation time 179083596980 ps
CPU time 91.11 seconds
Started Jul 28 06:42:05 PM PDT 24
Finished Jul 28 06:43:37 PM PDT 24
Peak memory 201232 kb
Host smart-2609c497-81af-4fde-96a4-8a6bd35fa409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442247818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.442247818
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.90974312
Short name T487
Test name
Test status
Simulation time 327047912917 ps
CPU time 776.15 seconds
Started Jul 28 06:41:58 PM PDT 24
Finished Jul 28 06:54:54 PM PDT 24
Peak memory 201160 kb
Host smart-20611ef8-3d81-4a16-903b-4fe9006f10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90974312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.90974312
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3886980733
Short name T492
Test name
Test status
Simulation time 326363870306 ps
CPU time 714.52 seconds
Started Jul 28 06:41:59 PM PDT 24
Finished Jul 28 06:53:54 PM PDT 24
Peak memory 201108 kb
Host smart-db5de744-f33a-401e-bebe-99ad36052a85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886980733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3886980733
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1482248128
Short name T201
Test name
Test status
Simulation time 333359098605 ps
CPU time 123.5 seconds
Started Jul 28 06:41:59 PM PDT 24
Finished Jul 28 06:44:03 PM PDT 24
Peak memory 201088 kb
Host smart-f05bad54-8fc9-4aae-a827-e12f8d57e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482248128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1482248128
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2186249830
Short name T598
Test name
Test status
Simulation time 489210285322 ps
CPU time 648.37 seconds
Started Jul 28 06:41:59 PM PDT 24
Finished Jul 28 06:52:47 PM PDT 24
Peak memory 201216 kb
Host smart-e9fd731c-c1c3-404e-9266-b45500b56fc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186249830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2186249830
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4104182625
Short name T190
Test name
Test status
Simulation time 187671678837 ps
CPU time 154.48 seconds
Started Jul 28 06:42:06 PM PDT 24
Finished Jul 28 06:44:41 PM PDT 24
Peak memory 201152 kb
Host smart-0937083a-0196-4256-9dc6-3db728d58b0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104182625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4104182625
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1924667463
Short name T777
Test name
Test status
Simulation time 90917059544 ps
CPU time 454.85 seconds
Started Jul 28 06:42:10 PM PDT 24
Finished Jul 28 06:49:45 PM PDT 24
Peak memory 201632 kb
Host smart-7c992f5d-f068-4356-b1b5-bc921219a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924667463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1924667463
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.723400405
Short name T712
Test name
Test status
Simulation time 38596781976 ps
CPU time 87.35 seconds
Started Jul 28 06:42:09 PM PDT 24
Finished Jul 28 06:43:37 PM PDT 24
Peak memory 201000 kb
Host smart-bd473aa4-e9d7-4bad-adac-ac49befc9372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723400405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.723400405
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.946673150
Short name T520
Test name
Test status
Simulation time 3311807630 ps
CPU time 2.51 seconds
Started Jul 28 06:42:10 PM PDT 24
Finished Jul 28 06:42:12 PM PDT 24
Peak memory 200988 kb
Host smart-581ba0ea-38e3-4077-af98-5d6c0d65cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946673150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.946673150
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.960531270
Short name T641
Test name
Test status
Simulation time 5830655168 ps
CPU time 1.77 seconds
Started Jul 28 06:41:59 PM PDT 24
Finished Jul 28 06:42:00 PM PDT 24
Peak memory 201060 kb
Host smart-8e96f05d-6d85-432b-8760-49e661e1fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960531270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.960531270
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1557327566
Short name T311
Test name
Test status
Simulation time 249538806601 ps
CPU time 724.36 seconds
Started Jul 28 06:42:10 PM PDT 24
Finished Jul 28 06:54:15 PM PDT 24
Peak memory 209808 kb
Host smart-8cd0cae2-adec-41bd-8bbd-893097bbc212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557327566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1557327566
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.769943392
Short name T706
Test name
Test status
Simulation time 363554781731 ps
CPU time 516.1 seconds
Started Jul 28 06:42:08 PM PDT 24
Finished Jul 28 06:50:44 PM PDT 24
Peak memory 209984 kb
Host smart-aae4ab08-1673-4890-9f04-621d3e2abe35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769943392 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.769943392
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4047185611
Short name T745
Test name
Test status
Simulation time 171540371030 ps
CPU time 105.14 seconds
Started Jul 28 06:42:33 PM PDT 24
Finished Jul 28 06:44:18 PM PDT 24
Peak memory 201176 kb
Host smart-9a19b91a-4e1f-4519-97f1-6ddc3bd43b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047185611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4047185611
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2125956245
Short name T303
Test name
Test status
Simulation time 489839560399 ps
CPU time 749.51 seconds
Started Jul 28 06:42:15 PM PDT 24
Finished Jul 28 06:54:45 PM PDT 24
Peak memory 201188 kb
Host smart-885d6abf-af34-4b6d-8bf2-48258dd7ec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125956245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2125956245
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.80843309
Short name T476
Test name
Test status
Simulation time 317624193536 ps
CPU time 185.52 seconds
Started Jul 28 06:42:16 PM PDT 24
Finished Jul 28 06:45:22 PM PDT 24
Peak memory 201144 kb
Host smart-62f43034-4780-47ec-bffe-afc5332e4482
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=80843309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt
_fixed.80843309
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3146273926
Short name T683
Test name
Test status
Simulation time 491270452466 ps
CPU time 830.41 seconds
Started Jul 28 06:42:16 PM PDT 24
Finished Jul 28 06:56:06 PM PDT 24
Peak memory 201120 kb
Host smart-58e73ceb-7c07-4b7c-af01-94f7e6b5aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146273926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3146273926
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3802069654
Short name T698
Test name
Test status
Simulation time 328137464371 ps
CPU time 788.4 seconds
Started Jul 28 06:42:14 PM PDT 24
Finished Jul 28 06:55:23 PM PDT 24
Peak memory 201212 kb
Host smart-69dae869-c179-48af-9b21-d26284bc7e53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802069654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3802069654
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1945401965
Short name T705
Test name
Test status
Simulation time 184204080573 ps
CPU time 110.51 seconds
Started Jul 28 06:42:15 PM PDT 24
Finished Jul 28 06:44:06 PM PDT 24
Peak memory 201116 kb
Host smart-4257d822-4940-4c13-b1e6-7bdabe1e891d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945401965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1945401965
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.345186621
Short name T538
Test name
Test status
Simulation time 132668465157 ps
CPU time 452.49 seconds
Started Jul 28 06:42:27 PM PDT 24
Finished Jul 28 06:50:00 PM PDT 24
Peak memory 201644 kb
Host smart-181bb059-62fc-4d63-99ee-502ceac968cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345186621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.345186621
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3700369334
Short name T106
Test name
Test status
Simulation time 42085596939 ps
CPU time 97.47 seconds
Started Jul 28 06:42:28 PM PDT 24
Finished Jul 28 06:44:06 PM PDT 24
Peak memory 201016 kb
Host smart-1ac39712-d38b-4b7d-a641-57c0d8c3f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700369334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3700369334
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.483072875
Short name T400
Test name
Test status
Simulation time 5177568971 ps
CPU time 1.99 seconds
Started Jul 28 06:42:29 PM PDT 24
Finished Jul 28 06:42:31 PM PDT 24
Peak memory 200948 kb
Host smart-ed050d3a-8229-423e-bc2f-911c4ab14017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483072875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.483072875
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.669096043
Short name T438
Test name
Test status
Simulation time 6106083495 ps
CPU time 16.1 seconds
Started Jul 28 06:42:14 PM PDT 24
Finished Jul 28 06:42:30 PM PDT 24
Peak memory 201076 kb
Host smart-6f1c469c-cf41-4324-afc3-6dfc33d9b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669096043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.669096043
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.911854783
Short name T680
Test name
Test status
Simulation time 323061086308 ps
CPU time 467.17 seconds
Started Jul 28 06:42:27 PM PDT 24
Finished Jul 28 06:50:15 PM PDT 24
Peak memory 209804 kb
Host smart-fc3f7025-c1b2-424c-9791-1f209790a0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911854783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
911854783
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3458063759
Short name T580
Test name
Test status
Simulation time 38943978591 ps
CPU time 94.34 seconds
Started Jul 28 06:42:27 PM PDT 24
Finished Jul 28 06:44:02 PM PDT 24
Peak memory 209940 kb
Host smart-d14a690d-2a8b-4d8f-a4c7-af54a9a3a76a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458063759 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3458063759
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3692139831
Short name T191
Test name
Test status
Simulation time 369231801 ps
CPU time 1.49 seconds
Started Jul 28 06:42:45 PM PDT 24
Finished Jul 28 06:42:47 PM PDT 24
Peak memory 200984 kb
Host smart-b4f4aa23-8416-4ba2-a2e3-6eee00107f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692139831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3692139831
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1982739858
Short name T543
Test name
Test status
Simulation time 252534381416 ps
CPU time 458.17 seconds
Started Jul 28 06:42:42 PM PDT 24
Finished Jul 28 06:50:20 PM PDT 24
Peak memory 201116 kb
Host smart-cbb3d591-f1eb-4fdb-afc3-c679bee29a0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982739858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1982739858
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1049680362
Short name T595
Test name
Test status
Simulation time 160715491389 ps
CPU time 93.49 seconds
Started Jul 28 06:42:43 PM PDT 24
Finished Jul 28 06:44:17 PM PDT 24
Peak memory 201148 kb
Host smart-7e7be788-08ac-4fbf-b191-cb580edf1177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049680362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1049680362
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2939459853
Short name T602
Test name
Test status
Simulation time 493022837093 ps
CPU time 535.86 seconds
Started Jul 28 06:42:34 PM PDT 24
Finished Jul 28 06:51:30 PM PDT 24
Peak memory 201212 kb
Host smart-70921b1d-97fb-49d5-8078-d3adb1518ae4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939459853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2939459853
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2349217855
Short name T710
Test name
Test status
Simulation time 165302099175 ps
CPU time 377.13 seconds
Started Jul 28 06:42:33 PM PDT 24
Finished Jul 28 06:48:51 PM PDT 24
Peak memory 201140 kb
Host smart-84029193-c987-4a57-a9e4-1070890ff2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349217855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2349217855
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3976629104
Short name T497
Test name
Test status
Simulation time 492867508622 ps
CPU time 1113.02 seconds
Started Jul 28 06:42:35 PM PDT 24
Finished Jul 28 07:01:08 PM PDT 24
Peak memory 201136 kb
Host smart-fc357c6a-5dde-4c04-a328-a4fc2f7c8bce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976629104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3976629104
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3407847921
Short name T313
Test name
Test status
Simulation time 537964057459 ps
CPU time 1291.56 seconds
Started Jul 28 06:42:41 PM PDT 24
Finished Jul 28 07:04:13 PM PDT 24
Peak memory 201192 kb
Host smart-7fa7738d-0f58-47e1-9b8b-93c20e98d4ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407847921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3407847921
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3033538045
Short name T541
Test name
Test status
Simulation time 414256102239 ps
CPU time 222.74 seconds
Started Jul 28 06:42:42 PM PDT 24
Finished Jul 28 06:46:25 PM PDT 24
Peak memory 201148 kb
Host smart-00e9361a-e07b-4c1d-ab6d-272ffe7a7c4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033538045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3033538045
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.736355752
Short name T792
Test name
Test status
Simulation time 92026314673 ps
CPU time 373.01 seconds
Started Jul 28 06:42:43 PM PDT 24
Finished Jul 28 06:48:56 PM PDT 24
Peak memory 201624 kb
Host smart-40eb47e0-247e-4571-8c28-21991b340ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736355752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.736355752
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2236146701
Short name T28
Test name
Test status
Simulation time 39394519783 ps
CPU time 19.71 seconds
Started Jul 28 06:42:42 PM PDT 24
Finished Jul 28 06:43:02 PM PDT 24
Peak memory 201032 kb
Host smart-7dcd3ea0-2e51-4738-99fb-a58e327f959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236146701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2236146701
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.646251106
Short name T466
Test name
Test status
Simulation time 3652670353 ps
CPU time 3.38 seconds
Started Jul 28 06:42:42 PM PDT 24
Finished Jul 28 06:42:46 PM PDT 24
Peak memory 201032 kb
Host smart-e5fd6c99-83d7-45c0-b80a-284fd35c57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646251106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.646251106
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.4270340800
Short name T669
Test name
Test status
Simulation time 5909414877 ps
CPU time 3.22 seconds
Started Jul 28 06:42:34 PM PDT 24
Finished Jul 28 06:42:37 PM PDT 24
Peak memory 201020 kb
Host smart-b2ac6b96-317d-49c7-8006-86f56c6575fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270340800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.4270340800
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4065983584
Short name T770
Test name
Test status
Simulation time 352227965166 ps
CPU time 62.85 seconds
Started Jul 28 06:42:46 PM PDT 24
Finished Jul 28 06:43:49 PM PDT 24
Peak memory 201396 kb
Host smart-11ba49ae-9708-44eb-a753-8d0e14f5d43d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065983584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4065983584
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.312401438
Short name T449
Test name
Test status
Simulation time 389476350 ps
CPU time 0.76 seconds
Started Jul 28 06:43:04 PM PDT 24
Finished Jul 28 06:43:05 PM PDT 24
Peak memory 200976 kb
Host smart-c95b2ad1-c647-4291-947a-d56159097840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312401438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.312401438
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3908495733
Short name T86
Test name
Test status
Simulation time 168336996120 ps
CPU time 156.68 seconds
Started Jul 28 06:42:58 PM PDT 24
Finished Jul 28 06:45:35 PM PDT 24
Peak memory 201136 kb
Host smart-6e0cfe65-a6a0-40bf-ba90-5cc1c56e3953
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908495733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3908495733
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2230053253
Short name T82
Test name
Test status
Simulation time 509598335550 ps
CPU time 608.1 seconds
Started Jul 28 06:42:58 PM PDT 24
Finished Jul 28 06:53:06 PM PDT 24
Peak memory 201176 kb
Host smart-1c7c8e90-5754-4a3e-896a-d113ff73f47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230053253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2230053253
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1808479364
Short name T700
Test name
Test status
Simulation time 159261466229 ps
CPU time 90.69 seconds
Started Jul 28 06:42:50 PM PDT 24
Finished Jul 28 06:44:21 PM PDT 24
Peak memory 201144 kb
Host smart-da9e2edc-47e5-4c45-8264-f601005a64b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808479364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1808479364
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4173604130
Short name T773
Test name
Test status
Simulation time 326828852085 ps
CPU time 394.9 seconds
Started Jul 28 06:42:52 PM PDT 24
Finished Jul 28 06:49:27 PM PDT 24
Peak memory 201208 kb
Host smart-864be3bd-6459-4a87-90f7-7a6c43ea232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173604130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4173604130
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1769923251
Short name T656
Test name
Test status
Simulation time 165484412904 ps
CPU time 371.69 seconds
Started Jul 28 06:42:52 PM PDT 24
Finished Jul 28 06:49:03 PM PDT 24
Peak memory 201180 kb
Host smart-d0229b83-4e54-421a-9d0a-de660875346d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769923251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1769923251
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1191105741
Short name T141
Test name
Test status
Simulation time 524217971501 ps
CPU time 78.82 seconds
Started Jul 28 06:42:53 PM PDT 24
Finished Jul 28 06:44:12 PM PDT 24
Peak memory 201156 kb
Host smart-7aca9604-1f7a-4b36-8903-139e6fc929a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191105741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1191105741
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4287431485
Short name T430
Test name
Test status
Simulation time 590499669945 ps
CPU time 321.62 seconds
Started Jul 28 06:42:58 PM PDT 24
Finished Jul 28 06:48:19 PM PDT 24
Peak memory 201080 kb
Host smart-434107f8-39aa-4bab-90de-4f5440151b12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287431485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4287431485
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3662769271
Short name T456
Test name
Test status
Simulation time 95549605668 ps
CPU time 479.82 seconds
Started Jul 28 06:43:03 PM PDT 24
Finished Jul 28 06:51:03 PM PDT 24
Peak memory 201636 kb
Host smart-3fb96dca-751c-4c60-9b57-c13d1c6e5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662769271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3662769271
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.898639630
Short name T504
Test name
Test status
Simulation time 32048776994 ps
CPU time 69.81 seconds
Started Jul 28 06:43:05 PM PDT 24
Finished Jul 28 06:44:15 PM PDT 24
Peak memory 201012 kb
Host smart-e43e9c05-b3e8-4834-b4cf-c5127c63858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898639630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.898639630
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3099820760
Short name T578
Test name
Test status
Simulation time 4097121491 ps
CPU time 2.92 seconds
Started Jul 28 06:43:04 PM PDT 24
Finished Jul 28 06:43:07 PM PDT 24
Peak memory 200992 kb
Host smart-1f2c7f8d-342d-4e15-a620-2bc8138c5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099820760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3099820760
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1956929337
Short name T686
Test name
Test status
Simulation time 5952577533 ps
CPU time 14.14 seconds
Started Jul 28 06:42:54 PM PDT 24
Finished Jul 28 06:43:08 PM PDT 24
Peak memory 201040 kb
Host smart-e8341c18-1985-464c-9d3f-d075a95f7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956929337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1956929337
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1991938787
Short name T366
Test name
Test status
Simulation time 322547114139 ps
CPU time 1074.46 seconds
Started Jul 28 06:43:06 PM PDT 24
Finished Jul 28 07:01:00 PM PDT 24
Peak memory 201592 kb
Host smart-5e9c6c1e-b817-4e9b-b3eb-eb0b4f726bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991938787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1991938787
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3461779906
Short name T39
Test name
Test status
Simulation time 926867443005 ps
CPU time 102.48 seconds
Started Jul 28 06:43:06 PM PDT 24
Finished Jul 28 06:44:49 PM PDT 24
Peak memory 209504 kb
Host smart-2096973d-7c71-4e24-a5e8-e63697997815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461779906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3461779906
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3478372699
Short name T12
Test name
Test status
Simulation time 521652559 ps
CPU time 0.9 seconds
Started Jul 28 06:43:15 PM PDT 24
Finished Jul 28 06:43:16 PM PDT 24
Peak memory 200920 kb
Host smart-d158fd4a-96b5-495a-820d-33d3ce9bfcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478372699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3478372699
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1306308542
Short name T764
Test name
Test status
Simulation time 358531177249 ps
CPU time 152.44 seconds
Started Jul 28 06:43:10 PM PDT 24
Finished Jul 28 06:45:43 PM PDT 24
Peak memory 201156 kb
Host smart-0015eb89-a431-4556-a25e-0c15b34b2efa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306308542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1306308542
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.268372233
Short name T605
Test name
Test status
Simulation time 166754386326 ps
CPU time 195.58 seconds
Started Jul 28 06:43:11 PM PDT 24
Finished Jul 28 06:46:27 PM PDT 24
Peak memory 201180 kb
Host smart-2ddc274b-6178-4d3c-a487-c9fb9f0135db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268372233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.268372233
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3910389874
Short name T37
Test name
Test status
Simulation time 331099321699 ps
CPU time 171.18 seconds
Started Jul 28 06:43:11 PM PDT 24
Finished Jul 28 06:46:02 PM PDT 24
Peak memory 201148 kb
Host smart-111c12e2-eb22-4f22-93aa-5414d6999978
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910389874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3910389874
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1763828847
Short name T173
Test name
Test status
Simulation time 330270684992 ps
CPU time 214.08 seconds
Started Jul 28 06:43:09 PM PDT 24
Finished Jul 28 06:46:44 PM PDT 24
Peak memory 201280 kb
Host smart-c391e703-758d-4b8c-a0bf-d06392785a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763828847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1763828847
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2979150038
Short name T426
Test name
Test status
Simulation time 497766525895 ps
CPU time 1178.38 seconds
Started Jul 28 06:43:10 PM PDT 24
Finished Jul 28 07:02:49 PM PDT 24
Peak memory 201140 kb
Host smart-2ccec61e-e294-473c-a3f1-b03f1f8e32c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979150038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2979150038
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.758751767
Short name T482
Test name
Test status
Simulation time 184310940024 ps
CPU time 116.34 seconds
Started Jul 28 06:43:11 PM PDT 24
Finished Jul 28 06:45:07 PM PDT 24
Peak memory 201184 kb
Host smart-b7a5b10e-eefb-4c2b-8851-5feb9633a2e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758751767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.758751767
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.899340677
Short name T632
Test name
Test status
Simulation time 204263387348 ps
CPU time 166.6 seconds
Started Jul 28 06:43:09 PM PDT 24
Finished Jul 28 06:45:56 PM PDT 24
Peak memory 201180 kb
Host smart-c627ce6d-e0ca-4314-9218-4642586f4013
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899340677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.899340677
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3226087361
Short name T527
Test name
Test status
Simulation time 36641124339 ps
CPU time 43.26 seconds
Started Jul 28 06:43:16 PM PDT 24
Finished Jul 28 06:44:00 PM PDT 24
Peak memory 200992 kb
Host smart-d6a590f5-ce50-455d-a625-84a94102ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226087361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3226087361
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.719413857
Short name T590
Test name
Test status
Simulation time 4179382276 ps
CPU time 10.5 seconds
Started Jul 28 06:43:17 PM PDT 24
Finished Jul 28 06:43:28 PM PDT 24
Peak memory 200968 kb
Host smart-304a4ea9-e9f2-445d-9680-71d4be1f8718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719413857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.719413857
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1426919365
Short name T375
Test name
Test status
Simulation time 5707984251 ps
CPU time 7.88 seconds
Started Jul 28 06:43:04 PM PDT 24
Finished Jul 28 06:43:12 PM PDT 24
Peak memory 201044 kb
Host smart-af174093-f07f-45ae-b2e1-12e6615e1f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426919365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1426919365
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1183682534
Short name T569
Test name
Test status
Simulation time 7696342971 ps
CPU time 9.35 seconds
Started Jul 28 06:43:16 PM PDT 24
Finished Jul 28 06:43:26 PM PDT 24
Peak memory 201072 kb
Host smart-b14c7d9b-4ac4-4ec6-8744-10b730d55d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183682534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1183682534
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2957053086
Short name T194
Test name
Test status
Simulation time 412012692 ps
CPU time 0.83 seconds
Started Jul 28 06:43:32 PM PDT 24
Finished Jul 28 06:43:33 PM PDT 24
Peak memory 200916 kb
Host smart-6aeef5da-605f-496e-b313-7cdcbbe3c9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957053086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2957053086
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1408487599
Short name T129
Test name
Test status
Simulation time 176194719795 ps
CPU time 202.43 seconds
Started Jul 28 06:43:24 PM PDT 24
Finished Jul 28 06:46:47 PM PDT 24
Peak memory 201204 kb
Host smart-b2580e05-f313-4b86-b580-322d766351d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408487599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1408487599
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3000387061
Short name T454
Test name
Test status
Simulation time 165831186394 ps
CPU time 387.07 seconds
Started Jul 28 06:43:23 PM PDT 24
Finished Jul 28 06:49:50 PM PDT 24
Peak memory 201164 kb
Host smart-02dccc15-8e82-41cc-98e7-98014899bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000387061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3000387061
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2469228874
Short name T370
Test name
Test status
Simulation time 499894212423 ps
CPU time 573.18 seconds
Started Jul 28 06:43:22 PM PDT 24
Finished Jul 28 06:52:56 PM PDT 24
Peak memory 201200 kb
Host smart-041450e5-91d6-41a9-89c6-d0bef92a726d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469228874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2469228874
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.262181084
Short name T465
Test name
Test status
Simulation time 492811603634 ps
CPU time 1078.4 seconds
Started Jul 28 06:43:21 PM PDT 24
Finished Jul 28 07:01:20 PM PDT 24
Peak memory 201096 kb
Host smart-e9a1542e-90e8-4e05-9f9e-98ca27642a07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262181084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.262181084
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1567762600
Short name T275
Test name
Test status
Simulation time 347598635216 ps
CPU time 192.04 seconds
Started Jul 28 06:43:26 PM PDT 24
Finished Jul 28 06:46:38 PM PDT 24
Peak memory 201156 kb
Host smart-0563acdb-b198-483f-99ff-9e62f368dcc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567762600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1567762600
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.251673949
Short name T470
Test name
Test status
Simulation time 392294040750 ps
CPU time 470.25 seconds
Started Jul 28 06:43:23 PM PDT 24
Finished Jul 28 06:51:14 PM PDT 24
Peak memory 201144 kb
Host smart-d44fc66e-406a-4b42-adc0-63813e61d68a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251673949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.251673949
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3292748720
Short name T795
Test name
Test status
Simulation time 125452907956 ps
CPU time 446.63 seconds
Started Jul 28 06:43:33 PM PDT 24
Finished Jul 28 06:50:59 PM PDT 24
Peak memory 201588 kb
Host smart-e9c4cb6f-d46d-454c-b206-e3d52b9eb6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292748720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3292748720
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1948896624
Short name T435
Test name
Test status
Simulation time 21581444428 ps
CPU time 7.47 seconds
Started Jul 28 06:43:32 PM PDT 24
Finished Jul 28 06:43:40 PM PDT 24
Peak memory 200952 kb
Host smart-94f6cd6d-adc0-4ee3-880b-a443eed0b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948896624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1948896624
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2747129074
Short name T409
Test name
Test status
Simulation time 3783653870 ps
CPU time 8.21 seconds
Started Jul 28 06:43:31 PM PDT 24
Finished Jul 28 06:43:39 PM PDT 24
Peak memory 200968 kb
Host smart-2fe9c18b-b5b4-4936-a836-93d393560b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747129074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2747129074
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2277525134
Short name T207
Test name
Test status
Simulation time 5771083097 ps
CPU time 7.08 seconds
Started Jul 28 06:43:21 PM PDT 24
Finished Jul 28 06:43:28 PM PDT 24
Peak memory 201020 kb
Host smart-3d6d6210-afd4-476a-b967-86d195ec5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277525134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2277525134
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2879745574
Short name T638
Test name
Test status
Simulation time 175150675586 ps
CPU time 101.64 seconds
Started Jul 28 06:43:32 PM PDT 24
Finished Jul 28 06:45:14 PM PDT 24
Peak memory 201176 kb
Host smart-00e44da1-11a3-4dd4-80e0-4d2e0b3fec00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879745574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2879745574
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3951480861
Short name T216
Test name
Test status
Simulation time 82758552303 ps
CPU time 112.5 seconds
Started Jul 28 06:43:31 PM PDT 24
Finished Jul 28 06:45:24 PM PDT 24
Peak memory 218016 kb
Host smart-8eed0df4-4b05-4c83-89a6-acea6851a068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951480861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3951480861
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4112154636
Short name T781
Test name
Test status
Simulation time 357935441 ps
CPU time 0.83 seconds
Started Jul 28 06:39:13 PM PDT 24
Finished Jul 28 06:39:14 PM PDT 24
Peak memory 200968 kb
Host smart-4fe9585f-c8e6-47f3-a5c8-09d380e73873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112154636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4112154636
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3308069938
Short name T315
Test name
Test status
Simulation time 522893331840 ps
CPU time 764.24 seconds
Started Jul 28 06:39:13 PM PDT 24
Finished Jul 28 06:51:57 PM PDT 24
Peak memory 201116 kb
Host smart-f9a3ff5e-0af1-4cf0-bc35-13414aabe729
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308069938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3308069938
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1611285867
Short name T769
Test name
Test status
Simulation time 334197603143 ps
CPU time 807.67 seconds
Started Jul 28 06:39:07 PM PDT 24
Finished Jul 28 06:52:35 PM PDT 24
Peak memory 201140 kb
Host smart-e8d16d82-4014-4b47-ba7c-253630b66106
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611285867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1611285867
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3865191102
Short name T672
Test name
Test status
Simulation time 167202306694 ps
CPU time 181.72 seconds
Started Jul 28 06:39:02 PM PDT 24
Finished Jul 28 06:42:04 PM PDT 24
Peak memory 201156 kb
Host smart-5fd2a155-722d-422f-ba4c-ae9066762873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865191102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3865191102
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.374516384
Short name T766
Test name
Test status
Simulation time 330459898046 ps
CPU time 211.74 seconds
Started Jul 28 06:39:07 PM PDT 24
Finished Jul 28 06:42:39 PM PDT 24
Peak memory 201128 kb
Host smart-419826db-fe2c-422b-93df-ecfee6366b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=374516384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.374516384
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3673483203
Short name T151
Test name
Test status
Simulation time 571111789775 ps
CPU time 1295.74 seconds
Started Jul 28 06:39:07 PM PDT 24
Finished Jul 28 07:00:43 PM PDT 24
Peak memory 201148 kb
Host smart-c05d303c-0948-47ca-a58f-30c5b8398d2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673483203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3673483203
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1615360918
Short name T445
Test name
Test status
Simulation time 599760386190 ps
CPU time 357.22 seconds
Started Jul 28 06:39:07 PM PDT 24
Finished Jul 28 06:45:05 PM PDT 24
Peak memory 201152 kb
Host smart-b3ce95c7-2468-4943-8db7-bd4529ab8b2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615360918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1615360918
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3605286837
Short name T226
Test name
Test status
Simulation time 111805303709 ps
CPU time 532.95 seconds
Started Jul 28 06:39:14 PM PDT 24
Finished Jul 28 06:48:07 PM PDT 24
Peak memory 201660 kb
Host smart-2e1efa6d-3717-4e41-b6e7-a3abf31307ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605286837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3605286837
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3929953703
Short name T373
Test name
Test status
Simulation time 42840805189 ps
CPU time 14.73 seconds
Started Jul 28 06:39:14 PM PDT 24
Finished Jul 28 06:39:29 PM PDT 24
Peak memory 200984 kb
Host smart-7d7ee100-c11f-40d2-ad91-a87804c7ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929953703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3929953703
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2717622924
Short name T376
Test name
Test status
Simulation time 2909342182 ps
CPU time 2.51 seconds
Started Jul 28 06:39:12 PM PDT 24
Finished Jul 28 06:39:14 PM PDT 24
Peak memory 201012 kb
Host smart-53c9a01a-c304-4a34-ba8d-1a046f017f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717622924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2717622924
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.763431591
Short name T57
Test name
Test status
Simulation time 4214996537 ps
CPU time 7.91 seconds
Started Jul 28 06:39:14 PM PDT 24
Finished Jul 28 06:39:22 PM PDT 24
Peak memory 216832 kb
Host smart-4bec505e-9b99-4ad4-a3fe-a5504c5cb077
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763431591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.763431591
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1178993959
Short name T645
Test name
Test status
Simulation time 5576010241 ps
CPU time 4.12 seconds
Started Jul 28 06:39:02 PM PDT 24
Finished Jul 28 06:39:07 PM PDT 24
Peak memory 201008 kb
Host smart-6ed384a1-d313-4d84-aee1-c87bbc85fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178993959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1178993959
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3364975349
Short name T36
Test name
Test status
Simulation time 10710423423 ps
CPU time 7.09 seconds
Started Jul 28 06:39:15 PM PDT 24
Finished Jul 28 06:39:22 PM PDT 24
Peak memory 201040 kb
Host smart-5deed44a-bba7-403a-8b5c-ce137c7c068d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364975349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3364975349
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1998589023
Short name T18
Test name
Test status
Simulation time 76610673678 ps
CPU time 179.74 seconds
Started Jul 28 06:39:14 PM PDT 24
Finished Jul 28 06:42:14 PM PDT 24
Peak memory 217484 kb
Host smart-febf9844-748c-45bd-be92-c9aa74b766b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998589023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1998589023
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3719421324
Short name T25
Test name
Test status
Simulation time 508373484 ps
CPU time 1.15 seconds
Started Jul 28 06:43:49 PM PDT 24
Finished Jul 28 06:43:50 PM PDT 24
Peak memory 200920 kb
Host smart-867c5e78-0101-4b5e-aa07-f4e3fcde40c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719421324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3719421324
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1781718080
Short name T244
Test name
Test status
Simulation time 162447373442 ps
CPU time 379.75 seconds
Started Jul 28 06:43:48 PM PDT 24
Finished Jul 28 06:50:08 PM PDT 24
Peak memory 201136 kb
Host smart-b2be94cf-a133-43df-8828-91a077de1a28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781718080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1781718080
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.196127894
Short name T140
Test name
Test status
Simulation time 180873961168 ps
CPU time 107.82 seconds
Started Jul 28 06:43:49 PM PDT 24
Finished Jul 28 06:45:37 PM PDT 24
Peak memory 201144 kb
Host smart-d59c2984-5123-4196-89cf-e67abc56d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196127894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.196127894
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3249079011
Short name T516
Test name
Test status
Simulation time 163426806816 ps
CPU time 353.84 seconds
Started Jul 28 06:43:40 PM PDT 24
Finished Jul 28 06:49:34 PM PDT 24
Peak memory 201112 kb
Host smart-b7dd263a-5830-40fa-920b-c693921b834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249079011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3249079011
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3586297004
Short name T689
Test name
Test status
Simulation time 483457027363 ps
CPU time 102.28 seconds
Started Jul 28 06:43:39 PM PDT 24
Finished Jul 28 06:45:22 PM PDT 24
Peak memory 201220 kb
Host smart-819d55a7-21d1-4a00-b058-c2b02d68fffc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586297004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3586297004
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3999011545
Short name T180
Test name
Test status
Simulation time 326949740744 ps
CPU time 387.66 seconds
Started Jul 28 06:43:40 PM PDT 24
Finished Jul 28 06:50:08 PM PDT 24
Peak memory 201152 kb
Host smart-b4882247-2c9f-48c7-945f-59370136b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999011545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3999011545
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.21655919
Short name T500
Test name
Test status
Simulation time 491010305920 ps
CPU time 109.38 seconds
Started Jul 28 06:43:39 PM PDT 24
Finished Jul 28 06:45:29 PM PDT 24
Peak memory 201156 kb
Host smart-b7fbc2d0-8b6d-43a2-b7b9-dae40586b450
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed
.21655919
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3580288951
Short name T526
Test name
Test status
Simulation time 602213210262 ps
CPU time 382.7 seconds
Started Jul 28 06:43:47 PM PDT 24
Finished Jul 28 06:50:09 PM PDT 24
Peak memory 201156 kb
Host smart-a12112f7-0389-4c88-8e37-9cdd3544cc1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580288951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3580288951
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2050643153
Short name T220
Test name
Test status
Simulation time 113175820273 ps
CPU time 634.2 seconds
Started Jul 28 06:43:51 PM PDT 24
Finished Jul 28 06:54:25 PM PDT 24
Peak memory 201592 kb
Host smart-d61658cc-6167-4bea-9fbe-94593ad5f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050643153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2050643153
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1742083370
Short name T186
Test name
Test status
Simulation time 44719383566 ps
CPU time 25.83 seconds
Started Jul 28 06:43:48 PM PDT 24
Finished Jul 28 06:44:14 PM PDT 24
Peak memory 201020 kb
Host smart-3bf15b83-d2d7-4727-a326-a8443e2a0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742083370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1742083370
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.4227863087
Short name T774
Test name
Test status
Simulation time 4263546122 ps
CPU time 3.27 seconds
Started Jul 28 06:43:47 PM PDT 24
Finished Jul 28 06:43:50 PM PDT 24
Peak memory 201004 kb
Host smart-4b62b78e-8acc-4e6f-a531-44cd0a3e7783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227863087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.4227863087
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1237180844
Short name T379
Test name
Test status
Simulation time 5603895441 ps
CPU time 4.31 seconds
Started Jul 28 06:43:41 PM PDT 24
Finished Jul 28 06:43:45 PM PDT 24
Peak memory 201040 kb
Host smart-438e8a61-66b3-43ef-890b-f424e66d4c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237180844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1237180844
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.498736494
Short name T579
Test name
Test status
Simulation time 201175470244 ps
CPU time 477.53 seconds
Started Jul 28 06:43:50 PM PDT 24
Finished Jul 28 06:51:47 PM PDT 24
Peak memory 201220 kb
Host smart-5d328680-6f03-405c-9e22-f75c7b6b1764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498736494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
498736494
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1089977408
Short name T35
Test name
Test status
Simulation time 64155782495 ps
CPU time 139.26 seconds
Started Jul 28 06:43:51 PM PDT 24
Finished Jul 28 06:46:10 PM PDT 24
Peak memory 209464 kb
Host smart-a0f42b22-a569-4982-bbcf-1b2313f17932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089977408 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1089977408
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4077886734
Short name T478
Test name
Test status
Simulation time 393173778 ps
CPU time 0.75 seconds
Started Jul 28 06:44:04 PM PDT 24
Finished Jul 28 06:44:05 PM PDT 24
Peak memory 200952 kb
Host smart-80773caa-5726-4e51-af56-68366e926dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077886734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4077886734
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2804772250
Short name T336
Test name
Test status
Simulation time 518098063579 ps
CPU time 834.9 seconds
Started Jul 28 06:43:58 PM PDT 24
Finished Jul 28 06:57:53 PM PDT 24
Peak memory 201152 kb
Host smart-e9326860-3c16-40a7-92db-6601a59aa686
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804772250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2804772250
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.436882049
Short name T152
Test name
Test status
Simulation time 548230693587 ps
CPU time 653.37 seconds
Started Jul 28 06:44:03 PM PDT 24
Finished Jul 28 06:54:57 PM PDT 24
Peak memory 201172 kb
Host smart-68dbfff6-65ea-48cc-8f48-b0765c6b75ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436882049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.436882049
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.69817674
Short name T159
Test name
Test status
Simulation time 336152525237 ps
CPU time 172.16 seconds
Started Jul 28 06:43:57 PM PDT 24
Finished Jul 28 06:46:50 PM PDT 24
Peak memory 201240 kb
Host smart-68ac91bf-1cb4-4a34-831f-337967c9b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69817674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.69817674
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3298664826
Short name T92
Test name
Test status
Simulation time 320028359487 ps
CPU time 160.69 seconds
Started Jul 28 06:43:57 PM PDT 24
Finished Jul 28 06:46:38 PM PDT 24
Peak memory 201164 kb
Host smart-556160c5-4c0f-4bff-a138-6ebd9810bb3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298664826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3298664826
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.610164318
Short name T521
Test name
Test status
Simulation time 324626075096 ps
CPU time 804.06 seconds
Started Jul 28 06:43:52 PM PDT 24
Finished Jul 28 06:57:16 PM PDT 24
Peak memory 201104 kb
Host smart-866ec0b6-d70f-422a-b592-5f7ba2720851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610164318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.610164318
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.641556319
Short name T594
Test name
Test status
Simulation time 491049002922 ps
CPU time 1176.25 seconds
Started Jul 28 06:43:51 PM PDT 24
Finished Jul 28 07:03:27 PM PDT 24
Peak memory 201168 kb
Host smart-73bfe08f-0af0-4b89-ac46-ae390388b516
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=641556319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.641556319
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.976987272
Short name T572
Test name
Test status
Simulation time 622041549617 ps
CPU time 1410.23 seconds
Started Jul 28 06:43:56 PM PDT 24
Finished Jul 28 07:07:27 PM PDT 24
Peak memory 201116 kb
Host smart-39f7e241-dd69-4658-b0b5-d38a27ba2f9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976987272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.976987272
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1956706534
Short name T787
Test name
Test status
Simulation time 95033925714 ps
CPU time 401.93 seconds
Started Jul 28 06:44:06 PM PDT 24
Finished Jul 28 06:50:48 PM PDT 24
Peak memory 201624 kb
Host smart-a8a1b80f-ce84-432e-994d-6e8ac0fa34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956706534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1956706534
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1655059323
Short name T406
Test name
Test status
Simulation time 38113904298 ps
CPU time 42.13 seconds
Started Jul 28 06:44:05 PM PDT 24
Finished Jul 28 06:44:47 PM PDT 24
Peak memory 200980 kb
Host smart-c9a17ea3-a286-423b-9fd5-3c072e681fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655059323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1655059323
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2467971153
Short name T495
Test name
Test status
Simulation time 3027127865 ps
CPU time 2.59 seconds
Started Jul 28 06:44:04 PM PDT 24
Finished Jul 28 06:44:07 PM PDT 24
Peak memory 200968 kb
Host smart-a2bf8e90-3826-4504-a2b8-caa3b578f8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467971153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2467971153
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2985843033
Short name T555
Test name
Test status
Simulation time 5773258597 ps
CPU time 1.54 seconds
Started Jul 28 06:43:51 PM PDT 24
Finished Jul 28 06:43:52 PM PDT 24
Peak memory 201016 kb
Host smart-d5cc4cb0-af7f-417c-ae68-e54c4a868568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985843033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2985843033
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.684545876
Short name T556
Test name
Test status
Simulation time 376787871607 ps
CPU time 227.32 seconds
Started Jul 28 06:44:02 PM PDT 24
Finished Jul 28 06:47:49 PM PDT 24
Peak memory 201152 kb
Host smart-1edff9c3-d0a3-4972-8349-3674afb9e7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684545876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
684545876
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2148817718
Short name T265
Test name
Test status
Simulation time 589890550876 ps
CPU time 206.18 seconds
Started Jul 28 06:44:04 PM PDT 24
Finished Jul 28 06:47:30 PM PDT 24
Peak memory 209932 kb
Host smart-ec364b62-4150-4b0b-9f2f-5358b68c26bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148817718 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2148817718
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1649338716
Short name T791
Test name
Test status
Simulation time 359231161 ps
CPU time 1.54 seconds
Started Jul 28 06:44:21 PM PDT 24
Finished Jul 28 06:44:22 PM PDT 24
Peak memory 200884 kb
Host smart-5f055bdb-db24-4d00-ace1-85e875b299d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649338716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1649338716
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2660486866
Short name T574
Test name
Test status
Simulation time 488240966373 ps
CPU time 1174.32 seconds
Started Jul 28 06:44:10 PM PDT 24
Finished Jul 28 07:03:44 PM PDT 24
Peak memory 201204 kb
Host smart-5478ba80-9731-46dd-9e68-8dd2b67f710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660486866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2660486866
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2799319768
Short name T383
Test name
Test status
Simulation time 335871467709 ps
CPU time 800.27 seconds
Started Jul 28 06:44:08 PM PDT 24
Finished Jul 28 06:57:28 PM PDT 24
Peak memory 201088 kb
Host smart-84e727a9-cbd0-455a-9fd6-6de00d724252
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799319768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2799319768
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1309495298
Short name T131
Test name
Test status
Simulation time 322320584839 ps
CPU time 344.51 seconds
Started Jul 28 06:44:09 PM PDT 24
Finished Jul 28 06:49:53 PM PDT 24
Peak memory 201184 kb
Host smart-944959a7-4826-4a3f-a59a-e87c73de49f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309495298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1309495298
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1799603618
Short name T460
Test name
Test status
Simulation time 333703452450 ps
CPU time 711.47 seconds
Started Jul 28 06:44:09 PM PDT 24
Finished Jul 28 06:56:01 PM PDT 24
Peak memory 201088 kb
Host smart-36e2f5e5-74a0-4ea3-b19a-60ca69a18785
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799603618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1799603618
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.650607235
Short name T357
Test name
Test status
Simulation time 563699808660 ps
CPU time 1238.24 seconds
Started Jul 28 06:44:08 PM PDT 24
Finished Jul 28 07:04:46 PM PDT 24
Peak memory 201276 kb
Host smart-c3cd702e-c647-4af4-9db2-c4a5488c4131
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650607235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.650607235
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.779307652
Short name T674
Test name
Test status
Simulation time 398692441553 ps
CPU time 436.55 seconds
Started Jul 28 06:44:09 PM PDT 24
Finished Jul 28 06:51:25 PM PDT 24
Peak memory 201172 kb
Host smart-6214fec1-c698-4bf3-8ce8-992434c4c5cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779307652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.779307652
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1057526022
Short name T534
Test name
Test status
Simulation time 31031718355 ps
CPU time 68.63 seconds
Started Jul 28 06:44:15 PM PDT 24
Finished Jul 28 06:45:24 PM PDT 24
Peak memory 201016 kb
Host smart-2b48b5ce-a7f1-4185-a550-69d6084d5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057526022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1057526022
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3013182971
Short name T744
Test name
Test status
Simulation time 3194810172 ps
CPU time 2.85 seconds
Started Jul 28 06:44:17 PM PDT 24
Finished Jul 28 06:44:20 PM PDT 24
Peak memory 200948 kb
Host smart-12369638-1876-4b50-a7d9-87354deb59e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013182971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3013182971
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1024405151
Short name T693
Test name
Test status
Simulation time 5952588984 ps
CPU time 13.98 seconds
Started Jul 28 06:44:04 PM PDT 24
Finished Jul 28 06:44:18 PM PDT 24
Peak memory 200984 kb
Host smart-df38cf33-3910-4b53-8b1d-f89e8f732f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024405151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1024405151
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1824748460
Short name T364
Test name
Test status
Simulation time 482250827224 ps
CPU time 317.34 seconds
Started Jul 28 06:44:21 PM PDT 24
Finished Jul 28 06:49:39 PM PDT 24
Peak memory 218168 kb
Host smart-d03fb3de-8a15-4670-9e38-9029a2e19d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824748460 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1824748460
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.422825565
Short name T192
Test name
Test status
Simulation time 326584352 ps
CPU time 0.86 seconds
Started Jul 28 06:44:37 PM PDT 24
Finished Jul 28 06:44:38 PM PDT 24
Peak memory 200980 kb
Host smart-4126d203-ac2d-4ca5-b675-0adf6fe27bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422825565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.422825565
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3388260617
Short name T768
Test name
Test status
Simulation time 514959359549 ps
CPU time 277.04 seconds
Started Jul 28 06:44:27 PM PDT 24
Finished Jul 28 06:49:04 PM PDT 24
Peak memory 201212 kb
Host smart-96ee6050-02b9-46dd-88ec-40cca4464816
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388260617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3388260617
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2984271059
Short name T324
Test name
Test status
Simulation time 484067932355 ps
CPU time 606.89 seconds
Started Jul 28 06:44:25 PM PDT 24
Finished Jul 28 06:54:32 PM PDT 24
Peak memory 201164 kb
Host smart-a5be0a60-5cbe-4450-97b1-8b23cff9b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984271059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2984271059
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.4214902390
Short name T306
Test name
Test status
Simulation time 331021011228 ps
CPU time 699.21 seconds
Started Jul 28 06:44:20 PM PDT 24
Finished Jul 28 06:55:59 PM PDT 24
Peak memory 201236 kb
Host smart-d74f3fad-4aab-4b31-8cbf-40f5cd15729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214902390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4214902390
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3390880031
Short name T536
Test name
Test status
Simulation time 164359967151 ps
CPU time 99.05 seconds
Started Jul 28 06:44:25 PM PDT 24
Finished Jul 28 06:46:05 PM PDT 24
Peak memory 201136 kb
Host smart-ad02c3a8-6149-43be-b4a9-617e546b34ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390880031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3390880031
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3491716265
Short name T126
Test name
Test status
Simulation time 488154422045 ps
CPU time 860.4 seconds
Started Jul 28 06:44:20 PM PDT 24
Finished Jul 28 06:58:40 PM PDT 24
Peak memory 201212 kb
Host smart-5e587f9c-d1a1-4620-a342-818cfddef68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491716265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3491716265
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2816648355
Short name T670
Test name
Test status
Simulation time 161173822016 ps
CPU time 380.3 seconds
Started Jul 28 06:44:22 PM PDT 24
Finished Jul 28 06:50:42 PM PDT 24
Peak memory 201148 kb
Host smart-44e1513a-b0c6-44e8-baad-b79ae43b7c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816648355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2816648355
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1243295334
Short name T170
Test name
Test status
Simulation time 194041872097 ps
CPU time 442.7 seconds
Started Jul 28 06:44:26 PM PDT 24
Finished Jul 28 06:51:49 PM PDT 24
Peak memory 201148 kb
Host smart-3aa4a96d-530e-4668-8f07-3c9e075c329a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243295334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1243295334
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4086552195
Short name T257
Test name
Test status
Simulation time 410986399236 ps
CPU time 932.97 seconds
Started Jul 28 06:44:24 PM PDT 24
Finished Jul 28 06:59:57 PM PDT 24
Peak memory 201176 kb
Host smart-d0056af7-1c54-4d7e-9265-20c2ba2add10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086552195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.4086552195
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3967010782
Short name T85
Test name
Test status
Simulation time 114684400329 ps
CPU time 565.38 seconds
Started Jul 28 06:44:32 PM PDT 24
Finished Jul 28 06:53:58 PM PDT 24
Peak memory 201600 kb
Host smart-0a86f20f-e260-4e39-89fe-3f7c35099b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967010782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3967010782
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2960141728
Short name T369
Test name
Test status
Simulation time 29314677259 ps
CPU time 26.35 seconds
Started Jul 28 06:44:26 PM PDT 24
Finished Jul 28 06:44:53 PM PDT 24
Peak memory 201020 kb
Host smart-d2e7943c-22d1-4040-a66a-f048fb4f856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960141728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2960141728
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3911257137
Short name T784
Test name
Test status
Simulation time 4238791290 ps
CPU time 2.57 seconds
Started Jul 28 06:44:26 PM PDT 24
Finished Jul 28 06:44:29 PM PDT 24
Peak memory 200984 kb
Host smart-d654c7f3-4efd-4b4b-a875-fe8a7e4f6063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911257137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3911257137
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.12381674
Short name T776
Test name
Test status
Simulation time 5770220844 ps
CPU time 4.19 seconds
Started Jul 28 06:44:21 PM PDT 24
Finished Jul 28 06:44:25 PM PDT 24
Peak memory 201000 kb
Host smart-8b64b958-4507-4d8b-8efd-173ddb56d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12381674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.12381674
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.994470848
Short name T582
Test name
Test status
Simulation time 167275107242 ps
CPU time 394.84 seconds
Started Jul 28 06:44:32 PM PDT 24
Finished Jul 28 06:51:07 PM PDT 24
Peak memory 201164 kb
Host smart-51209db0-0d64-4503-89df-44dede29a466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994470848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
994470848
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.443543517
Short name T4
Test name
Test status
Simulation time 486970837 ps
CPU time 0.7 seconds
Started Jul 28 06:44:47 PM PDT 24
Finished Jul 28 06:44:48 PM PDT 24
Peak memory 200992 kb
Host smart-eba5ece4-a10d-4f15-ac41-d9fb9c6222ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443543517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.443543517
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3930339030
Short name T276
Test name
Test status
Simulation time 167331796779 ps
CPU time 122.49 seconds
Started Jul 28 06:44:38 PM PDT 24
Finished Jul 28 06:46:41 PM PDT 24
Peak memory 201160 kb
Host smart-5856315b-044a-49dd-916d-cb01245f5b0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930339030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3930339030
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2629500227
Short name T189
Test name
Test status
Simulation time 342321683793 ps
CPU time 131.99 seconds
Started Jul 28 06:44:43 PM PDT 24
Finished Jul 28 06:46:55 PM PDT 24
Peak memory 201152 kb
Host smart-a61b130a-12ff-42eb-826c-b2721ab000de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629500227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2629500227
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.317779831
Short name T589
Test name
Test status
Simulation time 330758271367 ps
CPU time 594.94 seconds
Started Jul 28 06:44:39 PM PDT 24
Finished Jul 28 06:54:34 PM PDT 24
Peak memory 201176 kb
Host smart-1a168d3e-aac3-43b8-837d-1a46088d9f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317779831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.317779831
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3985347739
Short name T38
Test name
Test status
Simulation time 502284217131 ps
CPU time 321.4 seconds
Started Jul 28 06:44:36 PM PDT 24
Finished Jul 28 06:49:57 PM PDT 24
Peak memory 201096 kb
Host smart-cc5ff32b-eecf-400c-8bd0-b71a871bae60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985347739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3985347739
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3527811722
Short name T411
Test name
Test status
Simulation time 169390717636 ps
CPU time 211.78 seconds
Started Jul 28 06:44:39 PM PDT 24
Finished Jul 28 06:48:11 PM PDT 24
Peak memory 201248 kb
Host smart-7963fbc1-7cb7-4f98-bff4-0b4eb0947ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527811722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3527811722
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3584068659
Short name T577
Test name
Test status
Simulation time 485368512512 ps
CPU time 277.37 seconds
Started Jul 28 06:44:37 PM PDT 24
Finished Jul 28 06:49:15 PM PDT 24
Peak memory 201200 kb
Host smart-f52b8296-c444-43e6-b1bd-950010aec9fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584068659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3584068659
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.183802895
Short name T599
Test name
Test status
Simulation time 199480464466 ps
CPU time 113.95 seconds
Started Jul 28 06:44:37 PM PDT 24
Finished Jul 28 06:46:31 PM PDT 24
Peak memory 201152 kb
Host smart-a3bd6489-a641-4967-a73d-285dc3b80e95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183802895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.183802895
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4102846663
Short name T394
Test name
Test status
Simulation time 195919326347 ps
CPU time 194.69 seconds
Started Jul 28 06:44:35 PM PDT 24
Finished Jul 28 06:47:50 PM PDT 24
Peak memory 201144 kb
Host smart-384451fa-27bf-43d1-83c0-0cf10332cf06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102846663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4102846663
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.397729709
Short name T164
Test name
Test status
Simulation time 109358808743 ps
CPU time 381.22 seconds
Started Jul 28 06:44:42 PM PDT 24
Finished Jul 28 06:51:03 PM PDT 24
Peak memory 201632 kb
Host smart-e688ace1-2985-424d-9dbb-80a92983bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397729709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.397729709
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4252280162
Short name T433
Test name
Test status
Simulation time 28954113388 ps
CPU time 16.07 seconds
Started Jul 28 06:44:41 PM PDT 24
Finished Jul 28 06:44:57 PM PDT 24
Peak memory 201024 kb
Host smart-138ae63a-218d-4b5a-bc99-8e97d1f43e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252280162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4252280162
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3351666616
Short name T554
Test name
Test status
Simulation time 5251591021 ps
CPU time 12.94 seconds
Started Jul 28 06:44:44 PM PDT 24
Finished Jul 28 06:44:57 PM PDT 24
Peak memory 200908 kb
Host smart-2b262ef9-9b05-442e-ae01-96f077f1ae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351666616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3351666616
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1893819528
Short name T678
Test name
Test status
Simulation time 5715929808 ps
CPU time 2.07 seconds
Started Jul 28 06:44:39 PM PDT 24
Finished Jul 28 06:44:41 PM PDT 24
Peak memory 201028 kb
Host smart-8f883b12-4f64-4347-adb4-343b9f8b4ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893819528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1893819528
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4123410043
Short name T279
Test name
Test status
Simulation time 200766703630 ps
CPU time 125.57 seconds
Started Jul 28 06:44:41 PM PDT 24
Finished Jul 28 06:46:47 PM PDT 24
Peak memory 201152 kb
Host smart-7909cbcd-b7e7-4d5a-97ac-6a47e0e802de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123410043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4123410043
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1285722523
Short name T229
Test name
Test status
Simulation time 256154265370 ps
CPU time 360.39 seconds
Started Jul 28 06:44:43 PM PDT 24
Finished Jul 28 06:50:43 PM PDT 24
Peak memory 209896 kb
Host smart-415dccd1-de75-49ff-b3ae-6b9b484c9154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285722523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1285722523
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3515635585
Short name T501
Test name
Test status
Simulation time 532999295 ps
CPU time 1.01 seconds
Started Jul 28 06:45:03 PM PDT 24
Finished Jul 28 06:45:04 PM PDT 24
Peak memory 200916 kb
Host smart-7b791b95-5d75-4842-8cce-fc5d3a3aa15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515635585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3515635585
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.4049054147
Short name T350
Test name
Test status
Simulation time 186081872891 ps
CPU time 414.59 seconds
Started Jul 28 06:44:53 PM PDT 24
Finished Jul 28 06:51:48 PM PDT 24
Peak memory 201124 kb
Host smart-ada2ad35-f396-425e-bd4f-761935a4f390
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049054147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.4049054147
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2215086685
Short name T312
Test name
Test status
Simulation time 341978130794 ps
CPU time 487.39 seconds
Started Jul 28 06:44:52 PM PDT 24
Finished Jul 28 06:53:00 PM PDT 24
Peak memory 201212 kb
Host smart-05fd8198-08f8-4f1b-81ec-2c854516f5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215086685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2215086685
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.395496769
Short name T398
Test name
Test status
Simulation time 486342086901 ps
CPU time 1102.01 seconds
Started Jul 28 06:44:53 PM PDT 24
Finished Jul 28 07:03:15 PM PDT 24
Peak memory 201148 kb
Host smart-411dbbeb-6f59-4575-87fe-7fb350983bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395496769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.395496769
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2598060101
Short name T83
Test name
Test status
Simulation time 322813543366 ps
CPU time 732.61 seconds
Started Jul 28 06:44:49 PM PDT 24
Finished Jul 28 06:57:02 PM PDT 24
Peak memory 201200 kb
Host smart-fecf365c-7603-45f7-810f-5fe8435e5e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598060101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2598060101
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.87462341
Short name T715
Test name
Test status
Simulation time 165343627372 ps
CPU time 198.53 seconds
Started Jul 28 06:44:47 PM PDT 24
Finished Jul 28 06:48:06 PM PDT 24
Peak memory 201172 kb
Host smart-bb477068-a89c-4f6d-a105-bbf50d1dbf61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=87462341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed
.87462341
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1690385851
Short name T767
Test name
Test status
Simulation time 547727136323 ps
CPU time 1259.58 seconds
Started Jul 28 06:44:52 PM PDT 24
Finished Jul 28 07:05:52 PM PDT 24
Peak memory 201236 kb
Host smart-ed3a0359-814e-4582-bae1-2e0259c74ff1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690385851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1690385851
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2698640820
Short name T546
Test name
Test status
Simulation time 201105116788 ps
CPU time 485.37 seconds
Started Jul 28 06:44:53 PM PDT 24
Finished Jul 28 06:52:58 PM PDT 24
Peak memory 201180 kb
Host smart-007d5e47-1644-4a48-a4af-f8e3379afb97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698640820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2698640820
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1081641762
Short name T681
Test name
Test status
Simulation time 87900475926 ps
CPU time 467.99 seconds
Started Jul 28 06:45:03 PM PDT 24
Finished Jul 28 06:52:51 PM PDT 24
Peak memory 201624 kb
Host smart-ad46a361-fa2f-4445-b8a1-5ccb0ac56aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081641762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1081641762
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2932250317
Short name T571
Test name
Test status
Simulation time 44694965411 ps
CPU time 95.15 seconds
Started Jul 28 06:45:05 PM PDT 24
Finished Jul 28 06:46:41 PM PDT 24
Peak memory 201032 kb
Host smart-eae13221-0e34-4f39-9d55-334fb2be05bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932250317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2932250317
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1484338857
Short name T539
Test name
Test status
Simulation time 5174824846 ps
CPU time 12.62 seconds
Started Jul 28 06:44:53 PM PDT 24
Finished Jul 28 06:45:06 PM PDT 24
Peak memory 200948 kb
Host smart-38c291fe-be10-406f-9f14-d6cc411fd9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484338857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1484338857
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2268081391
Short name T637
Test name
Test status
Simulation time 5775643576 ps
CPU time 14.53 seconds
Started Jul 28 06:44:49 PM PDT 24
Finished Jul 28 06:45:04 PM PDT 24
Peak memory 201040 kb
Host smart-d75c408c-5834-4f9e-b96c-dd21584f8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268081391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2268081391
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1451113814
Short name T124
Test name
Test status
Simulation time 41922438086 ps
CPU time 97.71 seconds
Started Jul 28 06:45:03 PM PDT 24
Finished Jul 28 06:46:41 PM PDT 24
Peak memory 217140 kb
Host smart-0fa83de8-d4fe-44a1-94ef-923cd452eccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451113814 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1451113814
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2566587747
Short name T381
Test name
Test status
Simulation time 405169191 ps
CPU time 1.26 seconds
Started Jul 28 06:45:20 PM PDT 24
Finished Jul 28 06:45:21 PM PDT 24
Peak memory 200960 kb
Host smart-9e8cb5c0-a234-492e-a9a8-7f8c3a46cc9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566587747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2566587747
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2679113150
Short name T346
Test name
Test status
Simulation time 516736184880 ps
CPU time 552.65 seconds
Started Jul 28 06:45:19 PM PDT 24
Finished Jul 28 06:54:32 PM PDT 24
Peak memory 201160 kb
Host smart-37fbf3d0-7566-4dba-a286-d97d2a569e81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679113150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2679113150
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.873179980
Short name T197
Test name
Test status
Simulation time 497288967731 ps
CPU time 429.48 seconds
Started Jul 28 06:45:04 PM PDT 24
Finished Jul 28 06:52:13 PM PDT 24
Peak memory 201128 kb
Host smart-e435df64-c20b-49ba-956f-88bf7da90572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873179980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.873179980
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.753368326
Short name T687
Test name
Test status
Simulation time 327541072672 ps
CPU time 204.56 seconds
Started Jul 28 06:45:07 PM PDT 24
Finished Jul 28 06:48:31 PM PDT 24
Peak memory 201192 kb
Host smart-d7d4c0de-76f5-4b7f-a576-5300a2d15cb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=753368326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.753368326
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.827637236
Short name T410
Test name
Test status
Simulation time 488076583282 ps
CPU time 266.65 seconds
Started Jul 28 06:45:06 PM PDT 24
Finished Jul 28 06:49:32 PM PDT 24
Peak memory 201144 kb
Host smart-18e489e3-2f34-4311-a776-6dad5a240fa6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=827637236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.827637236
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3477415803
Short name T752
Test name
Test status
Simulation time 186504396027 ps
CPU time 434.84 seconds
Started Jul 28 06:45:10 PM PDT 24
Finished Jul 28 06:52:25 PM PDT 24
Peak memory 201116 kb
Host smart-a8c9ab4e-e0b2-4349-98e9-a530bb5978e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477415803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3477415803
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.13551568
Short name T625
Test name
Test status
Simulation time 582770256082 ps
CPU time 196.89 seconds
Started Jul 28 06:45:10 PM PDT 24
Finished Jul 28 06:48:27 PM PDT 24
Peak memory 201084 kb
Host smart-c592c64e-a398-4056-ac78-78a306b5bbcd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
dc_ctrl_filters_wakeup_fixed.13551568
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4012039578
Short name T786
Test name
Test status
Simulation time 64543131219 ps
CPU time 203.54 seconds
Started Jul 28 06:45:14 PM PDT 24
Finished Jul 28 06:48:38 PM PDT 24
Peak memory 201664 kb
Host smart-74d4423c-af8b-4afc-8f2a-83ae47638730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012039578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4012039578
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1125820438
Short name T407
Test name
Test status
Simulation time 42202504817 ps
CPU time 93.5 seconds
Started Jul 28 06:45:16 PM PDT 24
Finished Jul 28 06:46:50 PM PDT 24
Peak memory 201036 kb
Host smart-7b7bc068-5341-4434-bbae-2c2fd316a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125820438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1125820438
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4146964939
Short name T702
Test name
Test status
Simulation time 4268856648 ps
CPU time 11.48 seconds
Started Jul 28 06:45:16 PM PDT 24
Finished Jul 28 06:45:28 PM PDT 24
Peak memory 200932 kb
Host smart-48fef25f-cb2f-4415-9299-6340bc913319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146964939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4146964939
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.671973760
Short name T570
Test name
Test status
Simulation time 5949756403 ps
CPU time 7.19 seconds
Started Jul 28 06:45:04 PM PDT 24
Finished Jul 28 06:45:11 PM PDT 24
Peak memory 201040 kb
Host smart-e90f5150-5b2b-418d-9cf0-e77e0f62da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671973760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.671973760
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.628062605
Short name T363
Test name
Test status
Simulation time 145303384962 ps
CPU time 298.07 seconds
Started Jul 28 06:45:15 PM PDT 24
Finished Jul 28 06:50:13 PM PDT 24
Peak memory 209936 kb
Host smart-715b9360-ff6f-4859-aadb-dd8787bdeaba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628062605 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.628062605
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1146657129
Short name T472
Test name
Test status
Simulation time 444050659 ps
CPU time 1.06 seconds
Started Jul 28 06:45:38 PM PDT 24
Finished Jul 28 06:45:39 PM PDT 24
Peak memory 200964 kb
Host smart-b9466c52-342c-4405-9ad7-4ce7b2fbb30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146657129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1146657129
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1825302611
Short name T755
Test name
Test status
Simulation time 328833803177 ps
CPU time 739.67 seconds
Started Jul 28 06:45:32 PM PDT 24
Finished Jul 28 06:57:52 PM PDT 24
Peak memory 201224 kb
Host smart-5d3f95bc-4bd7-420d-b85d-fb101fa8ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825302611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1825302611
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1587765109
Short name T158
Test name
Test status
Simulation time 497719158377 ps
CPU time 1164.6 seconds
Started Jul 28 06:45:28 PM PDT 24
Finished Jul 28 07:04:53 PM PDT 24
Peak memory 201152 kb
Host smart-dd6a6cb0-7412-4d23-8597-ada96bdcfa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587765109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1587765109
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.191629902
Short name T664
Test name
Test status
Simulation time 332763172186 ps
CPU time 181.31 seconds
Started Jul 28 06:45:26 PM PDT 24
Finished Jul 28 06:48:28 PM PDT 24
Peak memory 201164 kb
Host smart-dd342441-6901-4fa4-ab6c-48192ad9c6a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=191629902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.191629902
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3267637032
Short name T414
Test name
Test status
Simulation time 328999226677 ps
CPU time 409.48 seconds
Started Jul 28 06:45:21 PM PDT 24
Finished Jul 28 06:52:11 PM PDT 24
Peak memory 201164 kb
Host smart-7aa5e8ff-9d1a-4df3-a607-523ee7b3fb99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267637032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3267637032
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.142700880
Short name T240
Test name
Test status
Simulation time 572268132664 ps
CPU time 1292.23 seconds
Started Jul 28 06:45:28 PM PDT 24
Finished Jul 28 07:07:00 PM PDT 24
Peak memory 201100 kb
Host smart-93e53374-737f-4382-8ff7-908e7c0dd5e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142700880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.142700880
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4000744834
Short name T584
Test name
Test status
Simulation time 408396273275 ps
CPU time 893.93 seconds
Started Jul 28 06:45:29 PM PDT 24
Finished Jul 28 07:00:23 PM PDT 24
Peak memory 201204 kb
Host smart-a5a6e5f4-84ff-457f-8870-e88c1c35ad54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000744834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4000744834
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1684525825
Short name T223
Test name
Test status
Simulation time 105162267937 ps
CPU time 388.29 seconds
Started Jul 28 06:45:39 PM PDT 24
Finished Jul 28 06:52:07 PM PDT 24
Peak memory 201628 kb
Host smart-8a199bee-9ee2-4b3f-b56c-7e28556dbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684525825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1684525825
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3885290652
Short name T384
Test name
Test status
Simulation time 24416791818 ps
CPU time 30.28 seconds
Started Jul 28 06:45:39 PM PDT 24
Finished Jul 28 06:46:09 PM PDT 24
Peak memory 201004 kb
Host smart-46b753a1-518e-4163-b5fa-d15e607dceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885290652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3885290652
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.692655067
Short name T518
Test name
Test status
Simulation time 4986848798 ps
CPU time 2.1 seconds
Started Jul 28 06:45:36 PM PDT 24
Finished Jul 28 06:45:38 PM PDT 24
Peak memory 200988 kb
Host smart-6e331c7f-3171-4cf2-bea5-56649389dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692655067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.692655067
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1775898005
Short name T382
Test name
Test status
Simulation time 5678787669 ps
CPU time 3.88 seconds
Started Jul 28 06:45:21 PM PDT 24
Finished Jul 28 06:45:25 PM PDT 24
Peak memory 201036 kb
Host smart-fa04d3f0-1469-4011-a820-47ef5ba1c9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775898005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1775898005
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2487058107
Short name T697
Test name
Test status
Simulation time 175982783158 ps
CPU time 96.5 seconds
Started Jul 28 06:45:38 PM PDT 24
Finished Jul 28 06:47:14 PM PDT 24
Peak memory 201220 kb
Host smart-4061e57b-df6c-4663-9af5-f9dc1e9710f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487058107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2487058107
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2421008456
Short name T591
Test name
Test status
Simulation time 340916226 ps
CPU time 1.4 seconds
Started Jul 28 06:45:50 PM PDT 24
Finished Jul 28 06:45:51 PM PDT 24
Peak memory 200944 kb
Host smart-b0023f9d-e577-4840-8019-ef1b64ea9696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421008456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2421008456
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2536017880
Short name T635
Test name
Test status
Simulation time 163438747512 ps
CPU time 287.59 seconds
Started Jul 28 06:45:45 PM PDT 24
Finished Jul 28 06:50:32 PM PDT 24
Peak memory 201168 kb
Host smart-db3db7a1-fe90-4118-bf48-1efc49eecce5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536017880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2536017880
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3070088224
Short name T606
Test name
Test status
Simulation time 164284012854 ps
CPU time 260.01 seconds
Started Jul 28 06:45:38 PM PDT 24
Finished Jul 28 06:49:58 PM PDT 24
Peak memory 201192 kb
Host smart-4496296b-4b32-4ebd-b6b8-c441d3231529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070088224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3070088224
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2019441196
Short name T195
Test name
Test status
Simulation time 498887812337 ps
CPU time 1125.96 seconds
Started Jul 28 06:45:40 PM PDT 24
Finished Jul 28 07:04:27 PM PDT 24
Peak memory 201108 kb
Host smart-a41f6a71-6f38-424f-90af-ea02dd03a561
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019441196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2019441196
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1447318775
Short name T735
Test name
Test status
Simulation time 485376722089 ps
CPU time 419.37 seconds
Started Jul 28 06:45:39 PM PDT 24
Finished Jul 28 06:52:39 PM PDT 24
Peak memory 201128 kb
Host smart-22f7d932-0be6-402a-bf3f-db38b7b47fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447318775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1447318775
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3944955332
Short name T391
Test name
Test status
Simulation time 165125582954 ps
CPU time 372.48 seconds
Started Jul 28 06:45:38 PM PDT 24
Finished Jul 28 06:51:50 PM PDT 24
Peak memory 201152 kb
Host smart-07c4e570-d0e2-4563-96fc-617a0b5ce280
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944955332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3944955332
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.984186823
Short name T23
Test name
Test status
Simulation time 180570059589 ps
CPU time 174.12 seconds
Started Jul 28 06:45:46 PM PDT 24
Finished Jul 28 06:48:40 PM PDT 24
Peak memory 201196 kb
Host smart-a25d8172-353b-4b26-b596-5a48796401b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984186823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.984186823
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.539384009
Short name T377
Test name
Test status
Simulation time 200106082505 ps
CPU time 112.17 seconds
Started Jul 28 06:45:45 PM PDT 24
Finished Jul 28 06:47:38 PM PDT 24
Peak memory 201124 kb
Host smart-12adc397-cd07-4235-8ff4-7ce70ec13d84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539384009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.539384009
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2262500399
Short name T732
Test name
Test status
Simulation time 103703060590 ps
CPU time 550.34 seconds
Started Jul 28 06:45:51 PM PDT 24
Finished Jul 28 06:55:01 PM PDT 24
Peak memory 201576 kb
Host smart-10ca369f-d721-47de-b10a-7b5a842a2542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262500399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2262500399
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.519333585
Short name T510
Test name
Test status
Simulation time 29229924392 ps
CPU time 16.01 seconds
Started Jul 28 06:45:51 PM PDT 24
Finished Jul 28 06:46:07 PM PDT 24
Peak memory 201008 kb
Host smart-72c81999-f086-4ab4-9046-abd039e24ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519333585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.519333585
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.756788703
Short name T436
Test name
Test status
Simulation time 4723356669 ps
CPU time 10.49 seconds
Started Jul 28 06:45:51 PM PDT 24
Finished Jul 28 06:46:02 PM PDT 24
Peak memory 200972 kb
Host smart-57b7d5ab-56d3-4c71-b354-9224ef0dd69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756788703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.756788703
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.733073005
Short name T488
Test name
Test status
Simulation time 6043425142 ps
CPU time 1.53 seconds
Started Jul 28 06:45:37 PM PDT 24
Finished Jul 28 06:45:38 PM PDT 24
Peak memory 200956 kb
Host smart-9f131a2e-0514-49d0-b9a0-9e6041f74844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733073005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.733073005
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1529979442
Short name T493
Test name
Test status
Simulation time 75390721467 ps
CPU time 144.78 seconds
Started Jul 28 06:45:49 PM PDT 24
Finished Jul 28 06:48:14 PM PDT 24
Peak memory 209996 kb
Host smart-ff14965c-5106-4c29-9733-3363c732834d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529979442 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1529979442
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2297636431
Short name T196
Test name
Test status
Simulation time 369957604 ps
CPU time 1.38 seconds
Started Jul 28 06:46:00 PM PDT 24
Finished Jul 28 06:46:01 PM PDT 24
Peak memory 200960 kb
Host smart-f8e058cd-1ef3-4ce6-a404-92bb60ecaf65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297636431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2297636431
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1842041408
Short name T340
Test name
Test status
Simulation time 462108279247 ps
CPU time 1104.23 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 07:04:27 PM PDT 24
Peak memory 201244 kb
Host smart-52064f5d-7c49-4f8a-9d66-ae6ea97832b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842041408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1842041408
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.297037625
Short name T327
Test name
Test status
Simulation time 160625829585 ps
CPU time 71.57 seconds
Started Jul 28 06:45:56 PM PDT 24
Finished Jul 28 06:47:08 PM PDT 24
Peak memory 201216 kb
Host smart-5ec5d402-7980-4245-b31f-d4a1a70b650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297037625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.297037625
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.580701678
Short name T468
Test name
Test status
Simulation time 333606067031 ps
CPU time 125.65 seconds
Started Jul 28 06:45:57 PM PDT 24
Finished Jul 28 06:48:02 PM PDT 24
Peak memory 201252 kb
Host smart-3e04c989-dab4-4244-98af-406f7cf17324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=580701678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.580701678
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3212186058
Short name T148
Test name
Test status
Simulation time 330090433813 ps
CPU time 136.16 seconds
Started Jul 28 06:45:56 PM PDT 24
Finished Jul 28 06:48:13 PM PDT 24
Peak memory 201156 kb
Host smart-81d48518-ca00-45f5-9bd9-534a6ca65366
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212186058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3212186058
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1646805530
Short name T797
Test name
Test status
Simulation time 595147840317 ps
CPU time 208.89 seconds
Started Jul 28 06:45:59 PM PDT 24
Finished Jul 28 06:49:28 PM PDT 24
Peak memory 201088 kb
Host smart-27a65df6-f3b3-455d-b9db-d1a677f92934
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646805530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1646805530
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.812914642
Short name T185
Test name
Test status
Simulation time 86228075755 ps
CPU time 336.43 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 06:51:39 PM PDT 24
Peak memory 201616 kb
Host smart-c811e76e-ba7e-4668-87a6-72e3f2064a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812914642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.812914642
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3162113494
Short name T387
Test name
Test status
Simulation time 29866782802 ps
CPU time 6.85 seconds
Started Jul 28 06:46:03 PM PDT 24
Finished Jul 28 06:46:09 PM PDT 24
Peak memory 200964 kb
Host smart-297b3403-5724-4305-b232-ae24884882b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162113494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3162113494
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3685938680
Short name T726
Test name
Test status
Simulation time 4300995474 ps
CPU time 10.62 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 06:46:12 PM PDT 24
Peak memory 200960 kb
Host smart-e1dd4acf-4da5-4948-915b-3f11f198f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685938680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3685938680
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1369022417
Short name T100
Test name
Test status
Simulation time 6018063479 ps
CPU time 7.86 seconds
Started Jul 28 06:45:58 PM PDT 24
Finished Jul 28 06:46:06 PM PDT 24
Peak memory 201036 kb
Host smart-e8d1d071-d3f7-4a47-a25d-8f5aa44c6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369022417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1369022417
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1261700343
Short name T236
Test name
Test status
Simulation time 346941913584 ps
CPU time 1144.39 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 07:05:07 PM PDT 24
Peak memory 209804 kb
Host smart-131ca9a5-c8e1-4807-94b7-2c147e6f5266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261700343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1261700343
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.307659594
Short name T417
Test name
Test status
Simulation time 453042989 ps
CPU time 1.04 seconds
Started Jul 28 06:39:33 PM PDT 24
Finished Jul 28 06:39:34 PM PDT 24
Peak memory 200960 kb
Host smart-a2d36577-631d-48d1-8283-c69f6101c2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307659594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.307659594
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.204943444
Short name T335
Test name
Test status
Simulation time 513560376225 ps
CPU time 1067.32 seconds
Started Jul 28 06:39:26 PM PDT 24
Finished Jul 28 06:57:14 PM PDT 24
Peak memory 201120 kb
Host smart-b2855e0b-a1c5-4d1e-8f80-d6ac97b3b857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204943444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.204943444
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3230679399
Short name T9
Test name
Test status
Simulation time 320847373773 ps
CPU time 710.39 seconds
Started Jul 28 06:39:26 PM PDT 24
Finished Jul 28 06:51:17 PM PDT 24
Peak memory 201160 kb
Host smart-58d362be-7746-4fc5-bb3e-18343c35f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230679399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3230679399
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3019587439
Short name T137
Test name
Test status
Simulation time 330112161543 ps
CPU time 209.17 seconds
Started Jul 28 06:39:21 PM PDT 24
Finished Jul 28 06:42:51 PM PDT 24
Peak memory 201224 kb
Host smart-54a793a7-3061-4b79-9c5b-4afc3cf26404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019587439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3019587439
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3505608809
Short name T522
Test name
Test status
Simulation time 332000105426 ps
CPU time 704.54 seconds
Started Jul 28 06:39:19 PM PDT 24
Finished Jul 28 06:51:04 PM PDT 24
Peak memory 201256 kb
Host smart-abc5e90a-a12c-4c49-b940-a6613f892bab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505608809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3505608809
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4216832841
Short name T575
Test name
Test status
Simulation time 162371692222 ps
CPU time 191.53 seconds
Started Jul 28 06:39:20 PM PDT 24
Finished Jul 28 06:42:31 PM PDT 24
Peak memory 201224 kb
Host smart-ca67556d-4711-4d8a-9fd3-e159b99d70f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216832841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4216832841
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.778600529
Short name T422
Test name
Test status
Simulation time 328107094171 ps
CPU time 48.64 seconds
Started Jul 28 06:39:18 PM PDT 24
Finished Jul 28 06:40:07 PM PDT 24
Peak memory 201072 kb
Host smart-d8f3bf31-4d0b-4ef8-95e0-fc9a8e292db5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=778600529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.778600529
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2921536763
Short name T537
Test name
Test status
Simulation time 392903772884 ps
CPU time 830.12 seconds
Started Jul 28 06:39:27 PM PDT 24
Finished Jul 28 06:53:17 PM PDT 24
Peak memory 201208 kb
Host smart-c8b5864a-a748-4cfd-a2e9-681e1027519d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921536763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2921536763
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.468618929
Short name T448
Test name
Test status
Simulation time 38948374106 ps
CPU time 47.47 seconds
Started Jul 28 06:39:27 PM PDT 24
Finished Jul 28 06:40:14 PM PDT 24
Peak memory 201004 kb
Host smart-f3bf07de-101a-499c-957d-e1c7f38ec514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468618929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.468618929
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1711029390
Short name T399
Test name
Test status
Simulation time 5414443521 ps
CPU time 3.49 seconds
Started Jul 28 06:39:26 PM PDT 24
Finished Jul 28 06:39:29 PM PDT 24
Peak memory 201060 kb
Host smart-da4b8c48-318d-4632-9c7f-83565d74d821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711029390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1711029390
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1425311672
Short name T69
Test name
Test status
Simulation time 7900574330 ps
CPU time 18.1 seconds
Started Jul 28 06:39:33 PM PDT 24
Finished Jul 28 06:39:51 PM PDT 24
Peak memory 217852 kb
Host smart-b87ca764-251f-4f96-a4ac-420b1b9454e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425311672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1425311672
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3058936679
Short name T544
Test name
Test status
Simulation time 5724082019 ps
CPU time 8.39 seconds
Started Jul 28 06:39:20 PM PDT 24
Finished Jul 28 06:39:28 PM PDT 24
Peak memory 201072 kb
Host smart-447af159-5155-4847-aa79-66588b9ca911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058936679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3058936679
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1052901672
Short name T349
Test name
Test status
Simulation time 491334965105 ps
CPU time 1171.44 seconds
Started Jul 28 06:39:33 PM PDT 24
Finished Jul 28 06:59:05 PM PDT 24
Peak memory 201236 kb
Host smart-4b15019a-40cc-4f2c-a212-9b572c950228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052901672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1052901672
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2392500276
Short name T450
Test name
Test status
Simulation time 398675435 ps
CPU time 1.51 seconds
Started Jul 28 06:46:16 PM PDT 24
Finished Jul 28 06:46:18 PM PDT 24
Peak memory 200964 kb
Host smart-59e66322-1a76-483a-94b2-7ff41de363d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392500276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2392500276
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2271211556
Short name T662
Test name
Test status
Simulation time 568704093699 ps
CPU time 182 seconds
Started Jul 28 06:46:14 PM PDT 24
Finished Jul 28 06:49:16 PM PDT 24
Peak memory 201132 kb
Host smart-0821d9a2-f983-468e-af14-c9c48cc6071b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271211556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2271211556
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1079988054
Short name T356
Test name
Test status
Simulation time 544441969203 ps
CPU time 1183.82 seconds
Started Jul 28 06:46:12 PM PDT 24
Finished Jul 28 07:05:56 PM PDT 24
Peak memory 201168 kb
Host smart-052c38c9-ee89-4bda-bc3f-4a0227050f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079988054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1079988054
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2896728232
Short name T30
Test name
Test status
Simulation time 334410699780 ps
CPU time 750.75 seconds
Started Jul 28 06:46:07 PM PDT 24
Finished Jul 28 06:58:38 PM PDT 24
Peak memory 201376 kb
Host smart-d647154b-4369-435c-b942-86b5e9c74145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896728232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2896728232
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2668946632
Short name T758
Test name
Test status
Simulation time 325545639146 ps
CPU time 117.77 seconds
Started Jul 28 06:46:09 PM PDT 24
Finished Jul 28 06:48:07 PM PDT 24
Peak memory 201144 kb
Host smart-239aa37d-0050-4a93-9336-d6a71c701c2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668946632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2668946632
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1447892970
Short name T665
Test name
Test status
Simulation time 169876216891 ps
CPU time 40.55 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 06:46:42 PM PDT 24
Peak memory 201112 kb
Host smart-e974e63d-f56b-4538-b81b-c0c8803144ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447892970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1447892970
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4107677068
Short name T586
Test name
Test status
Simulation time 330425755903 ps
CPU time 202.15 seconds
Started Jul 28 06:46:06 PM PDT 24
Finished Jul 28 06:49:29 PM PDT 24
Peak memory 201120 kb
Host smart-bfa5edf0-d62c-4f59-96d2-7576ed1b76a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107677068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4107677068
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3061972903
Short name T329
Test name
Test status
Simulation time 386041447087 ps
CPU time 812.63 seconds
Started Jul 28 06:46:05 PM PDT 24
Finished Jul 28 06:59:38 PM PDT 24
Peak memory 201092 kb
Host smart-289086cf-702a-4e8c-b21a-4582389640fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061972903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3061972903
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2293763976
Short name T699
Test name
Test status
Simulation time 381904540142 ps
CPU time 436.45 seconds
Started Jul 28 06:46:13 PM PDT 24
Finished Jul 28 06:53:30 PM PDT 24
Peak memory 201148 kb
Host smart-c51f3a64-aa9b-4983-8f3c-5694426e4853
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293763976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2293763976
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.408943984
Short name T703
Test name
Test status
Simulation time 96158093121 ps
CPU time 311.06 seconds
Started Jul 28 06:46:17 PM PDT 24
Finished Jul 28 06:51:28 PM PDT 24
Peak memory 201612 kb
Host smart-f5c2d477-2ffd-49aa-8d96-14888ddb15f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408943984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.408943984
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1047723871
Short name T105
Test name
Test status
Simulation time 41308670314 ps
CPU time 45.46 seconds
Started Jul 28 06:46:18 PM PDT 24
Finished Jul 28 06:47:04 PM PDT 24
Peak memory 200992 kb
Host smart-fada26be-c3b6-428e-8969-583289f7d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047723871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1047723871
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.956775828
Short name T499
Test name
Test status
Simulation time 4456013078 ps
CPU time 5.74 seconds
Started Jul 28 06:46:13 PM PDT 24
Finished Jul 28 06:46:19 PM PDT 24
Peak memory 200952 kb
Host smart-5c1beaac-173f-4141-af92-ce678abf78ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956775828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.956775828
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.666853957
Short name T550
Test name
Test status
Simulation time 5820762987 ps
CPU time 14.16 seconds
Started Jul 28 06:46:02 PM PDT 24
Finished Jul 28 06:46:16 PM PDT 24
Peak memory 201000 kb
Host smart-7c2adff7-2d49-4577-9b88-de342bdc7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666853957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.666853957
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.745932001
Short name T219
Test name
Test status
Simulation time 148315258822 ps
CPU time 523.59 seconds
Started Jul 28 06:46:16 PM PDT 24
Finished Jul 28 06:55:00 PM PDT 24
Peak memory 211328 kb
Host smart-47ee67df-dd75-431c-a8df-8db23113a3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745932001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
745932001
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1321685220
Short name T167
Test name
Test status
Simulation time 489730305 ps
CPU time 0.91 seconds
Started Jul 28 06:46:39 PM PDT 24
Finished Jul 28 06:46:40 PM PDT 24
Peak memory 200880 kb
Host smart-24a6663b-e6f8-45c6-96a7-b40511a0c19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321685220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1321685220
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.47575700
Short name T147
Test name
Test status
Simulation time 167544165631 ps
CPU time 103.93 seconds
Started Jul 28 06:46:33 PM PDT 24
Finished Jul 28 06:48:17 PM PDT 24
Peak memory 201140 kb
Host smart-c37945de-b819-4e0c-b0da-91a69e38e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47575700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.47575700
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1993852400
Short name T667
Test name
Test status
Simulation time 160754352101 ps
CPU time 287.16 seconds
Started Jul 28 06:46:29 PM PDT 24
Finished Jul 28 06:51:16 PM PDT 24
Peak memory 201084 kb
Host smart-cb1c2a8b-f98f-4d3f-89c5-80d078ba8a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993852400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1993852400
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2042886926
Short name T676
Test name
Test status
Simulation time 500405163709 ps
CPU time 481.21 seconds
Started Jul 28 06:46:28 PM PDT 24
Finished Jul 28 06:54:30 PM PDT 24
Peak memory 201152 kb
Host smart-2d548a05-c0cd-46c4-ae38-d2ea645c9c92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042886926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2042886926
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4102668808
Short name T334
Test name
Test status
Simulation time 159149469081 ps
CPU time 392.85 seconds
Started Jul 28 06:46:29 PM PDT 24
Finished Jul 28 06:53:02 PM PDT 24
Peak memory 201144 kb
Host smart-a9a2b946-d8a7-451f-b5ad-33ca20427e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102668808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4102668808
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4123532223
Short name T695
Test name
Test status
Simulation time 487764803521 ps
CPU time 1149.84 seconds
Started Jul 28 06:46:29 PM PDT 24
Finished Jul 28 07:05:39 PM PDT 24
Peak memory 201200 kb
Host smart-cee837f7-79c3-4627-8659-3efa53c4c386
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123532223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4123532223
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2596350113
Short name T302
Test name
Test status
Simulation time 343394855547 ps
CPU time 201.16 seconds
Started Jul 28 06:46:29 PM PDT 24
Finished Jul 28 06:49:50 PM PDT 24
Peak memory 201108 kb
Host smart-fa3d50e3-29c0-4b75-9eab-76ef414aafce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596350113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2596350113
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3782846546
Short name T161
Test name
Test status
Simulation time 410610416598 ps
CPU time 76.49 seconds
Started Jul 28 06:46:30 PM PDT 24
Finished Jul 28 06:47:46 PM PDT 24
Peak memory 201140 kb
Host smart-9bd24951-f839-4a05-8ab1-0013bb73a033
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782846546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3782846546
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2933409973
Short name T42
Test name
Test status
Simulation time 79295674350 ps
CPU time 290.76 seconds
Started Jul 28 06:46:34 PM PDT 24
Finished Jul 28 06:51:24 PM PDT 24
Peak memory 201576 kb
Host smart-e25701aa-f798-4e54-8bb3-22d2451b3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933409973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2933409973
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2656154691
Short name T434
Test name
Test status
Simulation time 40960451564 ps
CPU time 86.92 seconds
Started Jul 28 06:46:36 PM PDT 24
Finished Jul 28 06:48:03 PM PDT 24
Peak memory 200980 kb
Host smart-ed986403-ad73-4e86-ac23-97ac48e7ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656154691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2656154691
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1210365379
Short name T209
Test name
Test status
Simulation time 6043234499 ps
CPU time 3.96 seconds
Started Jul 28 06:46:32 PM PDT 24
Finished Jul 28 06:46:36 PM PDT 24
Peak memory 201040 kb
Host smart-f97b7cd6-1e39-4ec0-8994-95b99631b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210365379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1210365379
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.619251119
Short name T503
Test name
Test status
Simulation time 5458145107 ps
CPU time 14.11 seconds
Started Jul 28 06:46:23 PM PDT 24
Finished Jul 28 06:46:38 PM PDT 24
Peak memory 201040 kb
Host smart-7568b11b-55a1-4409-95ea-2ac28ddff7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619251119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.619251119
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2086886681
Short name T32
Test name
Test status
Simulation time 28903206143 ps
CPU time 71.34 seconds
Started Jul 28 06:46:34 PM PDT 24
Finished Jul 28 06:47:46 PM PDT 24
Peak memory 201064 kb
Host smart-600db273-dea9-488d-87d2-22130e09888e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086886681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2086886681
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4030762477
Short name T388
Test name
Test status
Simulation time 354750354 ps
CPU time 0.97 seconds
Started Jul 28 06:46:52 PM PDT 24
Finished Jul 28 06:46:53 PM PDT 24
Peak memory 200968 kb
Host smart-743dd1df-f4ad-4044-b458-0c9d9a454cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030762477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4030762477
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2756140689
Short name T508
Test name
Test status
Simulation time 513070866979 ps
CPU time 1164.07 seconds
Started Jul 28 06:46:46 PM PDT 24
Finished Jul 28 07:06:10 PM PDT 24
Peak memory 201156 kb
Host smart-2d2e28ea-ef8d-4d03-b75a-748b9acff587
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756140689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2756140689
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1744816658
Short name T200
Test name
Test status
Simulation time 494107689662 ps
CPU time 275.7 seconds
Started Jul 28 06:46:46 PM PDT 24
Finished Jul 28 06:51:22 PM PDT 24
Peak memory 201156 kb
Host smart-d96f2cd9-0bb8-41e9-b90a-3d46cf719756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744816658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1744816658
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3989049927
Short name T576
Test name
Test status
Simulation time 489918907498 ps
CPU time 1158.93 seconds
Started Jul 28 06:46:45 PM PDT 24
Finished Jul 28 07:06:04 PM PDT 24
Peak memory 201140 kb
Host smart-380ac9a2-f99c-4696-b822-9cd021bc65b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989049927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3989049927
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1400461129
Short name T566
Test name
Test status
Simulation time 492211160904 ps
CPU time 586.36 seconds
Started Jul 28 06:46:44 PM PDT 24
Finished Jul 28 06:56:31 PM PDT 24
Peak memory 201144 kb
Host smart-26453d10-b8a6-43f0-8c1a-d09a25e1ef03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400461129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1400461129
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3903831252
Short name T647
Test name
Test status
Simulation time 162992193322 ps
CPU time 94.03 seconds
Started Jul 28 06:46:40 PM PDT 24
Finished Jul 28 06:48:14 PM PDT 24
Peak memory 201176 kb
Host smart-72bcc172-fe4d-467f-8bc9-1afbedb9b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903831252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3903831252
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2013406888
Short name T505
Test name
Test status
Simulation time 495385796675 ps
CPU time 1090.5 seconds
Started Jul 28 06:46:39 PM PDT 24
Finished Jul 28 07:04:50 PM PDT 24
Peak memory 201164 kb
Host smart-c13033d7-900e-4c1e-a076-c74436247ed4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013406888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2013406888
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3879870204
Short name T314
Test name
Test status
Simulation time 173291197523 ps
CPU time 47.06 seconds
Started Jul 28 06:46:45 PM PDT 24
Finished Jul 28 06:47:32 PM PDT 24
Peak memory 201208 kb
Host smart-7e36f3a0-56b5-4e9f-a04f-bc6d67bed097
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879870204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3879870204
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3753536870
Short name T95
Test name
Test status
Simulation time 405143136635 ps
CPU time 926.39 seconds
Started Jul 28 06:46:45 PM PDT 24
Finished Jul 28 07:02:11 PM PDT 24
Peak memory 201220 kb
Host smart-f1bfe300-9b08-49a9-b064-852951bcab5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753536870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3753536870
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3118459736
Short name T560
Test name
Test status
Simulation time 119602357262 ps
CPU time 431.84 seconds
Started Jul 28 06:46:46 PM PDT 24
Finished Jul 28 06:53:58 PM PDT 24
Peak memory 201652 kb
Host smart-33f51ba4-a9b5-467c-8d08-2bf29116a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118459736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3118459736
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.706929726
Short name T489
Test name
Test status
Simulation time 32334081608 ps
CPU time 69.03 seconds
Started Jul 28 06:46:46 PM PDT 24
Finished Jul 28 06:47:55 PM PDT 24
Peak memory 201020 kb
Host smart-646b562f-f415-46b8-926d-3b932f97873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706929726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.706929726
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4138350968
Short name T474
Test name
Test status
Simulation time 3785269559 ps
CPU time 4.74 seconds
Started Jul 28 06:46:46 PM PDT 24
Finished Jul 28 06:46:51 PM PDT 24
Peak memory 201012 kb
Host smart-4fe37422-ca7a-443c-ac30-a0a4b5ed018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138350968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4138350968
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1999365701
Short name T390
Test name
Test status
Simulation time 6126514031 ps
CPU time 13.15 seconds
Started Jul 28 06:46:39 PM PDT 24
Finished Jul 28 06:46:52 PM PDT 24
Peak memory 201008 kb
Host smart-ad46e9f4-0afc-446f-b6f3-bf6a660ec117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999365701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1999365701
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1265799833
Short name T535
Test name
Test status
Simulation time 500904481246 ps
CPU time 1079.42 seconds
Started Jul 28 06:46:51 PM PDT 24
Finished Jul 28 07:04:51 PM PDT 24
Peak memory 201188 kb
Host smart-811707ab-08e5-4436-924f-0cbfa722fdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265799833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1265799833
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2782669451
Short name T393
Test name
Test status
Simulation time 421528171 ps
CPU time 1.55 seconds
Started Jul 28 06:47:08 PM PDT 24
Finished Jul 28 06:47:10 PM PDT 24
Peak memory 200952 kb
Host smart-35d039b2-14ac-42c4-acf9-b464f87afe16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782669451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2782669451
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3927221958
Short name T249
Test name
Test status
Simulation time 170830621186 ps
CPU time 45.28 seconds
Started Jul 28 06:46:58 PM PDT 24
Finished Jul 28 06:47:43 PM PDT 24
Peak memory 201160 kb
Host smart-5a2959de-48f5-48fd-99fb-d03c29064a3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927221958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3927221958
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1615078851
Short name T761
Test name
Test status
Simulation time 330186758286 ps
CPU time 779.02 seconds
Started Jul 28 06:46:53 PM PDT 24
Finished Jul 28 06:59:52 PM PDT 24
Peak memory 201184 kb
Host smart-7b76da7e-46ea-47c5-a786-4db56e6bc286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615078851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1615078851
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1983061418
Short name T405
Test name
Test status
Simulation time 166514566384 ps
CPU time 94.03 seconds
Started Jul 28 06:46:58 PM PDT 24
Finished Jul 28 06:48:32 PM PDT 24
Peak memory 201176 kb
Host smart-46b530f7-d6c2-4714-9dcd-0704fc1a3582
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983061418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1983061418
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4258796741
Short name T181
Test name
Test status
Simulation time 493945356483 ps
CPU time 241.15 seconds
Started Jul 28 06:46:51 PM PDT 24
Finished Jul 28 06:50:52 PM PDT 24
Peak memory 201384 kb
Host smart-af6e9c0d-f7d1-4282-aaf9-6076ca19e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258796741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4258796741
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1582202648
Short name T688
Test name
Test status
Simulation time 318695440856 ps
CPU time 195.97 seconds
Started Jul 28 06:46:51 PM PDT 24
Finished Jul 28 06:50:07 PM PDT 24
Peak memory 201152 kb
Host smart-e2fa2d95-e4dc-43b8-b7a9-c8bbf540fe95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582202648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1582202648
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.751108347
Short name T256
Test name
Test status
Simulation time 178476634455 ps
CPU time 207.12 seconds
Started Jul 28 06:46:58 PM PDT 24
Finished Jul 28 06:50:25 PM PDT 24
Peak memory 201156 kb
Host smart-ab60215a-a300-4c20-a5db-43996b70100d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751108347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.751108347
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.729117750
Short name T653
Test name
Test status
Simulation time 190851711336 ps
CPU time 299.15 seconds
Started Jul 28 06:46:57 PM PDT 24
Finished Jul 28 06:51:56 PM PDT 24
Peak memory 201156 kb
Host smart-e28cf4cf-769e-480a-aad8-4c01a51e76b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729117750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.729117750
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3620944799
Short name T1
Test name
Test status
Simulation time 88230135873 ps
CPU time 327.69 seconds
Started Jul 28 06:47:03 PM PDT 24
Finished Jul 28 06:52:31 PM PDT 24
Peak memory 201592 kb
Host smart-e6eec559-978d-427f-abba-066392fce4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620944799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3620944799
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.714080959
Short name T779
Test name
Test status
Simulation time 34356096262 ps
CPU time 81.81 seconds
Started Jul 28 06:47:03 PM PDT 24
Finished Jul 28 06:48:25 PM PDT 24
Peak memory 200956 kb
Host smart-4b71a69d-2978-442a-9bf0-4afac2be13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714080959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.714080959
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2222301885
Short name T707
Test name
Test status
Simulation time 4903198350 ps
CPU time 6.21 seconds
Started Jul 28 06:47:02 PM PDT 24
Finished Jul 28 06:47:08 PM PDT 24
Peak memory 201012 kb
Host smart-6241c2de-b4f2-4ed7-9125-a0c69c17565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222301885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2222301885
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3531913632
Short name T644
Test name
Test status
Simulation time 5985966963 ps
CPU time 14.36 seconds
Started Jul 28 06:46:50 PM PDT 24
Finished Jul 28 06:47:04 PM PDT 24
Peak memory 201012 kb
Host smart-d54dd5d2-e2d9-4d48-8ddf-c380eb845189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531913632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3531913632
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1596777567
Short name T40
Test name
Test status
Simulation time 188127420128 ps
CPU time 203.6 seconds
Started Jul 28 06:47:08 PM PDT 24
Finished Jul 28 06:50:31 PM PDT 24
Peak memory 201216 kb
Host smart-e132d213-f53d-42ee-a412-c71e061b3d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596777567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1596777567
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2956692454
Short name T583
Test name
Test status
Simulation time 17112287094 ps
CPU time 52.36 seconds
Started Jul 28 06:47:01 PM PDT 24
Finished Jul 28 06:47:54 PM PDT 24
Peak memory 209940 kb
Host smart-69cc2477-48f9-4b91-b8fc-c5e6f9d29c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956692454 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2956692454
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.879215739
Short name T372
Test name
Test status
Simulation time 419681391 ps
CPU time 0.95 seconds
Started Jul 28 06:47:14 PM PDT 24
Finished Jul 28 06:47:15 PM PDT 24
Peak memory 200896 kb
Host smart-0a72d298-2e43-47e4-b77b-a4ca2ff724e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879215739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.879215739
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1653324040
Short name T724
Test name
Test status
Simulation time 517655400049 ps
CPU time 1215.69 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 07:07:30 PM PDT 24
Peak memory 201132 kb
Host smart-67a1c2db-ef0f-4ed7-98c6-6ac92b12e40e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653324040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1653324040
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1869827552
Short name T212
Test name
Test status
Simulation time 383087334556 ps
CPU time 248.08 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:51:23 PM PDT 24
Peak memory 201224 kb
Host smart-6645a0f7-3f28-47f0-992c-deda3f39f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869827552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1869827552
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1654835921
Short name T89
Test name
Test status
Simulation time 489742137332 ps
CPU time 279.73 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:51:55 PM PDT 24
Peak memory 201264 kb
Host smart-a4b780fc-be28-46f2-bd19-d3604aba8a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654835921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1654835921
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3625190616
Short name T523
Test name
Test status
Simulation time 482427105446 ps
CPU time 294.06 seconds
Started Jul 28 06:47:16 PM PDT 24
Finished Jul 28 06:52:10 PM PDT 24
Peak memory 201072 kb
Host smart-fc46b7ca-588f-4f9e-ae4d-72e1d1e181d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625190616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3625190616
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2906092392
Short name T561
Test name
Test status
Simulation time 166720097537 ps
CPU time 98.08 seconds
Started Jul 28 06:47:08 PM PDT 24
Finished Jul 28 06:48:46 PM PDT 24
Peak memory 201164 kb
Host smart-c4649710-33e7-42bf-afdd-53dc26dfef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906092392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2906092392
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3911042582
Short name T567
Test name
Test status
Simulation time 484802305896 ps
CPU time 556.77 seconds
Started Jul 28 06:47:09 PM PDT 24
Finished Jul 28 06:56:25 PM PDT 24
Peak memory 201128 kb
Host smart-37ed910b-30f5-406e-85c4-8c162ffbc081
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911042582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3911042582
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1818833760
Short name T11
Test name
Test status
Simulation time 178153122140 ps
CPU time 230.09 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:51:05 PM PDT 24
Peak memory 201120 kb
Host smart-4c833a54-4df6-43de-a85d-14417351debf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818833760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1818833760
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.289214250
Short name T457
Test name
Test status
Simulation time 205566524849 ps
CPU time 225.94 seconds
Started Jul 28 06:47:14 PM PDT 24
Finished Jul 28 06:51:00 PM PDT 24
Peak memory 201184 kb
Host smart-38949c90-6766-470a-b02d-b990f12ff065
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289214250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.289214250
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.172654774
Short name T228
Test name
Test status
Simulation time 77760827227 ps
CPU time 256.93 seconds
Started Jul 28 06:47:17 PM PDT 24
Finished Jul 28 06:51:34 PM PDT 24
Peak memory 201636 kb
Host smart-6cf071ca-3b4b-4fe8-afd0-11b8bbe00edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172654774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.172654774
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3894364935
Short name T512
Test name
Test status
Simulation time 24094178768 ps
CPU time 36.68 seconds
Started Jul 28 06:47:16 PM PDT 24
Finished Jul 28 06:47:53 PM PDT 24
Peak memory 201028 kb
Host smart-10cb340d-6fda-4982-83f8-b0d9ecba27bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894364935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3894364935
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.838988654
Short name T104
Test name
Test status
Simulation time 5188144754 ps
CPU time 12.59 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:47:27 PM PDT 24
Peak memory 200988 kb
Host smart-d16df2a0-907d-449c-8040-498d09a34c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838988654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.838988654
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3901516280
Short name T514
Test name
Test status
Simulation time 5740189134 ps
CPU time 6.86 seconds
Started Jul 28 06:47:10 PM PDT 24
Finished Jul 28 06:47:17 PM PDT 24
Peak memory 201044 kb
Host smart-89ff6bd5-7c5a-4c8b-9a22-e12a22b92ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901516280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3901516280
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3248260489
Short name T263
Test name
Test status
Simulation time 178535063089 ps
CPU time 114.04 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:49:10 PM PDT 24
Peak memory 201204 kb
Host smart-8e9f63cf-8156-4ecd-acb7-dcc19fd0242b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248260489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3248260489
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.932283007
Short name T21
Test name
Test status
Simulation time 216766943062 ps
CPU time 108.54 seconds
Started Jul 28 06:47:15 PM PDT 24
Finished Jul 28 06:49:03 PM PDT 24
Peak memory 209516 kb
Host smart-fbd8cb87-9019-48e2-9e6e-832648ed52ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932283007 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.932283007
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3557547787
Short name T716
Test name
Test status
Simulation time 485934894 ps
CPU time 1.61 seconds
Started Jul 28 06:47:28 PM PDT 24
Finished Jul 28 06:47:30 PM PDT 24
Peak memory 200988 kb
Host smart-47ca0d76-b4d4-44d8-a8ce-945c969c52de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557547787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3557547787
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4000252936
Short name T211
Test name
Test status
Simulation time 336530123255 ps
CPU time 766.09 seconds
Started Jul 28 06:47:28 PM PDT 24
Finished Jul 28 07:00:15 PM PDT 24
Peak memory 201212 kb
Host smart-cf23a1b4-445b-4edf-aa34-9be40f5130bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000252936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4000252936
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3119694730
Short name T144
Test name
Test status
Simulation time 496327886067 ps
CPU time 280.59 seconds
Started Jul 28 06:47:22 PM PDT 24
Finished Jul 28 06:52:03 PM PDT 24
Peak memory 201204 kb
Host smart-95becb90-2547-4fb8-b54c-8807a73b2207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119694730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3119694730
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1019141163
Short name T385
Test name
Test status
Simulation time 323520157698 ps
CPU time 587.5 seconds
Started Jul 28 06:47:22 PM PDT 24
Finished Jul 28 06:57:10 PM PDT 24
Peak memory 201188 kb
Host smart-35478d4a-85cb-4c9f-9dd8-06a2e890ca51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019141163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1019141163
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1820227424
Short name T317
Test name
Test status
Simulation time 163533862107 ps
CPU time 407.46 seconds
Started Jul 28 06:47:21 PM PDT 24
Finished Jul 28 06:54:09 PM PDT 24
Peak memory 201204 kb
Host smart-1709b50f-1999-4405-b678-1895415c752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820227424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1820227424
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1003903099
Short name T585
Test name
Test status
Simulation time 166492947551 ps
CPU time 229.18 seconds
Started Jul 28 06:47:23 PM PDT 24
Finished Jul 28 06:51:12 PM PDT 24
Peak memory 201088 kb
Host smart-94fdf7a9-203b-461c-8074-b96c229acedd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003903099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1003903099
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2004987840
Short name T77
Test name
Test status
Simulation time 465226556747 ps
CPU time 1059.41 seconds
Started Jul 28 06:47:22 PM PDT 24
Finished Jul 28 07:05:01 PM PDT 24
Peak memory 201208 kb
Host smart-b6a30920-64d8-492a-950d-4c68da904bd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004987840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2004987840
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2663829644
Short name T412
Test name
Test status
Simulation time 206287510048 ps
CPU time 471.12 seconds
Started Jul 28 06:47:22 PM PDT 24
Finished Jul 28 06:55:13 PM PDT 24
Peak memory 201232 kb
Host smart-66680fc1-de14-4efc-9ccf-3e4d7fc3132b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663829644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2663829644
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.23617951
Short name T224
Test name
Test status
Simulation time 70666882220 ps
CPU time 309.56 seconds
Started Jul 28 06:47:26 PM PDT 24
Finished Jul 28 06:52:36 PM PDT 24
Peak memory 201628 kb
Host smart-505a6e08-5bc9-4e77-a34b-c383ca411037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23617951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.23617951
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.682803034
Short name T649
Test name
Test status
Simulation time 42540625335 ps
CPU time 93.26 seconds
Started Jul 28 06:47:29 PM PDT 24
Finished Jul 28 06:49:02 PM PDT 24
Peak memory 200996 kb
Host smart-fa141f00-c135-4fed-a73b-48677acad543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682803034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.682803034
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.479685622
Short name T785
Test name
Test status
Simulation time 4001433176 ps
CPU time 3.12 seconds
Started Jul 28 06:47:27 PM PDT 24
Finished Jul 28 06:47:30 PM PDT 24
Peak memory 200956 kb
Host smart-46c49c80-4e3e-4b04-995a-117a7d14f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479685622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.479685622
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3224770852
Short name T739
Test name
Test status
Simulation time 5928544214 ps
CPU time 4.66 seconds
Started Jul 28 06:47:16 PM PDT 24
Finished Jul 28 06:47:21 PM PDT 24
Peak memory 200944 kb
Host smart-efb34463-f555-4be4-b780-2ffb439f13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224770852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3224770852
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1173157015
Short name T673
Test name
Test status
Simulation time 320012228 ps
CPU time 1.29 seconds
Started Jul 28 06:47:50 PM PDT 24
Finished Jul 28 06:47:51 PM PDT 24
Peak memory 200960 kb
Host smart-c5edb776-6044-47d1-8b8f-827e00ed7261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173157015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1173157015
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.616185839
Short name T552
Test name
Test status
Simulation time 172852455073 ps
CPU time 40.37 seconds
Started Jul 28 06:47:33 PM PDT 24
Finished Jul 28 06:48:13 PM PDT 24
Peak memory 201160 kb
Host smart-f4d78a15-35bf-4e83-9256-42345dafe8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616185839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.616185839
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2856481188
Short name T506
Test name
Test status
Simulation time 487893960401 ps
CPU time 280.88 seconds
Started Jul 28 06:47:32 PM PDT 24
Finished Jul 28 06:52:13 PM PDT 24
Peak memory 201144 kb
Host smart-e141086b-b714-4ce5-9bf4-f305408f5fd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856481188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2856481188
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.551710580
Short name T169
Test name
Test status
Simulation time 167608158581 ps
CPU time 187.09 seconds
Started Jul 28 06:47:32 PM PDT 24
Finished Jul 28 06:50:39 PM PDT 24
Peak memory 201080 kb
Host smart-49299fcf-7166-4734-9089-1c6188331a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551710580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.551710580
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2258686165
Short name T798
Test name
Test status
Simulation time 165136900397 ps
CPU time 189.13 seconds
Started Jul 28 06:47:31 PM PDT 24
Finished Jul 28 06:50:41 PM PDT 24
Peak memory 201168 kb
Host smart-97ec4799-b8d4-4640-8090-0309e93280a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258686165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2258686165
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2843554969
Short name T654
Test name
Test status
Simulation time 193014715086 ps
CPU time 117.6 seconds
Started Jul 28 06:47:32 PM PDT 24
Finished Jul 28 06:49:30 PM PDT 24
Peak memory 201204 kb
Host smart-c2d3b1fd-7612-4a18-bea0-2d8fc45616bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843554969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2843554969
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2908828974
Short name T401
Test name
Test status
Simulation time 400698694434 ps
CPU time 929.72 seconds
Started Jul 28 06:47:39 PM PDT 24
Finished Jul 28 07:03:08 PM PDT 24
Peak memory 201248 kb
Host smart-84566907-3e75-4b70-9693-43cff072deb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908828974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2908828974
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1055905878
Short name T87
Test name
Test status
Simulation time 100226555075 ps
CPU time 506.4 seconds
Started Jul 28 06:47:44 PM PDT 24
Finished Jul 28 06:56:10 PM PDT 24
Peak memory 201592 kb
Host smart-193fbc94-5139-40e0-b3f8-e3f449b194d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055905878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1055905878
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2398394068
Short name T428
Test name
Test status
Simulation time 33041778937 ps
CPU time 38.62 seconds
Started Jul 28 06:47:44 PM PDT 24
Finished Jul 28 06:48:23 PM PDT 24
Peak memory 201048 kb
Host smart-84af43fb-5d4a-4bd6-af52-0d1f6b6c51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398394068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2398394068
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3397261924
Short name T763
Test name
Test status
Simulation time 2895732119 ps
CPU time 3.74 seconds
Started Jul 28 06:47:41 PM PDT 24
Finished Jul 28 06:47:45 PM PDT 24
Peak memory 201016 kb
Host smart-1fef603a-330a-4762-a41e-b3e53c29c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397261924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3397261924
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2053465790
Short name T624
Test name
Test status
Simulation time 5876657233 ps
CPU time 4.48 seconds
Started Jul 28 06:47:32 PM PDT 24
Finished Jul 28 06:47:36 PM PDT 24
Peak memory 201024 kb
Host smart-83d6682c-d75a-4c79-ae61-d158c163224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053465790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2053465790
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2469062415
Short name T747
Test name
Test status
Simulation time 11400487245 ps
CPU time 25.84 seconds
Started Jul 28 06:47:50 PM PDT 24
Finished Jul 28 06:48:15 PM PDT 24
Peak memory 201044 kb
Host smart-1f3043fb-81fc-47a5-92c8-76839cead214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469062415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2469062415
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4206150057
Short name T392
Test name
Test status
Simulation time 495184586 ps
CPU time 1.23 seconds
Started Jul 28 06:47:55 PM PDT 24
Finished Jul 28 06:47:57 PM PDT 24
Peak memory 200964 kb
Host smart-327ef313-0720-4684-9ea0-d1b21325010a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206150057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4206150057
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.435074207
Short name T603
Test name
Test status
Simulation time 192110927838 ps
CPU time 402.06 seconds
Started Jul 28 06:47:48 PM PDT 24
Finished Jul 28 06:54:30 PM PDT 24
Peak memory 201164 kb
Host smart-6a4b5461-9d7a-4d24-9e57-35f5daf0849d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435074207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.435074207
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3617715090
Short name T320
Test name
Test status
Simulation time 170094848324 ps
CPU time 370.98 seconds
Started Jul 28 06:47:49 PM PDT 24
Finished Jul 28 06:54:00 PM PDT 24
Peak memory 201104 kb
Host smart-7b03e4e7-e7f6-4ccd-b38c-76594dba3bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617715090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3617715090
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1012997936
Short name T355
Test name
Test status
Simulation time 325968024482 ps
CPU time 63.2 seconds
Started Jul 28 06:47:50 PM PDT 24
Finished Jul 28 06:48:53 PM PDT 24
Peak memory 201240 kb
Host smart-64946fab-7feb-4521-82e0-78af190507a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012997936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1012997936
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.675763737
Short name T765
Test name
Test status
Simulation time 323587951083 ps
CPU time 386.73 seconds
Started Jul 28 06:47:43 PM PDT 24
Finished Jul 28 06:54:10 PM PDT 24
Peak memory 201180 kb
Host smart-fdc8c6ed-ddea-41da-80e8-4ff618fc763e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=675763737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.675763737
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.454957345
Short name T208
Test name
Test status
Simulation time 489802611761 ps
CPU time 1147.16 seconds
Started Jul 28 06:47:44 PM PDT 24
Finished Jul 28 07:06:51 PM PDT 24
Peak memory 201232 kb
Host smart-caf00802-39c8-47a2-8d17-b6fc9975731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454957345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.454957345
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2467190846
Short name T408
Test name
Test status
Simulation time 496267053438 ps
CPU time 185.23 seconds
Started Jul 28 06:47:50 PM PDT 24
Finished Jul 28 06:50:55 PM PDT 24
Peak memory 201156 kb
Host smart-1cf26fca-2281-404a-9e06-f4eae973efab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467190846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2467190846
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3720909550
Short name T301
Test name
Test status
Simulation time 570912585948 ps
CPU time 1406.72 seconds
Started Jul 28 06:47:50 PM PDT 24
Finished Jul 28 07:11:17 PM PDT 24
Peak memory 201140 kb
Host smart-7b04d8ba-6e89-4eee-897d-24a086b34530
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720909550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3720909550
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3525513987
Short name T461
Test name
Test status
Simulation time 203767677578 ps
CPU time 231.27 seconds
Started Jul 28 06:47:49 PM PDT 24
Finished Jul 28 06:51:40 PM PDT 24
Peak memory 201124 kb
Host smart-b96f2c04-6397-4a1a-abf5-486cc694d820
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525513987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3525513987
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4062057959
Short name T623
Test name
Test status
Simulation time 97834239415 ps
CPU time 477.53 seconds
Started Jul 28 06:47:55 PM PDT 24
Finished Jul 28 06:55:53 PM PDT 24
Peak memory 201668 kb
Host smart-229b7162-3f7f-4a71-b861-e521a35cef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062057959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4062057959
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2015415985
Short name T525
Test name
Test status
Simulation time 23908810647 ps
CPU time 50.16 seconds
Started Jul 28 06:47:57 PM PDT 24
Finished Jul 28 06:48:48 PM PDT 24
Peak memory 201028 kb
Host smart-0308303e-7552-423b-b9ed-4e160ea48c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015415985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2015415985
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.402136387
Short name T76
Test name
Test status
Simulation time 3560780659 ps
CPU time 2.78 seconds
Started Jul 28 06:47:49 PM PDT 24
Finished Jul 28 06:47:52 PM PDT 24
Peak memory 201052 kb
Host smart-eab83e09-f17d-447f-8a23-a27ac12a3c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402136387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.402136387
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.212027483
Short name T367
Test name
Test status
Simulation time 5813997733 ps
CPU time 14.55 seconds
Started Jul 28 06:47:45 PM PDT 24
Finished Jul 28 06:47:59 PM PDT 24
Peak memory 201012 kb
Host smart-6e547b60-53a2-4202-abe8-9072141737ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212027483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.212027483
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.327326535
Short name T775
Test name
Test status
Simulation time 565828397426 ps
CPU time 785.98 seconds
Started Jul 28 06:47:54 PM PDT 24
Finished Jul 28 07:01:00 PM PDT 24
Peak memory 201112 kb
Host smart-185a85f8-a69a-4a65-b09c-5241ac121e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327326535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
327326535
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2431988947
Short name T98
Test name
Test status
Simulation time 147597271373 ps
CPU time 240.47 seconds
Started Jul 28 06:47:58 PM PDT 24
Finished Jul 28 06:51:58 PM PDT 24
Peak memory 209980 kb
Host smart-d2bdcddd-10f0-4fef-85aa-3fc2747cd0b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431988947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2431988947
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.518477855
Short name T415
Test name
Test status
Simulation time 376852163 ps
CPU time 0.77 seconds
Started Jul 28 06:48:13 PM PDT 24
Finished Jul 28 06:48:14 PM PDT 24
Peak memory 200928 kb
Host smart-50cf8784-2cdb-43da-add7-c9a3646fec13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518477855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.518477855
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.335789945
Short name T551
Test name
Test status
Simulation time 166573540449 ps
CPU time 258.39 seconds
Started Jul 28 06:48:07 PM PDT 24
Finished Jul 28 06:52:26 PM PDT 24
Peak memory 201168 kb
Host smart-5394486a-1b79-4720-bd81-634e076616ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335789945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.335789945
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.743926253
Short name T125
Test name
Test status
Simulation time 485281947734 ps
CPU time 551.09 seconds
Started Jul 28 06:48:05 PM PDT 24
Finished Jul 28 06:57:16 PM PDT 24
Peak memory 201120 kb
Host smart-7c3f0349-7c08-4a2b-9931-fc7f36c3e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743926253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.743926253
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.515219861
Short name T722
Test name
Test status
Simulation time 161561298020 ps
CPU time 366.6 seconds
Started Jul 28 06:47:59 PM PDT 24
Finished Jul 28 06:54:06 PM PDT 24
Peak memory 201136 kb
Host smart-46fc8cb8-4c0f-4dd9-9960-355cce032f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515219861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.515219861
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3430657365
Short name T439
Test name
Test status
Simulation time 166610979032 ps
CPU time 188.58 seconds
Started Jul 28 06:48:06 PM PDT 24
Finished Jul 28 06:51:15 PM PDT 24
Peak memory 201124 kb
Host smart-c5122182-d3c4-4276-a602-9cfb0d941650
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430657365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3430657365
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1980748702
Short name T138
Test name
Test status
Simulation time 494684645441 ps
CPU time 554.99 seconds
Started Jul 28 06:47:59 PM PDT 24
Finished Jul 28 06:57:14 PM PDT 24
Peak memory 201184 kb
Host smart-bb00c037-01e0-452b-8759-c99e95374f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980748702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1980748702
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.248817194
Short name T432
Test name
Test status
Simulation time 169849622658 ps
CPU time 406.22 seconds
Started Jul 28 06:48:03 PM PDT 24
Finished Jul 28 06:54:50 PM PDT 24
Peak memory 201152 kb
Host smart-5272f852-ac57-4735-8179-ac1ba141ea0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248817194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.248817194
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1140145049
Short name T309
Test name
Test status
Simulation time 389438944309 ps
CPU time 234.22 seconds
Started Jul 28 06:48:05 PM PDT 24
Finished Jul 28 06:51:59 PM PDT 24
Peak memory 201216 kb
Host smart-8f2b3598-80a2-40d3-ad51-2ff3ebd52ebe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140145049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1140145049
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1113951991
Short name T558
Test name
Test status
Simulation time 415698884920 ps
CPU time 272.86 seconds
Started Jul 28 06:48:04 PM PDT 24
Finished Jul 28 06:52:37 PM PDT 24
Peak memory 201084 kb
Host smart-b1a1a354-074b-401d-a4b9-7c8232654fcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113951991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1113951991
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3902498513
Short name T682
Test name
Test status
Simulation time 137984605634 ps
CPU time 714.98 seconds
Started Jul 28 06:48:08 PM PDT 24
Finished Jul 28 07:00:03 PM PDT 24
Peak memory 201600 kb
Host smart-a13c7f61-510b-4606-98ff-1d1b39160a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902498513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3902498513
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2175837207
Short name T679
Test name
Test status
Simulation time 25429325954 ps
CPU time 9.78 seconds
Started Jul 28 06:48:04 PM PDT 24
Finished Jul 28 06:48:14 PM PDT 24
Peak memory 200992 kb
Host smart-8f8ae51c-9d70-414c-a447-c81d45ad1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175837207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2175837207
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4175633800
Short name T626
Test name
Test status
Simulation time 4129945113 ps
CPU time 3.05 seconds
Started Jul 28 06:48:05 PM PDT 24
Finished Jul 28 06:48:08 PM PDT 24
Peak memory 201236 kb
Host smart-598903e6-a2e9-44b9-a854-12af9d98f7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175633800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4175633800
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3551807163
Short name T440
Test name
Test status
Simulation time 6084349082 ps
CPU time 14.9 seconds
Started Jul 28 06:48:04 PM PDT 24
Finished Jul 28 06:48:19 PM PDT 24
Peak memory 201040 kb
Host smart-4158db14-c6ea-40dd-8ea1-780f10331ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551807163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3551807163
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1705882568
Short name T41
Test name
Test status
Simulation time 743302500435 ps
CPU time 569.79 seconds
Started Jul 28 06:48:10 PM PDT 24
Finished Jul 28 06:57:40 PM PDT 24
Peak memory 211968 kb
Host smart-7864d62c-e8d7-4c15-8cda-8609b1897357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705882568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1705882568
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1548104281
Short name T362
Test name
Test status
Simulation time 107527600186 ps
CPU time 277.24 seconds
Started Jul 28 06:48:09 PM PDT 24
Finished Jul 28 06:52:46 PM PDT 24
Peak memory 218020 kb
Host smart-b8f4a44a-66cf-451e-a11c-16031e2a29e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548104281 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1548104281
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1394910886
Short name T458
Test name
Test status
Simulation time 454687926 ps
CPU time 1.7 seconds
Started Jul 28 06:48:34 PM PDT 24
Finished Jul 28 06:48:36 PM PDT 24
Peak memory 200960 kb
Host smart-51373a72-e101-49db-ba29-51c63d79f265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394910886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1394910886
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.220692314
Short name T721
Test name
Test status
Simulation time 189327116742 ps
CPU time 109.36 seconds
Started Jul 28 06:48:23 PM PDT 24
Finished Jul 28 06:50:12 PM PDT 24
Peak memory 201180 kb
Host smart-05745883-8c81-4826-bf88-dce283b05811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220692314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.220692314
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.979075089
Short name T793
Test name
Test status
Simulation time 159907967429 ps
CPU time 66.3 seconds
Started Jul 28 06:48:19 PM PDT 24
Finished Jul 28 06:49:25 PM PDT 24
Peak memory 201396 kb
Host smart-94b0dc96-1e95-4a4d-a932-9f814173bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979075089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.979075089
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3904805463
Short name T694
Test name
Test status
Simulation time 324375709940 ps
CPU time 761.11 seconds
Started Jul 28 06:48:20 PM PDT 24
Finished Jul 28 07:01:01 PM PDT 24
Peak memory 201088 kb
Host smart-dc4e8980-993f-48c3-a158-0548ee940648
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904805463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3904805463
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4146896846
Short name T545
Test name
Test status
Simulation time 166126330511 ps
CPU time 181.75 seconds
Started Jul 28 06:48:18 PM PDT 24
Finished Jul 28 06:51:20 PM PDT 24
Peak memory 201208 kb
Host smart-836a38df-6ff2-46df-bc44-18f1a8651536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146896846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4146896846
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.321117231
Short name T613
Test name
Test status
Simulation time 333791791138 ps
CPU time 410.38 seconds
Started Jul 28 06:48:18 PM PDT 24
Finished Jul 28 06:55:08 PM PDT 24
Peak memory 201168 kb
Host smart-f9d85de3-4c87-4474-8a71-e3bc3a47ec09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=321117231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.321117231
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2284307706
Short name T547
Test name
Test status
Simulation time 362987896381 ps
CPU time 581.32 seconds
Started Jul 28 06:48:18 PM PDT 24
Finished Jul 28 06:58:00 PM PDT 24
Peak memory 201264 kb
Host smart-04083c78-cda1-422b-8be6-13843d23f37b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284307706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2284307706
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3967080109
Short name T559
Test name
Test status
Simulation time 586447730931 ps
CPU time 701.1 seconds
Started Jul 28 06:48:24 PM PDT 24
Finished Jul 28 07:00:06 PM PDT 24
Peak memory 201160 kb
Host smart-32b4071d-e94c-4913-b70e-58aa6c7b1a2c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967080109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3967080109
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2646761721
Short name T43
Test name
Test status
Simulation time 133394155434 ps
CPU time 470.07 seconds
Started Jul 28 06:48:22 PM PDT 24
Finished Jul 28 06:56:13 PM PDT 24
Peak memory 201648 kb
Host smart-cec05228-529b-48e3-9805-26f5f1e988ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646761721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2646761721
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2544535912
Short name T157
Test name
Test status
Simulation time 31944012160 ps
CPU time 38.53 seconds
Started Jul 28 06:48:24 PM PDT 24
Finished Jul 28 06:49:02 PM PDT 24
Peak memory 200996 kb
Host smart-f50196a2-7654-450d-b438-3513ad8c38c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544535912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2544535912
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1821859076
Short name T84
Test name
Test status
Simulation time 3040700756 ps
CPU time 1.69 seconds
Started Jul 28 06:48:25 PM PDT 24
Finished Jul 28 06:48:27 PM PDT 24
Peak memory 201004 kb
Host smart-4f05d952-e969-4c82-8d64-b06e0abfca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821859076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1821859076
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.376441962
Short name T790
Test name
Test status
Simulation time 5892954274 ps
CPU time 4.58 seconds
Started Jul 28 06:48:14 PM PDT 24
Finished Jul 28 06:48:19 PM PDT 24
Peak memory 201036 kb
Host smart-d4d280a5-64e4-487a-996d-df4e13e8bbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376441962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.376441962
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3182502581
Short name T756
Test name
Test status
Simulation time 186572514316 ps
CPU time 232.57 seconds
Started Jul 28 06:48:27 PM PDT 24
Finished Jul 28 06:52:19 PM PDT 24
Peak memory 201236 kb
Host smart-bde63751-95fc-40c1-bf1c-ea7aebad2754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182502581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3182502581
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1088450138
Short name T704
Test name
Test status
Simulation time 65970390872 ps
CPU time 112.06 seconds
Started Jul 28 06:48:29 PM PDT 24
Finished Jul 28 06:50:21 PM PDT 24
Peak memory 212288 kb
Host smart-079fcf16-4a2e-4b33-ac1d-e58326a7e2f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088450138 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1088450138
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.465420922
Short name T740
Test name
Test status
Simulation time 516135205 ps
CPU time 0.71 seconds
Started Jul 28 06:39:48 PM PDT 24
Finished Jul 28 06:39:49 PM PDT 24
Peak memory 200960 kb
Host smart-05b8e074-7d04-40ac-80c7-58347d5bc39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465420922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.465420922
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.243420782
Short name T353
Test name
Test status
Simulation time 330881322212 ps
CPU time 394.54 seconds
Started Jul 28 06:39:38 PM PDT 24
Finished Jul 28 06:46:12 PM PDT 24
Peak memory 201192 kb
Host smart-40bad33e-d268-444b-bc95-788e6890e0a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243420782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.243420782
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1235209233
Short name T323
Test name
Test status
Simulation time 513115487061 ps
CPU time 304.95 seconds
Started Jul 28 06:39:42 PM PDT 24
Finished Jul 28 06:44:47 PM PDT 24
Peak memory 201208 kb
Host smart-26d32ca1-52bd-4cc0-8cc6-c23193cbdf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235209233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1235209233
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.272645415
Short name T593
Test name
Test status
Simulation time 491285402805 ps
CPU time 1056.09 seconds
Started Jul 28 06:39:38 PM PDT 24
Finished Jul 28 06:57:14 PM PDT 24
Peak memory 201188 kb
Host smart-0ef290e4-0b80-4b73-88d0-70ae2fabe66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272645415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.272645415
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4225725151
Short name T691
Test name
Test status
Simulation time 323375368068 ps
CPU time 196.77 seconds
Started Jul 28 06:39:38 PM PDT 24
Finished Jul 28 06:42:55 PM PDT 24
Peak memory 201108 kb
Host smart-72ba7143-e19a-4bbb-81c1-60009fc1b242
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225725151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4225725151
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1452511951
Short name T617
Test name
Test status
Simulation time 172552322795 ps
CPU time 195.51 seconds
Started Jul 28 06:39:39 PM PDT 24
Finished Jul 28 06:42:55 PM PDT 24
Peak memory 201156 kb
Host smart-e890c599-dcb5-4a22-b4d9-e69b4d36ebd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452511951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1452511951
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3864266809
Short name T156
Test name
Test status
Simulation time 380506012991 ps
CPU time 875.73 seconds
Started Jul 28 06:39:38 PM PDT 24
Finished Jul 28 06:54:14 PM PDT 24
Peak memory 201124 kb
Host smart-3cf0fa38-1bd5-464a-8feb-bd5e3ab76e16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864266809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3864266809
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2680147655
Short name T446
Test name
Test status
Simulation time 585746916516 ps
CPU time 171.2 seconds
Started Jul 28 06:39:38 PM PDT 24
Finished Jul 28 06:42:29 PM PDT 24
Peak memory 201176 kb
Host smart-16ec9750-910d-45b8-89d5-d0226dd150aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680147655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2680147655
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3709375945
Short name T230
Test name
Test status
Simulation time 130175562185 ps
CPU time 484.37 seconds
Started Jul 28 06:39:45 PM PDT 24
Finished Jul 28 06:47:50 PM PDT 24
Peak memory 201672 kb
Host smart-c3dbe9f8-34af-4b17-b74c-a0aa868b7e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709375945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3709375945
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3709546207
Short name T690
Test name
Test status
Simulation time 26252979791 ps
CPU time 16.09 seconds
Started Jul 28 06:39:44 PM PDT 24
Finished Jul 28 06:40:01 PM PDT 24
Peak memory 200984 kb
Host smart-0d6ead7f-c0b4-49ea-8b98-8d66098ad41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709546207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3709546207
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3022695389
Short name T524
Test name
Test status
Simulation time 4951257993 ps
CPU time 13.81 seconds
Started Jul 28 06:39:44 PM PDT 24
Finished Jul 28 06:39:58 PM PDT 24
Peak memory 201060 kb
Host smart-61d1c05b-2df0-46d5-b8c9-ffea3cfe9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022695389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3022695389
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.414287741
Short name T68
Test name
Test status
Simulation time 4265254560 ps
CPU time 9.24 seconds
Started Jul 28 06:39:43 PM PDT 24
Finished Jul 28 06:39:52 PM PDT 24
Peak memory 216776 kb
Host smart-4033f50d-774c-45f0-a276-c7b4da0d267f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414287741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.414287741
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2995562742
Short name T162
Test name
Test status
Simulation time 5949098742 ps
CPU time 4.78 seconds
Started Jul 28 06:39:32 PM PDT 24
Finished Jul 28 06:39:37 PM PDT 24
Peak memory 200952 kb
Host smart-98a969d1-aa74-419a-9f4f-31a353b6493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995562742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2995562742
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2417613402
Short name T330
Test name
Test status
Simulation time 366080456633 ps
CPU time 219.51 seconds
Started Jul 28 06:39:44 PM PDT 24
Finished Jul 28 06:43:24 PM PDT 24
Peak memory 201188 kb
Host smart-b8083579-470d-4db6-9b1d-cccba714674b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417613402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2417613402
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4279914026
Short name T15
Test name
Test status
Simulation time 63098238413 ps
CPU time 36.69 seconds
Started Jul 28 06:39:44 PM PDT 24
Finished Jul 28 06:40:21 PM PDT 24
Peak memory 210008 kb
Host smart-5587b79a-f6b3-43ad-a002-e9a895536ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279914026 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4279914026
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3204433997
Short name T666
Test name
Test status
Simulation time 348990836 ps
CPU time 0.87 seconds
Started Jul 28 06:48:46 PM PDT 24
Finished Jul 28 06:48:46 PM PDT 24
Peak memory 200980 kb
Host smart-cf4dc926-f0fe-4114-8cb2-01d256c2056c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204433997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3204433997
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1813014572
Short name T269
Test name
Test status
Simulation time 167622163982 ps
CPU time 96.91 seconds
Started Jul 28 06:48:37 PM PDT 24
Finished Jul 28 06:50:14 PM PDT 24
Peak memory 201216 kb
Host smart-1378976d-b36d-4bc8-ac10-9e2a9114bd36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813014572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1813014572
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.4069737772
Short name T611
Test name
Test status
Simulation time 497981590429 ps
CPU time 1011.24 seconds
Started Jul 28 06:48:32 PM PDT 24
Finished Jul 28 07:05:24 PM PDT 24
Peak memory 201164 kb
Host smart-ed233845-bd3c-4534-a7df-17360506ea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069737772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4069737772
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1625250498
Short name T783
Test name
Test status
Simulation time 166595939695 ps
CPU time 136.72 seconds
Started Jul 28 06:48:29 PM PDT 24
Finished Jul 28 06:50:46 PM PDT 24
Peak memory 201212 kb
Host smart-62f0c27b-3860-42aa-9bc9-2cb880fa40b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625250498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1625250498
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1556398158
Short name T490
Test name
Test status
Simulation time 164678570028 ps
CPU time 385.93 seconds
Started Jul 28 06:48:32 PM PDT 24
Finished Jul 28 06:54:58 PM PDT 24
Peak memory 201236 kb
Host smart-d45651aa-39d1-4713-9bff-f5cc08e54686
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556398158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1556398158
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4094724519
Short name T351
Test name
Test status
Simulation time 358536415103 ps
CPU time 864.7 seconds
Started Jul 28 06:48:37 PM PDT 24
Finished Jul 28 07:03:02 PM PDT 24
Peak memory 201176 kb
Host smart-bd7ddd9a-3025-40d2-b7ef-4661c4bbbb85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094724519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4094724519
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2817836906
Short name T736
Test name
Test status
Simulation time 590736171346 ps
CPU time 691.67 seconds
Started Jul 28 06:48:37 PM PDT 24
Finished Jul 28 07:00:09 PM PDT 24
Peak memory 201160 kb
Host smart-71741c23-dcdb-45e1-b8e8-d469da911f20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817836906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2817836906
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3058547626
Short name T621
Test name
Test status
Simulation time 82771135215 ps
CPU time 282.66 seconds
Started Jul 28 06:48:42 PM PDT 24
Finished Jul 28 06:53:25 PM PDT 24
Peak memory 201620 kb
Host smart-9227ed61-0735-4813-8e95-a3d5a3ab62f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058547626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3058547626
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1372902869
Short name T441
Test name
Test status
Simulation time 33022782229 ps
CPU time 38.8 seconds
Started Jul 28 06:48:44 PM PDT 24
Finished Jul 28 06:49:24 PM PDT 24
Peak memory 201028 kb
Host smart-f56be460-5158-4be6-814f-c172eea6b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372902869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1372902869
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4210328952
Short name T396
Test name
Test status
Simulation time 4437392427 ps
CPU time 5.72 seconds
Started Jul 28 06:48:42 PM PDT 24
Finished Jul 28 06:48:47 PM PDT 24
Peak memory 200968 kb
Host smart-393d9983-864e-403b-b1e2-789cdd861355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210328952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4210328952
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2971419541
Short name T528
Test name
Test status
Simulation time 6002689081 ps
CPU time 4.98 seconds
Started Jul 28 06:48:27 PM PDT 24
Finished Jul 28 06:48:32 PM PDT 24
Peak memory 201012 kb
Host smart-90930c65-3724-4634-885a-4a8a5244ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971419541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2971419541
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1075203581
Short name T631
Test name
Test status
Simulation time 372283369976 ps
CPU time 876.39 seconds
Started Jul 28 06:48:41 PM PDT 24
Finished Jul 28 07:03:18 PM PDT 24
Peak memory 211992 kb
Host smart-5021c182-741e-415e-9d01-284f197bb9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075203581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1075203581
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3589021046
Short name T759
Test name
Test status
Simulation time 389257587 ps
CPU time 1.02 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 06:48:52 PM PDT 24
Peak memory 200968 kb
Host smart-67fa16a2-3f4f-462f-98e0-f9f94730ffcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589021046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3589021046
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1574317620
Short name T297
Test name
Test status
Simulation time 166109071651 ps
CPU time 344.31 seconds
Started Jul 28 06:48:50 PM PDT 24
Finished Jul 28 06:54:35 PM PDT 24
Peak memory 201180 kb
Host smart-eac682d5-3888-44b9-bf6f-7c9d2795ec1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574317620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1574317620
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2545763345
Short name T316
Test name
Test status
Simulation time 165213545278 ps
CPU time 379.93 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 06:55:11 PM PDT 24
Peak memory 201152 kb
Host smart-55805a17-983c-453f-a250-f979324a08d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545763345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2545763345
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1165406488
Short name T496
Test name
Test status
Simulation time 170319666149 ps
CPU time 392.59 seconds
Started Jul 28 06:48:48 PM PDT 24
Finished Jul 28 06:55:21 PM PDT 24
Peak memory 201160 kb
Host smart-4b2a3e4e-0ea6-49e6-8f90-39be1b8de36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165406488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1165406488
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3616164738
Short name T634
Test name
Test status
Simulation time 493840739377 ps
CPU time 1177.82 seconds
Started Jul 28 06:48:45 PM PDT 24
Finished Jul 28 07:08:23 PM PDT 24
Peak memory 201148 kb
Host smart-1e0a090c-029a-4178-8464-4d3eef46bd16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616164738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3616164738
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1899722155
Short name T742
Test name
Test status
Simulation time 164680133540 ps
CPU time 178.14 seconds
Started Jul 28 06:48:46 PM PDT 24
Finished Jul 28 06:51:44 PM PDT 24
Peak memory 201120 kb
Host smart-48c63b14-0804-40cd-b7ef-af1c920104bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899722155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1899722155
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1380835766
Short name T494
Test name
Test status
Simulation time 490580638603 ps
CPU time 1120.49 seconds
Started Jul 28 06:48:48 PM PDT 24
Finished Jul 28 07:07:29 PM PDT 24
Peak memory 201164 kb
Host smart-9022d23e-64a3-4915-a841-acfff51f0195
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380835766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1380835766
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3552629562
Short name T298
Test name
Test status
Simulation time 185203967998 ps
CPU time 412.45 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 06:55:44 PM PDT 24
Peak memory 201244 kb
Host smart-f4f6b6d6-ee0b-49da-8754-a0f888eb2aeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552629562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3552629562
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.246660627
Short name T81
Test name
Test status
Simulation time 389528276516 ps
CPU time 860.61 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 07:03:12 PM PDT 24
Peak memory 201160 kb
Host smart-f8a0532f-56c0-49d1-a579-f5b65055d888
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246660627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.246660627
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1441449064
Short name T633
Test name
Test status
Simulation time 93616712079 ps
CPU time 512.42 seconds
Started Jul 28 06:48:50 PM PDT 24
Finished Jul 28 06:57:23 PM PDT 24
Peak memory 201600 kb
Host smart-53d54e52-848d-41ef-aab4-e2fdd5a274cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441449064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1441449064
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3354679483
Short name T564
Test name
Test status
Simulation time 44898374989 ps
CPU time 21.78 seconds
Started Jul 28 06:48:51 PM PDT 24
Finished Jul 28 06:49:12 PM PDT 24
Peak memory 201016 kb
Host smart-027f6351-8e1a-4cdf-8534-919b5c569b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354679483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3354679483
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.600608314
Short name T429
Test name
Test status
Simulation time 3112444100 ps
CPU time 3.09 seconds
Started Jul 28 06:48:50 PM PDT 24
Finished Jul 28 06:48:54 PM PDT 24
Peak memory 200968 kb
Host smart-4b8a5921-dd8c-4f12-88a5-051114d4bfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600608314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.600608314
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.180979526
Short name T471
Test name
Test status
Simulation time 5935725140 ps
CPU time 8.49 seconds
Started Jul 28 06:48:45 PM PDT 24
Finished Jul 28 06:48:54 PM PDT 24
Peak memory 201080 kb
Host smart-39561237-12f9-40cb-93de-8f084c0ed1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180979526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.180979526
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4239312687
Short name T70
Test name
Test status
Simulation time 110767286101 ps
CPU time 63.21 seconds
Started Jul 28 06:48:50 PM PDT 24
Finished Jul 28 06:49:54 PM PDT 24
Peak memory 209936 kb
Host smart-a7749cba-10e7-4302-aeb5-59a5273d08b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239312687 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.4239312687
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3995870974
Short name T719
Test name
Test status
Simulation time 523276549 ps
CPU time 0.93 seconds
Started Jul 28 06:49:04 PM PDT 24
Finished Jul 28 06:49:05 PM PDT 24
Peak memory 200964 kb
Host smart-952b3cc3-754f-4fb8-ba7e-312d15c69774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995870974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3995870974
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3134264860
Short name T481
Test name
Test status
Simulation time 181616823542 ps
CPU time 87.85 seconds
Started Jul 28 06:48:59 PM PDT 24
Finished Jul 28 06:50:27 PM PDT 24
Peak memory 201168 kb
Host smart-b2bfe6c7-2644-4d32-8d22-016f006b5c25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134264860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3134264860
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3033784128
Short name T243
Test name
Test status
Simulation time 171287466796 ps
CPU time 399.96 seconds
Started Jul 28 06:48:59 PM PDT 24
Finished Jul 28 06:55:39 PM PDT 24
Peak memory 201196 kb
Host smart-95638704-c531-438f-91e8-63ce97b1d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033784128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3033784128
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2863574170
Short name T305
Test name
Test status
Simulation time 163016923604 ps
CPU time 402.97 seconds
Started Jul 28 06:48:54 PM PDT 24
Finished Jul 28 06:55:37 PM PDT 24
Peak memory 201188 kb
Host smart-8b643490-4e4a-4ac9-a272-5656dd43b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863574170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2863574170
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3260188477
Short name T72
Test name
Test status
Simulation time 326948927463 ps
CPU time 189.42 seconds
Started Jul 28 06:48:59 PM PDT 24
Finished Jul 28 06:52:08 PM PDT 24
Peak memory 201236 kb
Host smart-8726802c-c99c-4db6-84a6-33a933313b59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260188477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3260188477
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1794774891
Short name T443
Test name
Test status
Simulation time 487096823180 ps
CPU time 299.74 seconds
Started Jul 28 06:48:55 PM PDT 24
Finished Jul 28 06:53:55 PM PDT 24
Peak memory 201188 kb
Host smart-361a3ca8-7bd3-4547-802a-0ed3fef4527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794774891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1794774891
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2474928762
Short name T380
Test name
Test status
Simulation time 328190322022 ps
CPU time 687.62 seconds
Started Jul 28 06:48:54 PM PDT 24
Finished Jul 28 07:00:22 PM PDT 24
Peak memory 201152 kb
Host smart-2e74e04d-a1e8-472f-b1af-d03b6cd4bb40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474928762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2474928762
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2939300982
Short name T557
Test name
Test status
Simulation time 547172382248 ps
CPU time 1069.88 seconds
Started Jul 28 06:49:00 PM PDT 24
Finished Jul 28 07:06:50 PM PDT 24
Peak memory 201204 kb
Host smart-db644378-4242-4663-ae44-922cf8d2085a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939300982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2939300982
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2824144064
Short name T794
Test name
Test status
Simulation time 613185188511 ps
CPU time 354.02 seconds
Started Jul 28 06:48:59 PM PDT 24
Finished Jul 28 06:54:53 PM PDT 24
Peak memory 201096 kb
Host smart-f6eb22b3-e156-4248-8878-4a11f3eb1b3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824144064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2824144064
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3662168084
Short name T629
Test name
Test status
Simulation time 109783988731 ps
CPU time 380.57 seconds
Started Jul 28 06:48:59 PM PDT 24
Finished Jul 28 06:55:19 PM PDT 24
Peak memory 201640 kb
Host smart-9e2a3a2d-655e-47a0-b9f5-766edad49888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662168084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3662168084
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.945831816
Short name T442
Test name
Test status
Simulation time 27103652920 ps
CPU time 13.99 seconds
Started Jul 28 06:49:01 PM PDT 24
Finished Jul 28 06:49:15 PM PDT 24
Peak memory 201020 kb
Host smart-30ffe480-a809-4c8a-a061-540476c8bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945831816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.945831816
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2512327603
Short name T413
Test name
Test status
Simulation time 4619080455 ps
CPU time 11.3 seconds
Started Jul 28 06:49:00 PM PDT 24
Finished Jul 28 06:49:11 PM PDT 24
Peak memory 200992 kb
Host smart-009a7c46-d937-481e-9b03-5e976a809a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512327603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2512327603
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3388941076
Short name T601
Test name
Test status
Simulation time 6025774460 ps
CPU time 3.62 seconds
Started Jul 28 06:48:55 PM PDT 24
Finished Jul 28 06:48:58 PM PDT 24
Peak memory 201020 kb
Host smart-e02403ff-51db-4bb3-b73d-aae103a809d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388941076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3388941076
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3650137349
Short name T292
Test name
Test status
Simulation time 174619898512 ps
CPU time 111.08 seconds
Started Jul 28 06:49:07 PM PDT 24
Finished Jul 28 06:50:58 PM PDT 24
Peak memory 201160 kb
Host smart-69f96c6c-c219-4a97-a219-d14ed1dc956c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650137349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3650137349
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2165474258
Short name T354
Test name
Test status
Simulation time 231639128400 ps
CPU time 241.38 seconds
Started Jul 28 06:49:01 PM PDT 24
Finished Jul 28 06:53:03 PM PDT 24
Peak memory 210008 kb
Host smart-df32c2ae-3fd9-4a94-bacf-e4ef60519eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165474258 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2165474258
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3803387051
Short name T760
Test name
Test status
Simulation time 450766062 ps
CPU time 0.85 seconds
Started Jul 28 06:49:14 PM PDT 24
Finished Jul 28 06:49:15 PM PDT 24
Peak memory 200932 kb
Host smart-0046273d-8392-4881-b987-f4516cb499a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803387051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3803387051
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3289329018
Short name T272
Test name
Test status
Simulation time 166239082288 ps
CPU time 363.38 seconds
Started Jul 28 06:49:06 PM PDT 24
Finished Jul 28 06:55:09 PM PDT 24
Peak memory 201196 kb
Host smart-e50dae9c-7e79-438b-859d-7208a9dc5a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289329018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3289329018
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1555007788
Short name T378
Test name
Test status
Simulation time 325508179484 ps
CPU time 786.58 seconds
Started Jul 28 06:49:03 PM PDT 24
Finished Jul 28 07:02:10 PM PDT 24
Peak memory 201076 kb
Host smart-48bc83bb-73a7-4219-8c0f-d89ad3858deb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555007788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1555007788
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4083653102
Short name T352
Test name
Test status
Simulation time 334359274187 ps
CPU time 52.79 seconds
Started Jul 28 06:49:04 PM PDT 24
Finished Jul 28 06:49:57 PM PDT 24
Peak memory 201128 kb
Host smart-532b8328-2fab-4209-824a-ecc6de71e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083653102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4083653102
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.992570789
Short name T597
Test name
Test status
Simulation time 490487264444 ps
CPU time 148.29 seconds
Started Jul 28 06:49:04 PM PDT 24
Finished Jul 28 06:51:32 PM PDT 24
Peak memory 201144 kb
Host smart-2f4cf2ff-b120-4162-9ab8-56ceaab8b348
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=992570789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.992570789
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4070958506
Short name T685
Test name
Test status
Simulation time 186322243717 ps
CPU time 210.66 seconds
Started Jul 28 06:49:06 PM PDT 24
Finished Jul 28 06:52:36 PM PDT 24
Peak memory 201152 kb
Host smart-5a3b9d1a-8c44-4b54-9b4d-bb818627f74c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070958506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4070958506
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.20584962
Short name T701
Test name
Test status
Simulation time 194416917639 ps
CPU time 429.77 seconds
Started Jul 28 06:49:06 PM PDT 24
Finished Jul 28 06:56:16 PM PDT 24
Peak memory 201176 kb
Host smart-f41ed9e7-2dd3-40a8-817c-9b92140419ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.20584962
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.100845498
Short name T73
Test name
Test status
Simulation time 85911595567 ps
CPU time 309.06 seconds
Started Jul 28 06:49:09 PM PDT 24
Finished Jul 28 06:54:18 PM PDT 24
Peak memory 201812 kb
Host smart-f8736f2b-e5e7-4a7c-bf84-4c9fb0ac7f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100845498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.100845498
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.933196067
Short name T97
Test name
Test status
Simulation time 30025576234 ps
CPU time 33.14 seconds
Started Jul 28 06:49:09 PM PDT 24
Finished Jul 28 06:49:42 PM PDT 24
Peak memory 201020 kb
Host smart-3afa2f20-e802-43af-a102-dad3158211ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933196067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.933196067
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2203578267
Short name T651
Test name
Test status
Simulation time 4324476690 ps
CPU time 1.4 seconds
Started Jul 28 06:49:09 PM PDT 24
Finished Jul 28 06:49:10 PM PDT 24
Peak memory 200948 kb
Host smart-3cc2972e-7b7c-47c5-b62e-61aaf3253f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203578267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2203578267
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2458943391
Short name T204
Test name
Test status
Simulation time 6169986206 ps
CPU time 13.96 seconds
Started Jul 28 06:49:06 PM PDT 24
Finished Jul 28 06:49:20 PM PDT 24
Peak memory 201244 kb
Host smart-88231f29-39ee-450e-bca1-31d4b9d4b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458943391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2458943391
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.747284814
Short name T34
Test name
Test status
Simulation time 66723165981 ps
CPU time 173.28 seconds
Started Jul 28 06:49:12 PM PDT 24
Finished Jul 28 06:52:06 PM PDT 24
Peak memory 209896 kb
Host smart-c4cfcb6c-abf7-4068-8c5b-2ed7d9c7af4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747284814 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.747284814
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.230579517
Short name T62
Test name
Test status
Simulation time 453887133 ps
CPU time 0.91 seconds
Started Jul 28 06:49:32 PM PDT 24
Finished Jul 28 06:49:33 PM PDT 24
Peak memory 200920 kb
Host smart-e72c906e-d046-4651-b926-b570fd07396b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230579517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.230579517
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1882697705
Short name T345
Test name
Test status
Simulation time 176016605221 ps
CPU time 41.4 seconds
Started Jul 28 06:49:29 PM PDT 24
Finished Jul 28 06:50:10 PM PDT 24
Peak memory 201184 kb
Host smart-fbe009c3-3474-4c69-8590-e203d26b2d7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882697705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1882697705
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1833206471
Short name T264
Test name
Test status
Simulation time 251137402553 ps
CPU time 157.49 seconds
Started Jul 28 06:49:27 PM PDT 24
Finished Jul 28 06:52:04 PM PDT 24
Peak memory 201104 kb
Host smart-124a4471-61c4-46c8-8aa6-10200c10ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833206471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1833206471
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4235974282
Short name T174
Test name
Test status
Simulation time 496605447820 ps
CPU time 551.94 seconds
Started Jul 28 06:49:23 PM PDT 24
Finished Jul 28 06:58:35 PM PDT 24
Peak memory 201156 kb
Host smart-661b4fb0-3e57-426b-984b-c5719f18c7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235974282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4235974282
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3253762053
Short name T371
Test name
Test status
Simulation time 166102608592 ps
CPU time 399.84 seconds
Started Jul 28 06:49:23 PM PDT 24
Finished Jul 28 06:56:03 PM PDT 24
Peak memory 201196 kb
Host smart-c2e9072d-0d26-40f6-86a2-a0b5b64f2b78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253762053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3253762053
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.32012380
Short name T661
Test name
Test status
Simulation time 168912165900 ps
CPU time 365.59 seconds
Started Jul 28 06:49:19 PM PDT 24
Finished Jul 28 06:55:24 PM PDT 24
Peak memory 201224 kb
Host smart-14f631e2-f32f-4660-b1c9-03eab540063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32012380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.32012380
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2535429318
Short name T596
Test name
Test status
Simulation time 486188596738 ps
CPU time 188.16 seconds
Started Jul 28 06:49:23 PM PDT 24
Finished Jul 28 06:52:31 PM PDT 24
Peak memory 201172 kb
Host smart-dbe4fb0c-c7f5-4773-92dd-c820c1d6eaf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535429318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2535429318
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.712736026
Short name T214
Test name
Test status
Simulation time 365569367123 ps
CPU time 204.25 seconds
Started Jul 28 06:49:22 PM PDT 24
Finished Jul 28 06:52:47 PM PDT 24
Peak memory 201224 kb
Host smart-cab51116-e73f-4004-a5de-3e5f1989dd9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712736026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.712736026
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3187612665
Short name T136
Test name
Test status
Simulation time 201306721313 ps
CPU time 61.77 seconds
Started Jul 28 06:49:25 PM PDT 24
Finished Jul 28 06:50:27 PM PDT 24
Peak memory 201224 kb
Host smart-725ee643-918c-4a18-ba21-9940d854baed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187612665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3187612665
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3159931978
Short name T26
Test name
Test status
Simulation time 115480913305 ps
CPU time 478.36 seconds
Started Jul 28 06:49:29 PM PDT 24
Finished Jul 28 06:57:27 PM PDT 24
Peak memory 201568 kb
Host smart-c6a20cf6-e0ef-4707-acd3-e26637081b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159931978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3159931978
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4131527937
Short name T205
Test name
Test status
Simulation time 29415109094 ps
CPU time 51 seconds
Started Jul 28 06:49:27 PM PDT 24
Finished Jul 28 06:50:18 PM PDT 24
Peak memory 201012 kb
Host smart-ef2911a9-efca-4c2f-af62-839b77e6ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131527937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4131527937
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3141538412
Short name T581
Test name
Test status
Simulation time 4803993230 ps
CPU time 3.37 seconds
Started Jul 28 06:49:29 PM PDT 24
Finished Jul 28 06:49:32 PM PDT 24
Peak memory 201028 kb
Host smart-7ece5da3-9231-453a-a612-2fe790cbce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141538412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3141538412
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.539923920
Short name T727
Test name
Test status
Simulation time 5863975557 ps
CPU time 14.95 seconds
Started Jul 28 06:49:18 PM PDT 24
Finished Jul 28 06:49:33 PM PDT 24
Peak memory 201052 kb
Host smart-5444b062-8f2a-4ede-b193-d271100368be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539923920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.539923920
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1621570605
Short name T636
Test name
Test status
Simulation time 120175354842 ps
CPU time 136.88 seconds
Started Jul 28 06:49:33 PM PDT 24
Finished Jul 28 06:51:50 PM PDT 24
Peak memory 211096 kb
Host smart-774c08a2-be35-4444-be98-620482840610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621570605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1621570605
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1621737601
Short name T659
Test name
Test status
Simulation time 547743997 ps
CPU time 0.75 seconds
Started Jul 28 06:49:42 PM PDT 24
Finished Jul 28 06:49:43 PM PDT 24
Peak memory 200972 kb
Host smart-9972d068-3de4-4ac6-8e21-508fa442893f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621737601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1621737601
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2215716981
Short name T548
Test name
Test status
Simulation time 188690813960 ps
CPU time 411.6 seconds
Started Jul 28 06:49:36 PM PDT 24
Finished Jul 28 06:56:28 PM PDT 24
Peak memory 201188 kb
Host smart-458593df-86e9-461d-b377-d9ae237ef16d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215716981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2215716981
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2763669085
Short name T725
Test name
Test status
Simulation time 160116622604 ps
CPU time 44.6 seconds
Started Jul 28 06:49:37 PM PDT 24
Finished Jul 28 06:50:22 PM PDT 24
Peak memory 201156 kb
Host smart-5cb9cd14-d936-4bcf-96c2-8c64f86093c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763669085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2763669085
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.68064891
Short name T71
Test name
Test status
Simulation time 490879092472 ps
CPU time 1056.52 seconds
Started Jul 28 06:49:33 PM PDT 24
Finished Jul 28 07:07:09 PM PDT 24
Peak memory 201152 kb
Host smart-fbfed5ba-79c9-482a-890c-7942c1f2e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68064891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.68064891
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3070322913
Short name T620
Test name
Test status
Simulation time 166903191674 ps
CPU time 369.37 seconds
Started Jul 28 06:49:36 PM PDT 24
Finished Jul 28 06:55:46 PM PDT 24
Peak memory 201392 kb
Host smart-9a78e68d-b1a1-43ce-a709-dff4275c40f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070322913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3070322913
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.403341779
Short name T175
Test name
Test status
Simulation time 500734385432 ps
CPU time 1070.17 seconds
Started Jul 28 06:49:32 PM PDT 24
Finished Jul 28 07:07:22 PM PDT 24
Peak memory 201232 kb
Host smart-2e0828ad-8cc6-4913-b52a-ee109bdf2891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403341779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.403341779
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2756245913
Short name T404
Test name
Test status
Simulation time 317999592293 ps
CPU time 530.8 seconds
Started Jul 28 06:49:32 PM PDT 24
Finished Jul 28 06:58:23 PM PDT 24
Peak memory 201156 kb
Host smart-d2c570ea-46d3-4089-b5f4-2b61459e0af4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756245913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2756245913
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3706366772
Short name T610
Test name
Test status
Simulation time 398212491128 ps
CPU time 939.58 seconds
Started Jul 28 06:49:37 PM PDT 24
Finished Jul 28 07:05:17 PM PDT 24
Peak memory 201200 kb
Host smart-af9ddd0d-c103-4342-b678-060ad6e48e61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706366772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3706366772
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.782149037
Short name T507
Test name
Test status
Simulation time 196985230580 ps
CPU time 412.65 seconds
Started Jul 28 06:49:36 PM PDT 24
Finished Jul 28 06:56:29 PM PDT 24
Peak memory 201148 kb
Host smart-979b7019-2fe8-42d8-871b-6a3624a9df81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782149037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.782149037
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2187513118
Short name T738
Test name
Test status
Simulation time 93642676396 ps
CPU time 515.49 seconds
Started Jul 28 06:49:42 PM PDT 24
Finished Jul 28 06:58:17 PM PDT 24
Peak memory 201608 kb
Host smart-bc95c74b-9617-4428-a015-dd30bd34bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187513118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2187513118
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2627794155
Short name T619
Test name
Test status
Simulation time 24245647303 ps
CPU time 27.98 seconds
Started Jul 28 06:49:37 PM PDT 24
Finished Jul 28 06:50:05 PM PDT 24
Peak memory 201008 kb
Host smart-1a6834e6-7b98-48de-8d0c-343bba1de220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627794155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2627794155
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4082240350
Short name T513
Test name
Test status
Simulation time 4975686383 ps
CPU time 10.44 seconds
Started Jul 28 06:49:38 PM PDT 24
Finished Jul 28 06:49:48 PM PDT 24
Peak memory 201036 kb
Host smart-38611db3-4f39-453c-8073-16ce9e79aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082240350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4082240350
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1960269116
Short name T416
Test name
Test status
Simulation time 5692777658 ps
CPU time 2.87 seconds
Started Jul 28 06:49:33 PM PDT 24
Finished Jul 28 06:49:36 PM PDT 24
Peak memory 201064 kb
Host smart-1a43f7e9-64f8-4b1c-be1c-ca20340f2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960269116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1960269116
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3517429836
Short name T231
Test name
Test status
Simulation time 123766241556 ps
CPU time 375.88 seconds
Started Jul 28 06:49:42 PM PDT 24
Finished Jul 28 06:55:58 PM PDT 24
Peak memory 201712 kb
Host smart-5775b1d3-49ee-4d01-a889-3fecfac98037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517429836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3517429836
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1901863864
Short name T27
Test name
Test status
Simulation time 7805122122 ps
CPU time 18.12 seconds
Started Jul 28 06:49:43 PM PDT 24
Finished Jul 28 06:50:01 PM PDT 24
Peak memory 209372 kb
Host smart-8c1a1b4a-0088-4a84-bca5-2780298dd54b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901863864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1901863864
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2904304743
Short name T437
Test name
Test status
Simulation time 289809612 ps
CPU time 1.28 seconds
Started Jul 28 06:50:01 PM PDT 24
Finished Jul 28 06:50:02 PM PDT 24
Peak memory 200948 kb
Host smart-8cbac528-69fa-48fa-b7e1-4a0987445ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904304743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2904304743
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2855659463
Short name T642
Test name
Test status
Simulation time 168403291427 ps
CPU time 345.75 seconds
Started Jul 28 06:49:51 PM PDT 24
Finished Jul 28 06:55:37 PM PDT 24
Peak memory 201284 kb
Host smart-8738d12e-7cdc-4a1e-bda4-3c6cd771d6f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855659463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2855659463
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1160921930
Short name T293
Test name
Test status
Simulation time 162395430666 ps
CPU time 394.99 seconds
Started Jul 28 06:49:51 PM PDT 24
Finished Jul 28 06:56:26 PM PDT 24
Peak memory 201160 kb
Host smart-f63b0be4-0e9d-4182-9ddd-0d8b0f32d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160921930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1160921930
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2191768713
Short name T728
Test name
Test status
Simulation time 163341988944 ps
CPU time 199.59 seconds
Started Jul 28 06:49:46 PM PDT 24
Finished Jul 28 06:53:06 PM PDT 24
Peak memory 201188 kb
Host smart-d5108567-f154-4958-8ea0-eab5d26f186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191768713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2191768713
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2880253356
Short name T486
Test name
Test status
Simulation time 491984471356 ps
CPU time 130.45 seconds
Started Jul 28 06:49:53 PM PDT 24
Finished Jul 28 06:52:03 PM PDT 24
Peak memory 201228 kb
Host smart-31eaa52c-0742-488a-b135-82eb4e45c60d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880253356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2880253356
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3068726888
Short name T172
Test name
Test status
Simulation time 162524235206 ps
CPU time 362.57 seconds
Started Jul 28 06:49:47 PM PDT 24
Finished Jul 28 06:55:49 PM PDT 24
Peak memory 201184 kb
Host smart-05475408-7168-46e1-a62a-10df089700e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068726888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3068726888
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3588883650
Short name T630
Test name
Test status
Simulation time 159422420361 ps
CPU time 47.33 seconds
Started Jul 28 06:49:46 PM PDT 24
Finished Jul 28 06:50:34 PM PDT 24
Peak memory 201196 kb
Host smart-8c799540-abab-4cef-9929-018eb87faaf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588883650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3588883650
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1964685131
Short name T511
Test name
Test status
Simulation time 396475514356 ps
CPU time 451.46 seconds
Started Jul 28 06:49:51 PM PDT 24
Finished Jul 28 06:57:22 PM PDT 24
Peak memory 201160 kb
Host smart-1f1b5de1-eb63-4bd3-bbd9-a60c13e37dbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964685131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1964685131
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2512676874
Short name T232
Test name
Test status
Simulation time 82640442846 ps
CPU time 273.6 seconds
Started Jul 28 06:49:56 PM PDT 24
Finished Jul 28 06:54:30 PM PDT 24
Peak memory 201684 kb
Host smart-4319a3df-4cf4-4e13-9e6e-8b6080ec19e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512676874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2512676874
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.697771424
Short name T652
Test name
Test status
Simulation time 42036683474 ps
CPU time 97.51 seconds
Started Jul 28 06:49:56 PM PDT 24
Finished Jul 28 06:51:33 PM PDT 24
Peak memory 201036 kb
Host smart-2859f67e-c7a3-4b06-8cd1-dfe36961e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697771424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.697771424
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2207116333
Short name T741
Test name
Test status
Simulation time 4272510174 ps
CPU time 3.13 seconds
Started Jul 28 06:49:57 PM PDT 24
Finished Jul 28 06:50:00 PM PDT 24
Peak memory 200984 kb
Host smart-ecc74f87-c8a5-4328-94a8-f7ae8fdaf517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207116333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2207116333
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4109034631
Short name T479
Test name
Test status
Simulation time 5661862141 ps
CPU time 14.08 seconds
Started Jul 28 06:49:47 PM PDT 24
Finished Jul 28 06:50:01 PM PDT 24
Peak memory 201000 kb
Host smart-d74c2b5b-1e10-45bb-8bbd-6bbc102d386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109034631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4109034631
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1264311017
Short name T604
Test name
Test status
Simulation time 174733057857 ps
CPU time 403.87 seconds
Started Jul 28 06:50:01 PM PDT 24
Finished Jul 28 06:56:45 PM PDT 24
Peak memory 201144 kb
Host smart-c8615a2f-5268-4577-8730-49cf6fedf4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264311017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1264311017
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3213300107
Short name T609
Test name
Test status
Simulation time 500971785356 ps
CPU time 577.59 seconds
Started Jul 28 06:49:57 PM PDT 24
Finished Jul 28 06:59:35 PM PDT 24
Peak memory 210364 kb
Host smart-f17e5c83-9e94-4270-ac47-291c2d09dba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213300107 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3213300107
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3411744913
Short name T730
Test name
Test status
Simulation time 480524331 ps
CPU time 0.79 seconds
Started Jul 28 06:50:11 PM PDT 24
Finished Jul 28 06:50:12 PM PDT 24
Peak memory 200988 kb
Host smart-86ddc18e-04e3-40a3-930b-3c882fbb21c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411744913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3411744913
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.889183045
Short name T182
Test name
Test status
Simulation time 350033932034 ps
CPU time 48.7 seconds
Started Jul 28 06:50:05 PM PDT 24
Finished Jul 28 06:50:54 PM PDT 24
Peak memory 201160 kb
Host smart-f47f9b30-b4d3-4964-b445-cd2bc7e35d83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889183045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.889183045
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4017900992
Short name T154
Test name
Test status
Simulation time 168595659049 ps
CPU time 387.74 seconds
Started Jul 28 06:50:06 PM PDT 24
Finished Jul 28 06:56:34 PM PDT 24
Peak memory 201260 kb
Host smart-82d8f3f5-be05-4584-b05d-294542be0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017900992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4017900992
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1629713600
Short name T419
Test name
Test status
Simulation time 162671933866 ps
CPU time 181.06 seconds
Started Jul 28 06:50:07 PM PDT 24
Finished Jul 28 06:53:08 PM PDT 24
Peak memory 201188 kb
Host smart-e7799fcc-bd4e-406b-b6d5-7aa854edd8b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629713600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1629713600
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1987123648
Short name T239
Test name
Test status
Simulation time 333113819373 ps
CPU time 365.38 seconds
Started Jul 28 06:50:00 PM PDT 24
Finished Jul 28 06:56:06 PM PDT 24
Peak memory 201124 kb
Host smart-daf401f1-b9fa-4221-be12-0aeff7e30e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987123648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1987123648
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1100713495
Short name T622
Test name
Test status
Simulation time 325785577026 ps
CPU time 746.17 seconds
Started Jul 28 06:50:00 PM PDT 24
Finished Jul 28 07:02:27 PM PDT 24
Peak memory 201204 kb
Host smart-d4637991-95c9-4fcb-a60c-913a24a46b0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100713495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1100713495
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2006612494
Short name T255
Test name
Test status
Simulation time 503177608949 ps
CPU time 543.74 seconds
Started Jul 28 06:50:08 PM PDT 24
Finished Jul 28 06:59:12 PM PDT 24
Peak memory 201228 kb
Host smart-7a0559d7-d1d3-477c-97f0-e7c03dc356af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006612494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2006612494
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3590255349
Short name T608
Test name
Test status
Simulation time 211913445787 ps
CPU time 248.33 seconds
Started Jul 28 06:50:06 PM PDT 24
Finished Jul 28 06:54:15 PM PDT 24
Peak memory 201108 kb
Host smart-f324d7e4-af00-4932-ba11-6e6abd9beb39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590255349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3590255349
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.682441245
Short name T563
Test name
Test status
Simulation time 66833699590 ps
CPU time 237.89 seconds
Started Jul 28 06:50:13 PM PDT 24
Finished Jul 28 06:54:11 PM PDT 24
Peak memory 201660 kb
Host smart-68648790-df7d-48c8-b005-3f3ca1af2b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682441245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.682441245
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3286024744
Short name T453
Test name
Test status
Simulation time 42310855729 ps
CPU time 24.91 seconds
Started Jul 28 06:50:13 PM PDT 24
Finished Jul 28 06:50:38 PM PDT 24
Peak memory 201008 kb
Host smart-041024c6-aa40-47d8-ba0b-0bf6be9e0980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286024744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3286024744
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3597709472
Short name T469
Test name
Test status
Simulation time 3193411060 ps
CPU time 6.23 seconds
Started Jul 28 06:50:08 PM PDT 24
Finished Jul 28 06:50:14 PM PDT 24
Peak memory 200984 kb
Host smart-6a9b63a2-b2ae-4f33-830a-fb38ef233775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597709472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3597709472
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3379396028
Short name T455
Test name
Test status
Simulation time 5654409950 ps
CPU time 2.04 seconds
Started Jul 28 06:50:01 PM PDT 24
Finished Jul 28 06:50:03 PM PDT 24
Peak memory 201016 kb
Host smart-2fb7e114-7b44-4dca-9044-9621c3300165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379396028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3379396028
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3886828260
Short name T300
Test name
Test status
Simulation time 282537775688 ps
CPU time 631.92 seconds
Started Jul 28 06:50:11 PM PDT 24
Finished Jul 28 07:00:44 PM PDT 24
Peak memory 201172 kb
Host smart-146360d7-9b0d-4088-88b4-e6795e14e3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886828260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3886828260
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1152056840
Short name T748
Test name
Test status
Simulation time 321960745 ps
CPU time 1.01 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:50:35 PM PDT 24
Peak memory 200916 kb
Host smart-6211b1a8-9863-4bad-90fe-d5fbb03b5a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152056840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1152056840
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1887535669
Short name T254
Test name
Test status
Simulation time 498623720463 ps
CPU time 732.25 seconds
Started Jul 28 06:50:27 PM PDT 24
Finished Jul 28 07:02:40 PM PDT 24
Peak memory 201148 kb
Host smart-9b922d8e-d175-4fef-be3b-4fb61969d35b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887535669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1887535669
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1290305673
Short name T210
Test name
Test status
Simulation time 544092939179 ps
CPU time 296.33 seconds
Started Jul 28 06:50:28 PM PDT 24
Finished Jul 28 06:55:24 PM PDT 24
Peak memory 201224 kb
Host smart-bc478e4c-81e5-4e30-9cea-48476a5adcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290305673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1290305673
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.576036050
Short name T348
Test name
Test status
Simulation time 159921447424 ps
CPU time 371.87 seconds
Started Jul 28 06:50:16 PM PDT 24
Finished Jul 28 06:56:28 PM PDT 24
Peak memory 201116 kb
Host smart-d0d6485f-b211-4532-881f-d5dbadb8bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576036050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.576036050
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1041653039
Short name T402
Test name
Test status
Simulation time 329396482034 ps
CPU time 757.36 seconds
Started Jul 28 06:50:14 PM PDT 24
Finished Jul 28 07:02:52 PM PDT 24
Peak memory 201164 kb
Host smart-0b4e7c70-1a03-4638-bbb2-92a2535b7370
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041653039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1041653039
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.681272168
Short name T128
Test name
Test status
Simulation time 488101647894 ps
CPU time 950.43 seconds
Started Jul 28 06:50:11 PM PDT 24
Finished Jul 28 07:06:02 PM PDT 24
Peak memory 201180 kb
Host smart-fe6ce918-97c2-491d-9325-d9ab34e96a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681272168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.681272168
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2068698410
Short name T484
Test name
Test status
Simulation time 323943072537 ps
CPU time 182.27 seconds
Started Jul 28 06:50:18 PM PDT 24
Finished Jul 28 06:53:20 PM PDT 24
Peak memory 201164 kb
Host smart-ee4afcdf-4b73-4abc-a40d-64bbc99aac22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068698410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2068698410
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1475812246
Short name T684
Test name
Test status
Simulation time 441949206818 ps
CPU time 1061.59 seconds
Started Jul 28 06:50:17 PM PDT 24
Finished Jul 28 07:07:59 PM PDT 24
Peak memory 201120 kb
Host smart-60ee09aa-4161-4afe-8217-e1dda5e8ca83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475812246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1475812246
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3885228437
Short name T427
Test name
Test status
Simulation time 419828516630 ps
CPU time 527.78 seconds
Started Jul 28 06:50:22 PM PDT 24
Finished Jul 28 06:59:10 PM PDT 24
Peak memory 201144 kb
Host smart-0f35fda9-1950-4ed6-ab11-a2bd2fbeb910
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885228437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3885228437
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2533643009
Short name T743
Test name
Test status
Simulation time 95983504106 ps
CPU time 550.07 seconds
Started Jul 28 06:50:29 PM PDT 24
Finished Jul 28 06:59:39 PM PDT 24
Peak memory 201616 kb
Host smart-1e7f392e-76f3-42dd-86d7-34acb2dee3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533643009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2533643009
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4274733265
Short name T517
Test name
Test status
Simulation time 27237235982 ps
CPU time 64.36 seconds
Started Jul 28 06:50:31 PM PDT 24
Finished Jul 28 06:51:35 PM PDT 24
Peak memory 200980 kb
Host smart-04979133-0c64-418f-9981-2a12a1d77b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274733265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4274733265
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2684623500
Short name T395
Test name
Test status
Simulation time 3262688249 ps
CPU time 2.41 seconds
Started Jul 28 06:50:25 PM PDT 24
Finished Jul 28 06:50:28 PM PDT 24
Peak memory 201016 kb
Host smart-65934eb5-c59b-44da-a415-cba58626428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684623500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2684623500
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2279244740
Short name T403
Test name
Test status
Simulation time 5745211083 ps
CPU time 14.46 seconds
Started Jul 28 06:50:12 PM PDT 24
Finished Jul 28 06:50:26 PM PDT 24
Peak memory 201004 kb
Host smart-b9b7368b-09dd-46ab-a244-95a571ebb297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279244740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2279244740
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.845566029
Short name T338
Test name
Test status
Simulation time 289367964400 ps
CPU time 510.36 seconds
Started Jul 28 06:50:31 PM PDT 24
Finished Jul 28 06:59:02 PM PDT 24
Peak memory 201596 kb
Host smart-7a64d470-a8b5-4bd7-a0bf-bc9b50d9560b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845566029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
845566029
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1750916783
Short name T720
Test name
Test status
Simulation time 387931557 ps
CPU time 1.51 seconds
Started Jul 28 06:50:39 PM PDT 24
Finished Jul 28 06:50:40 PM PDT 24
Peak memory 200944 kb
Host smart-8a592189-c1e5-46ee-91ed-d3ab2fe0a4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750916783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1750916783
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3633150609
Short name T782
Test name
Test status
Simulation time 180620517889 ps
CPU time 403.24 seconds
Started Jul 28 06:50:36 PM PDT 24
Finished Jul 28 06:57:19 PM PDT 24
Peak memory 201204 kb
Host smart-f9afbaee-12b9-4c05-8943-be2f388f16b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633150609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3633150609
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2898235141
Short name T640
Test name
Test status
Simulation time 319089122322 ps
CPU time 196.36 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:53:50 PM PDT 24
Peak memory 201220 kb
Host smart-8dd61479-d9ca-43ca-9b1c-275d497230c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898235141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2898235141
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3750846611
Short name T778
Test name
Test status
Simulation time 498198901892 ps
CPU time 1162.57 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 07:09:57 PM PDT 24
Peak memory 201164 kb
Host smart-62e281fc-8af8-42ea-af32-b36cb15b2e8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750846611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3750846611
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2325047937
Short name T708
Test name
Test status
Simulation time 328674387302 ps
CPU time 394.67 seconds
Started Jul 28 06:50:35 PM PDT 24
Finished Jul 28 06:57:09 PM PDT 24
Peak memory 201144 kb
Host smart-b92a5db9-ad9e-4817-ade2-8f624b693935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325047937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2325047937
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1483075035
Short name T473
Test name
Test status
Simulation time 168306322413 ps
CPU time 376.79 seconds
Started Jul 28 06:50:33 PM PDT 24
Finished Jul 28 06:56:50 PM PDT 24
Peak memory 201116 kb
Host smart-e9505344-af51-4ac3-a08f-b22e1767b230
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483075035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1483075035
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3127127975
Short name T325
Test name
Test status
Simulation time 541426554127 ps
CPU time 99.67 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:52:14 PM PDT 24
Peak memory 201208 kb
Host smart-3c036467-e04a-4ce0-8371-6e52df5e7269
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127127975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3127127975
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3378692680
Short name T750
Test name
Test status
Simulation time 206765225214 ps
CPU time 468.75 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:58:23 PM PDT 24
Peak memory 201116 kb
Host smart-27a320b1-6da7-4ec2-8104-86eaee24939b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378692680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3378692680
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1991863316
Short name T592
Test name
Test status
Simulation time 128863688256 ps
CPU time 652.78 seconds
Started Jul 28 06:50:36 PM PDT 24
Finished Jul 28 07:01:29 PM PDT 24
Peak memory 201592 kb
Host smart-c20420e3-1ebb-43a9-b1be-1690cf107fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991863316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1991863316
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1549554539
Short name T616
Test name
Test status
Simulation time 24969674460 ps
CPU time 15.67 seconds
Started Jul 28 06:50:33 PM PDT 24
Finished Jul 28 06:50:49 PM PDT 24
Peak memory 201016 kb
Host smart-e0e70afa-5c40-4537-86b8-0e76515e046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549554539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1549554539
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2480776333
Short name T542
Test name
Test status
Simulation time 3780472111 ps
CPU time 2.76 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:50:36 PM PDT 24
Peak memory 201016 kb
Host smart-aa478c3a-6b9a-42e1-873c-272a9c2ee063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480776333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2480776333
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.905020901
Short name T788
Test name
Test status
Simulation time 5781505520 ps
CPU time 2.5 seconds
Started Jul 28 06:50:34 PM PDT 24
Finished Jul 28 06:50:37 PM PDT 24
Peak memory 200996 kb
Host smart-4bf48ede-95bc-4a22-972e-7d4c31e83425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905020901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.905020901
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3802696171
Short name T2
Test name
Test status
Simulation time 203441207525 ps
CPU time 453.76 seconds
Started Jul 28 06:50:39 PM PDT 24
Finished Jul 28 06:58:13 PM PDT 24
Peak memory 201124 kb
Host smart-f516d579-2712-4341-b325-919eccb79c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802696171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3802696171
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1436690964
Short name T91
Test name
Test status
Simulation time 45167511404 ps
CPU time 121.53 seconds
Started Jul 28 06:50:38 PM PDT 24
Finished Jul 28 06:52:40 PM PDT 24
Peak memory 210412 kb
Host smart-ec107ab6-4df8-42b6-8d0a-356313c48781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436690964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1436690964
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3637662861
Short name T498
Test name
Test status
Simulation time 486439677 ps
CPU time 1.66 seconds
Started Jul 28 06:39:58 PM PDT 24
Finished Jul 28 06:40:00 PM PDT 24
Peak memory 200960 kb
Host smart-e6eba268-a837-49bb-9a5d-978378d52d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637662861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3637662861
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3445410482
Short name T308
Test name
Test status
Simulation time 501205802058 ps
CPU time 583.7 seconds
Started Jul 28 06:39:55 PM PDT 24
Finished Jul 28 06:49:39 PM PDT 24
Peak memory 201176 kb
Host smart-fc9587b7-c5d9-416b-9066-c040e7da5b11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445410482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3445410482
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4112636894
Short name T171
Test name
Test status
Simulation time 352379840017 ps
CPU time 81.9 seconds
Started Jul 28 06:39:53 PM PDT 24
Finished Jul 28 06:41:15 PM PDT 24
Peak memory 201168 kb
Host smart-7838e410-c4f6-4625-bd79-5156691a29e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112636894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4112636894
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.776539197
Short name T328
Test name
Test status
Simulation time 324398933973 ps
CPU time 394.52 seconds
Started Jul 28 06:40:00 PM PDT 24
Finished Jul 28 06:46:34 PM PDT 24
Peak memory 201292 kb
Host smart-891c7ac5-a3ec-4962-acf6-876f1835125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776539197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.776539197
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1576596664
Short name T568
Test name
Test status
Simulation time 160979820527 ps
CPU time 362.88 seconds
Started Jul 28 06:39:58 PM PDT 24
Finished Jul 28 06:46:01 PM PDT 24
Peak memory 201148 kb
Host smart-fabe8881-bdf1-461f-8c72-7f1e4aed3c48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576596664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1576596664
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2060722294
Short name T746
Test name
Test status
Simulation time 162390443354 ps
CPU time 354.8 seconds
Started Jul 28 06:39:47 PM PDT 24
Finished Jul 28 06:45:42 PM PDT 24
Peak memory 201152 kb
Host smart-5e15f70f-c9ca-4a3b-a7b1-d8e95b806ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060722294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2060722294
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3924430825
Short name T485
Test name
Test status
Simulation time 162291507436 ps
CPU time 170.1 seconds
Started Jul 28 06:39:49 PM PDT 24
Finished Jul 28 06:42:39 PM PDT 24
Peak memory 201152 kb
Host smart-e9a17fdb-90cb-45bc-a191-22513af32003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924430825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3924430825
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3424688925
Short name T729
Test name
Test status
Simulation time 213069420793 ps
CPU time 35.19 seconds
Started Jul 28 06:39:59 PM PDT 24
Finished Jul 28 06:40:34 PM PDT 24
Peak memory 201224 kb
Host smart-7be69291-19cf-4839-970a-d7df95c238ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424688925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3424688925
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2194443621
Short name T203
Test name
Test status
Simulation time 417718035812 ps
CPU time 247.94 seconds
Started Jul 28 06:40:00 PM PDT 24
Finished Jul 28 06:44:08 PM PDT 24
Peak memory 201192 kb
Host smart-52272f77-193a-4bad-97f1-382cfaacc64f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194443621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2194443621
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3645283680
Short name T718
Test name
Test status
Simulation time 109069463617 ps
CPU time 574.28 seconds
Started Jul 28 06:40:00 PM PDT 24
Finished Jul 28 06:49:34 PM PDT 24
Peak memory 201628 kb
Host smart-7c3a8f97-b89e-4be5-9d74-5f4556c5dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645283680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3645283680
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2299773709
Short name T425
Test name
Test status
Simulation time 30917924872 ps
CPU time 16.97 seconds
Started Jul 28 06:40:03 PM PDT 24
Finished Jul 28 06:40:20 PM PDT 24
Peak memory 201044 kb
Host smart-639f0ce6-19c0-46a3-9992-52d692affa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299773709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2299773709
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3782967190
Short name T717
Test name
Test status
Simulation time 3222016344 ps
CPU time 2.6 seconds
Started Jul 28 06:40:00 PM PDT 24
Finished Jul 28 06:40:03 PM PDT 24
Peak memory 201028 kb
Host smart-ede2caad-b61e-4934-a5b9-d354425bb6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782967190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3782967190
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1510058709
Short name T709
Test name
Test status
Simulation time 5771056586 ps
CPU time 13.69 seconds
Started Jul 28 06:39:49 PM PDT 24
Finished Jul 28 06:40:03 PM PDT 24
Peak memory 201000 kb
Host smart-4d4d3fc7-5282-4103-826e-0cd7416b9851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510058709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1510058709
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.712684815
Short name T533
Test name
Test status
Simulation time 499039130353 ps
CPU time 1461.33 seconds
Started Jul 28 06:40:01 PM PDT 24
Finished Jul 28 07:04:23 PM PDT 24
Peak memory 209868 kb
Host smart-5ff30f50-45d1-4872-ae3b-64acc9b74ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712684815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.712684815
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2557364580
Short name T51
Test name
Test status
Simulation time 124702680281 ps
CPU time 156.21 seconds
Started Jul 28 06:39:59 PM PDT 24
Finished Jul 28 06:42:35 PM PDT 24
Peak memory 209500 kb
Host smart-b099dcc3-d067-4d73-a9d6-9f6406c85098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557364580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2557364580
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2185116760
Short name T723
Test name
Test status
Simulation time 327627081 ps
CPU time 0.75 seconds
Started Jul 28 06:40:12 PM PDT 24
Finished Jul 28 06:40:13 PM PDT 24
Peak memory 201016 kb
Host smart-15d44319-a090-4e50-bea4-271d3ffd0fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185116760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2185116760
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2481629026
Short name T253
Test name
Test status
Simulation time 175474767915 ps
CPU time 101.54 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:41:52 PM PDT 24
Peak memory 201104 kb
Host smart-025d7bf8-cc38-4b95-aa4c-77650b713d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481629026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2481629026
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1536575613
Short name T284
Test name
Test status
Simulation time 318696946486 ps
CPU time 687.46 seconds
Started Jul 28 06:39:59 PM PDT 24
Finished Jul 28 06:51:26 PM PDT 24
Peak memory 201184 kb
Host smart-b03973a6-17ee-4e04-978c-14322e74634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536575613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1536575613
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3548612165
Short name T618
Test name
Test status
Simulation time 332104020473 ps
CPU time 695.6 seconds
Started Jul 28 06:40:06 PM PDT 24
Finished Jul 28 06:51:42 PM PDT 24
Peak memory 201112 kb
Host smart-c15a76fc-ccdd-41c2-8360-13d89cb39b3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548612165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3548612165
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3366508362
Short name T248
Test name
Test status
Simulation time 162594845504 ps
CPU time 183.74 seconds
Started Jul 28 06:39:59 PM PDT 24
Finished Jul 28 06:43:03 PM PDT 24
Peak memory 201212 kb
Host smart-2525573a-6c56-4d70-aa27-89bdd5aff995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366508362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3366508362
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.361019910
Short name T464
Test name
Test status
Simulation time 495679812034 ps
CPU time 550.74 seconds
Started Jul 28 06:40:02 PM PDT 24
Finished Jul 28 06:49:13 PM PDT 24
Peak memory 201168 kb
Host smart-d0d8f996-4adc-444b-81b4-088634072259
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=361019910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.361019910
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.989152230
Short name T789
Test name
Test status
Simulation time 610820732483 ps
CPU time 370.98 seconds
Started Jul 28 06:40:08 PM PDT 24
Finished Jul 28 06:46:19 PM PDT 24
Peak memory 201156 kb
Host smart-d2595216-6eef-4462-aa21-21a55a4babd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989152230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.989152230
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.557715337
Short name T565
Test name
Test status
Simulation time 588017240278 ps
CPU time 1292.82 seconds
Started Jul 28 06:40:07 PM PDT 24
Finished Jul 28 07:01:40 PM PDT 24
Peak memory 201164 kb
Host smart-b3d603cb-1df4-4cc6-9d39-fcee39132411
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557715337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.557715337
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.889402785
Short name T222
Test name
Test status
Simulation time 72525084509 ps
CPU time 414.44 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:47:06 PM PDT 24
Peak memory 201644 kb
Host smart-3e8a5fc6-d526-4c8b-9487-87fb152e5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889402785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.889402785
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1115811195
Short name T529
Test name
Test status
Simulation time 26079961335 ps
CPU time 30.23 seconds
Started Jul 28 06:40:12 PM PDT 24
Finished Jul 28 06:40:42 PM PDT 24
Peak memory 201008 kb
Host smart-9fb27214-6963-4d6e-afe9-0ae0b6c0deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115811195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1115811195
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3152900780
Short name T421
Test name
Test status
Simulation time 3396820854 ps
CPU time 2.86 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:40:14 PM PDT 24
Peak memory 201008 kb
Host smart-12b38db0-15b8-461e-9c8f-dcc93ab0d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152900780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3152900780
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2050833809
Short name T532
Test name
Test status
Simulation time 5761669869 ps
CPU time 14.91 seconds
Started Jul 28 06:40:01 PM PDT 24
Finished Jul 28 06:40:16 PM PDT 24
Peak memory 201008 kb
Host smart-f2680c39-fcb3-49fc-bc13-e00878022218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050833809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2050833809
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.850401468
Short name T671
Test name
Test status
Simulation time 429561603 ps
CPU time 0.77 seconds
Started Jul 28 06:40:30 PM PDT 24
Finished Jul 28 06:40:31 PM PDT 24
Peak memory 200952 kb
Host smart-7fb5fa54-36ad-4453-ad41-93717b4e99e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850401468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.850401468
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1342993510
Short name T88
Test name
Test status
Simulation time 487386449899 ps
CPU time 1036.95 seconds
Started Jul 28 06:40:25 PM PDT 24
Finished Jul 28 06:57:42 PM PDT 24
Peak memory 201080 kb
Host smart-690c5afb-5747-4ead-8c40-d96efc5d242d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342993510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1342993510
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1680700224
Short name T296
Test name
Test status
Simulation time 334821602938 ps
CPU time 203.81 seconds
Started Jul 28 06:40:18 PM PDT 24
Finished Jul 28 06:43:42 PM PDT 24
Peak memory 201180 kb
Host smart-74dd4146-d4ed-4af2-bb0d-effb404c4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680700224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1680700224
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2164553343
Short name T733
Test name
Test status
Simulation time 326956172365 ps
CPU time 745.06 seconds
Started Jul 28 06:40:17 PM PDT 24
Finished Jul 28 06:52:42 PM PDT 24
Peak memory 201240 kb
Host smart-b3292f13-f7ff-46b4-a786-bf01f2403cca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164553343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2164553343
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.297601536
Short name T341
Test name
Test status
Simulation time 481122381402 ps
CPU time 1155.4 seconds
Started Jul 28 06:40:17 PM PDT 24
Finished Jul 28 06:59:32 PM PDT 24
Peak memory 201208 kb
Host smart-eea0bf31-0360-4328-91e6-83683b3059b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297601536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.297601536
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.412088356
Short name T447
Test name
Test status
Simulation time 325949864281 ps
CPU time 693.19 seconds
Started Jul 28 06:40:17 PM PDT 24
Finished Jul 28 06:51:51 PM PDT 24
Peak memory 201156 kb
Host smart-185af3bf-034a-4a10-8d7c-3ae3f2086f84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412088356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.412088356
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4043535111
Short name T431
Test name
Test status
Simulation time 211084439748 ps
CPU time 127.74 seconds
Started Jul 28 06:40:19 PM PDT 24
Finished Jul 28 06:42:26 PM PDT 24
Peak memory 201156 kb
Host smart-e2cdaf93-22a8-4610-98fb-8aadd9f48913
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043535111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4043535111
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1518545801
Short name T221
Test name
Test status
Simulation time 135974585806 ps
CPU time 588.44 seconds
Started Jul 28 06:40:24 PM PDT 24
Finished Jul 28 06:50:13 PM PDT 24
Peak memory 201612 kb
Host smart-2ed467e0-e8a7-4223-a532-1a8b8d751ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518545801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1518545801
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.726499468
Short name T549
Test name
Test status
Simulation time 22019767970 ps
CPU time 8.14 seconds
Started Jul 28 06:40:24 PM PDT 24
Finished Jul 28 06:40:33 PM PDT 24
Peak memory 200952 kb
Host smart-61d511a0-786a-4607-ba47-d1a800ac342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726499468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.726499468
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2565153654
Short name T772
Test name
Test status
Simulation time 3021488359 ps
CPU time 7.8 seconds
Started Jul 28 06:40:26 PM PDT 24
Finished Jul 28 06:40:34 PM PDT 24
Peak memory 200992 kb
Host smart-3c474faa-c62a-48b7-9340-f45a5c4717a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565153654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2565153654
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3731274031
Short name T562
Test name
Test status
Simulation time 5940535198 ps
CPU time 7.42 seconds
Started Jul 28 06:40:11 PM PDT 24
Finished Jul 28 06:40:19 PM PDT 24
Peak memory 201040 kb
Host smart-fe5d1042-bf5a-4118-b043-2830176abde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731274031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3731274031
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1641837240
Short name T477
Test name
Test status
Simulation time 76748405421 ps
CPU time 231.45 seconds
Started Jul 28 06:40:30 PM PDT 24
Finished Jul 28 06:44:22 PM PDT 24
Peak memory 201568 kb
Host smart-64f5b63c-d089-4dc7-b7a5-c5ce76e7f079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641837240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1641837240
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3724104198
Short name T233
Test name
Test status
Simulation time 108190681640 ps
CPU time 382.48 seconds
Started Jul 28 06:40:28 PM PDT 24
Finished Jul 28 06:46:50 PM PDT 24
Peak memory 210284 kb
Host smart-8afef2b9-63e6-47fc-ade5-3fc02fce87b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724104198 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3724104198
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2829419047
Short name T502
Test name
Test status
Simulation time 421928785 ps
CPU time 0.82 seconds
Started Jul 28 06:40:49 PM PDT 24
Finished Jul 28 06:40:50 PM PDT 24
Peak memory 201176 kb
Host smart-7bc82922-c2a8-4ef1-a18b-9f744188c9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829419047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2829419047
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2893703126
Short name T299
Test name
Test status
Simulation time 330494331762 ps
CPU time 192.78 seconds
Started Jul 28 06:40:41 PM PDT 24
Finished Jul 28 06:43:54 PM PDT 24
Peak memory 201160 kb
Host smart-ef818c51-fc9a-4214-9ceb-d77c54bd7a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893703126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2893703126
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1730032447
Short name T310
Test name
Test status
Simulation time 491020932069 ps
CPU time 588.36 seconds
Started Jul 28 06:40:41 PM PDT 24
Finished Jul 28 06:50:29 PM PDT 24
Peak memory 201192 kb
Host smart-2e675204-b65a-4674-9a18-b6dce174e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730032447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1730032447
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2891848617
Short name T462
Test name
Test status
Simulation time 489291900299 ps
CPU time 1198.25 seconds
Started Jul 28 06:40:41 PM PDT 24
Finished Jul 28 07:00:39 PM PDT 24
Peak memory 201148 kb
Host smart-3addebd2-6248-4d7c-ae29-88ea15a3427d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891848617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2891848617
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3978711248
Short name T397
Test name
Test status
Simulation time 164278056075 ps
CPU time 342.79 seconds
Started Jul 28 06:40:40 PM PDT 24
Finished Jul 28 06:46:23 PM PDT 24
Peak memory 201196 kb
Host smart-eee098b6-fa21-4abd-b79a-af664a378dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978711248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3978711248
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2722729949
Short name T663
Test name
Test status
Simulation time 332330721920 ps
CPU time 202.05 seconds
Started Jul 28 06:40:39 PM PDT 24
Finished Jul 28 06:44:02 PM PDT 24
Peak memory 201144 kb
Host smart-7648807c-8054-4326-ba9a-93e42ad7f714
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722729949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2722729949
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2059778660
Short name T251
Test name
Test status
Simulation time 337976166294 ps
CPU time 378.68 seconds
Started Jul 28 06:40:41 PM PDT 24
Finished Jul 28 06:46:59 PM PDT 24
Peak memory 201168 kb
Host smart-b0d6c4d4-80f0-49b4-a3b8-c4392f41acdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059778660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2059778660
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.116584199
Short name T628
Test name
Test status
Simulation time 197024206194 ps
CPU time 29.83 seconds
Started Jul 28 06:40:41 PM PDT 24
Finished Jul 28 06:41:11 PM PDT 24
Peak memory 201112 kb
Host smart-44cc4c3b-5215-4737-9c12-6ea774e89bd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116584199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.116584199
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1098866811
Short name T218
Test name
Test status
Simulation time 75016004336 ps
CPU time 250.64 seconds
Started Jul 28 06:40:42 PM PDT 24
Finished Jul 28 06:44:53 PM PDT 24
Peak memory 201580 kb
Host smart-f2d84b58-d924-467d-9056-62b26b6dc64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098866811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1098866811
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3602842453
Short name T749
Test name
Test status
Simulation time 43826960283 ps
CPU time 27.22 seconds
Started Jul 28 06:40:42 PM PDT 24
Finished Jul 28 06:41:10 PM PDT 24
Peak memory 201012 kb
Host smart-3d796df2-c8b6-44ce-bdc3-ddcee5ed1b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602842453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3602842453
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1196901037
Short name T762
Test name
Test status
Simulation time 3923194730 ps
CPU time 3.05 seconds
Started Jul 28 06:40:44 PM PDT 24
Finished Jul 28 06:40:47 PM PDT 24
Peak memory 200968 kb
Host smart-224aa09d-3c63-496a-a098-113968a4d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196901037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1196901037
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4223843708
Short name T467
Test name
Test status
Simulation time 5667413334 ps
CPU time 4.39 seconds
Started Jul 28 06:40:29 PM PDT 24
Finished Jul 28 06:40:33 PM PDT 24
Peak memory 201044 kb
Host smart-9662095f-2336-4880-9b74-df29d15845bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223843708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4223843708
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2971797817
Short name T142
Test name
Test status
Simulation time 354108349782 ps
CPU time 354.4 seconds
Started Jul 28 06:40:42 PM PDT 24
Finished Jul 28 06:46:36 PM PDT 24
Peak memory 201272 kb
Host smart-4562eed3-7b78-4999-9275-2f241f146a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971797817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2971797817
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1060861260
Short name T295
Test name
Test status
Simulation time 148749321690 ps
CPU time 92.37 seconds
Started Jul 28 06:40:43 PM PDT 24
Finished Jul 28 06:42:15 PM PDT 24
Peak memory 209448 kb
Host smart-f2b56195-719b-4fcf-98fd-38436c78727a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060861260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1060861260
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2683627031
Short name T424
Test name
Test status
Simulation time 328139867 ps
CPU time 1.4 seconds
Started Jul 28 06:40:58 PM PDT 24
Finished Jul 28 06:41:00 PM PDT 24
Peak memory 200920 kb
Host smart-6dd605f2-2d48-4012-b4e3-2259b7bbff7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683627031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2683627031
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1299261336
Short name T250
Test name
Test status
Simulation time 596006569715 ps
CPU time 509.18 seconds
Started Jul 28 06:40:53 PM PDT 24
Finished Jul 28 06:49:22 PM PDT 24
Peak memory 201136 kb
Host smart-843e65f5-d463-43f7-8bbf-7030db5bf879
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299261336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1299261336
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3153517020
Short name T270
Test name
Test status
Simulation time 347029277770 ps
CPU time 778.48 seconds
Started Jul 28 06:40:53 PM PDT 24
Finished Jul 28 06:53:52 PM PDT 24
Peak memory 201236 kb
Host smart-825066e1-c452-44af-9f9f-d33de3ef2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153517020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3153517020
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3265995350
Short name T215
Test name
Test status
Simulation time 493263132198 ps
CPU time 313.09 seconds
Started Jul 28 06:40:53 PM PDT 24
Finished Jul 28 06:46:06 PM PDT 24
Peak memory 201168 kb
Host smart-f39a8f1c-a747-48bf-b3d7-ec28f8787cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265995350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3265995350
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.825267900
Short name T96
Test name
Test status
Simulation time 493722482132 ps
CPU time 606.92 seconds
Started Jul 28 06:40:54 PM PDT 24
Finished Jul 28 06:51:02 PM PDT 24
Peak memory 201448 kb
Host smart-f0e9387e-349e-4946-a867-4cc246ec850f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=825267900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.825267900
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3101006767
Short name T149
Test name
Test status
Simulation time 157981143188 ps
CPU time 101.83 seconds
Started Jul 28 06:40:48 PM PDT 24
Finished Jul 28 06:42:30 PM PDT 24
Peak memory 201276 kb
Host smart-1e3c2f2b-06a9-4584-81bb-0776ce5bb024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101006767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3101006767
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3717533118
Short name T374
Test name
Test status
Simulation time 171215142006 ps
CPU time 367.58 seconds
Started Jul 28 06:40:47 PM PDT 24
Finished Jul 28 06:46:55 PM PDT 24
Peak memory 201072 kb
Host smart-8cb9e0dd-d03a-4246-a08c-9c97ef52d6ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717533118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3717533118
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4064089495
Short name T8
Test name
Test status
Simulation time 621409007873 ps
CPU time 777.05 seconds
Started Jul 28 06:40:51 PM PDT 24
Finished Jul 28 06:53:48 PM PDT 24
Peak memory 201208 kb
Host smart-77292fc0-a1d5-4c31-bd95-a046e7812f34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064089495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4064089495
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2321877704
Short name T103
Test name
Test status
Simulation time 601271215120 ps
CPU time 1319.95 seconds
Started Jul 28 06:40:52 PM PDT 24
Finished Jul 28 07:02:53 PM PDT 24
Peak memory 201160 kb
Host smart-3e18c082-2f01-4dde-9532-48d5508673c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321877704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2321877704
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.762767749
Short name T217
Test name
Test status
Simulation time 92741855699 ps
CPU time 322.08 seconds
Started Jul 28 06:40:52 PM PDT 24
Finished Jul 28 06:46:14 PM PDT 24
Peak memory 201604 kb
Host smart-ecb86042-55c9-4741-bb5f-0be093ca4126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762767749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.762767749
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.322717754
Short name T386
Test name
Test status
Simulation time 35848964356 ps
CPU time 10.63 seconds
Started Jul 28 06:40:53 PM PDT 24
Finished Jul 28 06:41:04 PM PDT 24
Peak memory 200960 kb
Host smart-7a01d3eb-920f-4364-8725-b2d68403bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322717754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.322717754
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2320597006
Short name T737
Test name
Test status
Simulation time 4064097605 ps
CPU time 3.07 seconds
Started Jul 28 06:40:53 PM PDT 24
Finished Jul 28 06:40:57 PM PDT 24
Peak memory 201000 kb
Host smart-c8233811-fc0d-402f-9951-434d266b3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320597006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2320597006
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2769345498
Short name T459
Test name
Test status
Simulation time 5862011938 ps
CPU time 14.91 seconds
Started Jul 28 06:40:46 PM PDT 24
Finished Jul 28 06:41:01 PM PDT 24
Peak memory 201044 kb
Host smart-32945e01-f433-442e-a4f8-66edbdb00da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769345498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2769345498
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2595607794
Short name T241
Test name
Test status
Simulation time 610206140428 ps
CPU time 969.69 seconds
Started Jul 28 06:40:58 PM PDT 24
Finished Jul 28 06:57:08 PM PDT 24
Peak memory 209792 kb
Host smart-4f1699f2-cdf1-43d7-90e6-6ed8b33171c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595607794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2595607794
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3874142085
Short name T343
Test name
Test status
Simulation time 362771347871 ps
CPU time 221.69 seconds
Started Jul 28 06:40:57 PM PDT 24
Finished Jul 28 06:44:39 PM PDT 24
Peak memory 209928 kb
Host smart-38af97c6-6800-4762-8a29-82f8370c2180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874142085 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3874142085
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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