Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6790	1			T6	19		T9	6		T13	8
testmodes[AdcCtrlTestmodeNormal]	5387	1			T1	2		T2	2		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5433	1			T5	13		T7	2		T9	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3702	1			T6	10		T9	2		T13	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1701	1			T6	8		T9	4		T13	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1273	1			T27	19		T40	19		T41	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1696	1			T6	9		T9	4		T13	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2007	1			T1	1		T2	1		T4	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1346	1			T9	1		T39	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1282	1			T27	26		T33	1		T40	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1337	1			T9	2		T39	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2567	1			T5	12		T7	1		T10	1