Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22224

1

T2

1

T3

1

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3631

1

T1

2

T2

1

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19797

1

T1

2

T2

1

T5

13

auto[1]

6058

1

T2

1

T3

1

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T212	8		T213	1		-	-
values[0]	14	1			T214	1		T215	13		-	-
values[1]	755	1			T39	2		T72	16		T216	1
values[2]	751	1			T12	8		T13	3		T24	15
values[3]	602	1			T4	1		T7	13		T12	11
values[4]	2984	1			T2	1		T3	1		T8	1
values[5]	751	1			T11	11		T25	21		T31	5
values[6]	807	1			T4	1		T29	2		T158	14
values[7]	625	1			T12	3		T26	12		T148	1
values[8]	652	1			T1	1		T2	1		T7	19
values[9]	1224	1			T1	1		T9	8		T39	30
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	930	1			T39	2		T72	16		T216	2
values[1]	693	1			T12	8		T13	3		T24	15
values[2]	823	1			T2	1		T4	1		T7	13
values[3]	2884	1			T3	1		T8	1		T10	13
values[4]	616	1			T11	11		T25	7		T29	2
values[5]	899	1			T4	1		T148	1		T130	1
values[6]	587	1			T7	19		T12	3		T39	2
values[7]	744	1			T1	1		T2	1		T23	23
values[8]	827	1			T1	1		T9	8		T13	3
values[9]	171	1			T39	30		T137	9		T217	35
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T39	1		T216	2		T95	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T72	6		T36	12		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	16		T139	1		T72	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	8		T13	2		T24	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	1		T4	1		T7	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	11		T69	2		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T3	1		T8	1		T10	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T25	1		T28	15		T151	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	7		T29	1		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T25	1		T29	1		T70	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T4	1		T158	14		T70	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T148	1		T130	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	1		T139	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	12		T12	3		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T131	1		T69	12		T70	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T2	1		T23	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T24	10		T26	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T9	4		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T39	17		T137	1		T217	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T218	14		T219	2		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	1		T95	3		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T72	10		T36	7		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T131	13		T72	2		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T25	5		T26	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	7		T133	12		T76	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T69	7		T34	2		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T38	25		T135	5		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T25	13		T124	1		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	4		T152	6		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	6		T70	2		T178	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T70	11		T170	15		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	6		T34	3		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	1		T130	4		T32	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	7		T26	11		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	5		T69	3		T70	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T23	8		T124	2		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	8		T150	4		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	4		T13	1		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T39	13		T137	8		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T218	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T212	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T214	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T215	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T39	1		T216	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T72	6		T217	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	1		T72	4		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	8		T13	2		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T7	6		T31	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	11		T226	1		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T2	1		T3	1		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T28	15		T151	18		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	7		T31	5		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	2		T70	3		T227	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T4	1		T29	1		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	1		T150	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	1		T139	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	3		T26	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	1		T70	3		T178	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T2	1		T7	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T39	17		T24	10		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T1	1		T9	4		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	1		T95	3		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T72	10		T221	2		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T72	2		T32	11		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T25	5		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	7		T131	13		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T16	4		T228	8		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T38	25		T135	5		T223	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T124	1		T14	3		T69	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	4		T152	6		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	19		T70	2		T227	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T140	4		T36	6		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T150	6		T34	3		T224	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	5		T130	4		T70	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	11		T132	11		T124	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	1		T70	7		T178	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	7		T23	8		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T39	13		T26	8		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	4		T13	1		T150	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	2		T216	2		T95	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T72	11		T36	12		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	14		T139	1		T72	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T13	3		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	1		T4	1		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T69	8		T34	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T3	1		T8	1		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T25	14		T28	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	5		T29	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T25	7		T29	1		T70	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T158	1		T70	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T148	1		T130	1		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	2		T139	1		T130	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	8		T12	1		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	6		T69	4		T70	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T2	1		T23	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	1		T26	9		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T9	7		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T39	14		T137	9		T217	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T218	14		T219	2		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T155	7		T164	17		T230	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T72	5		T36	7		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T131	15		T72	3		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	7		T24	14		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	5		T31	20		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	10		T69	1		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T10	11		T30	39		T175	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	14		T151	17		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	6		T31	4		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T70	2		T178	16		T160	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T158	13		T70	13		T74	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	3		T141	8		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T158	12		T32	4		T178	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	11		T12	2		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T69	11		T70	2		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T23	14		T28	19		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	9		T150	9		T133	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T13	1		T146	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T39	16		T217	19		T212	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T218	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T212	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T214	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T215	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	2		T216	1		T95	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T72	11		T217	1		T221	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	1		T72	3		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	1		T13	3		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	1		T7	8		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T226	1		T16	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T2	1		T3	1		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T28	1		T151	1		T124	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	5		T31	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	21		T70	3		T227	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T29	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	1		T150	7		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T131	6		T139	1		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T26	12		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T39	2		T70	8		T178	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T2	1		T7	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T39	14		T24	1		T26	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T1	1		T9	7		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T212	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T215	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T192	13		T155	7		T164	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T72	5		T231	14		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T72	3		T32	4		T232	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	7		T24	14		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	5		T31	20		T131	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T12	10		T16	6		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T10	11		T30	39		T175	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	14		T151	17		T14	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	6		T31	4		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T70	2		T227	11		T178	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T158	13		T36	6		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	3		T141	8		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T158	12		T70	13		T74	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	2		T124	15		T72	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T70	2		T178	15		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	11		T23	14		T28	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T39	16		T24	9		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	1		T13	1		T158	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22217

1

T1

2

T2

1

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3638

1

T2

1

T4

1

T7

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19798

1

T1

2

T2

2

T5

13

auto[1]

6057

1

T3

1

T4

2

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T139	1		T233	1		T215	13
values[0]	62	1			T39	2		T143	9		T157	11
values[1]	734	1			T1	1		T4	1		T11	11
values[2]	878	1			T12	8		T137	9		T139	1
values[3]	766	1			T7	19		T26	9		T31	9
values[4]	756	1			T1	1		T2	1		T9	8
values[5]	2861	1			T3	1		T8	1		T10	13
values[6]	738	1			T7	13		T25	7		T29	1
values[7]	762	1			T12	14		T13	3		T26	23
values[8]	519	1			T2	1		T25	14		T29	1
values[9]	1083	1			T4	1		T39	30		T23	23
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	958	1			T1	1		T4	1		T11	11
values[1]	814	1			T7	19		T12	8		T31	9
values[2]	831	1			T1	1		T24	10		T131	6
values[3]	2880	1			T2	1		T3	1		T8	1
values[4]	868	1			T7	13		T25	6		T31	5
values[5]	662	1			T12	11		T25	7		T26	11
values[6]	639	1			T12	3		T13	3		T26	12
values[7]	536	1			T2	1		T4	1		T39	30
values[8]	864	1			T23	23		T28	11		T31	13
values[9]	111	1			T24	15		T28	15		T139	1
minimum	16692	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	1		T11	7		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	1		T13	2		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	8		T137	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	12		T31	9		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T14	7		T69	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T24	10		T131	1		T141	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T3	1		T8	1		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T132	1		T124	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T25	1		T150	10		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	6		T31	5		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T150	12		T216	1		T143	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	11		T25	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	1		T148	1		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	3		T13	2		T131	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	1		T4	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	17		T25	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T158	16		T133	14		T72	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T23	15		T28	11		T31	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T28	15		T234	1		T235	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T24	15		T139	1		T21	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16557	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	4		T39	1		T150	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T178	11		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T137	8		T72	10		T236	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	7		T140	4		T70	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	3		T69	6		T70	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	5		T35	4		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T9	4		T38	25		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T132	11		T124	3		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T25	5		T150	4		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	7		T124	2		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T150	15		T217	10		T170	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	6		T26	10		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	11		T133	9		T76	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T131	10		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	10		T227	5		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	13		T25	13		T36	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T133	9		T72	2		T222	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T23	8		T124	1		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T234	9		T156	8		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T21	2		T238	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T233	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T139	1		T215	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T39	1		T143	9		T239	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T157	11		T240	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T11	7		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T13	2		T28	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	8		T137	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T130	1		T140	1		T70	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T26	1		T14	7		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	12		T31	9		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T9	4		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T24	10		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T3	1		T8	1		T10	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T124	16		T226	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T150	10		T216	1		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	6		T25	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	1		T148	1		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	14		T13	2		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T29	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T25	1		T129	1		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T4	1		T28	15		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T39	17		T23	15		T24	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T39	1		T241	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	4		T150	6		T69	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T178	11		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T137	8		T72	10		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T140	4		T70	7		T190	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T26	8		T14	3		T69	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	7		T35	4		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	4		T39	1		T130	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T131	5		T132	11		T217	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T38	25		T25	5		T135	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T124	3		T169	11		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T150	4		T34	2		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	7		T25	6		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T26	11		T150	15		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T26	10		T131	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T32	10		T37	1		T180	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	13		T36	6		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T133	9		T72	2		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	13		T23	8		T124	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1