Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22189

1

T1

2

T2

1

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3666

1

T2

1

T4

2

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19665

1

T1

2

T2

2

T5

13

auto[1]

6190

1

T3

1

T4

2

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T23	23		T24	15		T28	15
values[0]	37	1			T143	9		T239	13		T241	15
values[1]	764	1			T1	1		T4	1		T11	11
values[2]	887	1			T7	19		T12	8		T31	9
values[3]	794	1			T26	9		T14	10		T69	13
values[4]	748	1			T1	1		T2	1		T9	8
values[5]	2885	1			T3	1		T8	1		T10	13
values[6]	705	1			T7	13		T25	7		T31	5
values[7]	725	1			T12	14		T13	3		T26	23
values[8]	514	1			T2	1		T25	14		T29	1
values[9]	851	1			T4	1		T39	30		T28	11
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T1	1		T11	11		T39	2
values[1]	817	1			T7	19		T12	8		T31	9
values[2]	879	1			T1	1		T24	10		T26	9
values[3]	2858	1			T2	1		T3	1		T8	1
values[4]	834	1			T7	13		T25	6		T31	5
values[5]	726	1			T12	11		T25	7		T26	11
values[6]	575	1			T12	3		T13	3		T26	12
values[7]	515	1			T2	1		T4	1		T25	14
values[8]	864	1			T39	30		T23	23		T28	11
values[9]	133	1			T24	15		T28	15		T139	1
minimum	16884	1			T4	1		T5	13		T6	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T39	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T11	7		T13	2		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	8		T137	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	12		T31	9		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T26	1		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T24	10		T131	1		T141	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T3	1		T8	1		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T132	1		T124	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T7	6		T25	1		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T31	5		T124	13		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	12		T216	1		T35	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	11		T25	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	1		T148	1		T76	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	3		T13	2		T131	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	1		T25	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	1		T129	1		T227	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T124	1		T158	13		T133	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T39	17		T23	15		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T24	15		T28	15		T145	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T139	1		T224	10		T243	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16644	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T4	1		T221	1		T294	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	1		T150	6		T69	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	4		T13	1		T178	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T137	8		T236	15		T160	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	7		T140	4		T70	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	8		T14	3		T69	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T131	5		T35	4		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T9	4		T38	25		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T132	11		T124	3		T130	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	7		T25	5		T150	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T124	2		T169	11		T178	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	9		T236	3		T180	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T25	6		T26	10		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	11		T76	8		T95	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T131	10		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	13		T222	9		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T227	13		T144	12		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T124	1		T133	9		T72	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	13		T23	8		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T156	8		T237	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T224	10		T295	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	2		T294	8		T283	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T24	15		T28	15		T124	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T23	15		T139	1		T158	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T143	9		T239	13		T241	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T39	1		T158	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	1		T11	7		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	8		T137	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	12		T31	9		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T26	1		T14	7		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T141	9		T35	3		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T9	4		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	1		T24	10		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T3	1		T8	1		T10	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T124	13		T216	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	6		T150	10		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T25	1		T31	5		T131	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	1		T148	1		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	14		T13	2		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T25	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T129	1		T227	12		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T139	1		T158	13		T72	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T4	1		T39	17		T28	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T124	1		T133	9		T228	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T23	8		T20	2		T295	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T241	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	1		T150	6		T69	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	4		T13	1		T178	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T137	8		T154	12		T245	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	7		T140	4		T70	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T26	8		T14	3		T69	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	4		T220	12		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	4		T39	1		T69	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T131	5		T132	11		T124	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T38	25		T25	5		T135	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T124	2		T169	11		T178	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	7		T150	4		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T25	6		T131	13		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	11		T133	9		T76	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T26	10		T131	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T25	13		T32	10		T36	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T227	13		T144	12		T180	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T72	2		T222	9		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	13		T133	12		T70	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T39	2		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	5		T13	2		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	1		T137	9		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	8		T31	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T26	9		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T24	1		T131	6		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T3	1		T8	1		T9	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	1		T132	12		T124	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	8		T25	6		T150	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T31	1		T124	3		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T133	10		T216	1		T35	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T25	7		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	12		T148	1		T76	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T13	3		T131	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T25	14		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	1		T129	1		T227	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T124	2		T158	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	14		T23	9		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T24	1		T28	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T139	1		T224	11		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16721	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T4	1		T221	3		T294	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T158	13		T69	1		T74	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	6		T13	1		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	7		T231	14		T245	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	11		T31	8		T70	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	3		T69	6		T70	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	9		T141	8		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T9	1		T10	11		T30	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T124	15		T170	22		T160	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	5		T150	9		T36	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	4		T124	12		T178	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	11		T143	9		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	10		T131	15		T152	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T76	9		T153	6		T163	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	2		T131	8		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T222	9		T32	4		T36	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T227	11		T155	7		T292	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T158	12		T133	13		T72	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T39	16		T23	14		T28	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T24	14		T28	14		T145	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T224	9		T243	10		T295	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T143	8		T145	10		T157	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T294	11		T283	11		T296	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T24	1		T28	1		T124	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T23	9		T139	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T143	1		T239	1		T241	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T39	2		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	1		T11	5		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	1		T137	9		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T31	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T26	9		T14	7		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	1		T35	6		T220	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T9	7		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	1		T24	1		T131	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T3	1		T8	1		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T124	3		T216	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	8		T150	5		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	7		T31	1		T131	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	12		T148	1		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	2		T13	3		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T25	14		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T129	1		T227	14		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	1		T158	1		T72	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T39	14		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T24	14		T28	14		T133	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T23	14		T158	2		T20	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T143	8		T239	12		T241	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	13		T69	1		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	6		T13	1		T28	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	7		T74	6		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	11		T31	8		T70	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	3		T69	6		T70	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	8		T35	1		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T69	11		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	9		T124	15		T217	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T10	11		T30	39		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T124	12		T178	7		T161	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	5		T150	9		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	4		T131	15		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T133	11		T76	9		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	12		T131	8		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	4		T36	6		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T227	11		T155	7		T292	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T158	12		T72	3		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T39	16		T28	10		T31	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11