Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22446

1

T1

2

T3

1

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3409

1

T2

2

T4

1

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19713

1

T1

1

T4

2

T5

13

auto[1]

6142

1

T1

1

T2

2

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T132	12		T95	4		T169	12
values[0]	63	1			T150	27		T299	14		T300	22
values[1]	767	1			T12	3		T24	25		T26	11
values[2]	732	1			T4	1		T9	8		T39	2
values[3]	696	1			T7	19		T11	11		T25	7
values[4]	720	1			T2	1		T12	11		T39	2
values[5]	905	1			T7	13		T26	9		T28	11
values[6]	730	1			T1	1		T2	1		T12	8
values[7]	727	1			T4	1		T124	19		T14	10
values[8]	634	1			T1	1		T39	30		T13	6
values[9]	2934	1			T3	1		T8	1		T10	13
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	701	1			T24	25		T26	11		T129	1
values[1]	718	1			T4	1		T9	8		T39	2
values[2]	670	1			T7	19		T11	11		T23	23
values[3]	945	1			T2	1		T12	11		T39	2
values[4]	665	1			T7	13		T28	11		T29	1
values[5]	740	1			T1	1		T2	1		T12	8
values[6]	2899	1			T3	1		T4	1		T8	1
values[7]	603	1			T1	1		T39	30		T13	6
values[8]	860	1			T25	14		T31	5		T148	1
values[9]	85	1			T132	12		T95	4		T221	12
minimum	16969	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T129	1		T34	2		T35	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T24	25		T26	1		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	1		T25	1		T158	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	4		T39	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	12		T28	15		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	7		T23	15		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T12	11		T28	10		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	1		T39	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	6		T29	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	11		T124	13		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T12	8		T124	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T148	1		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T3	1		T8	1		T10	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T4	1		T26	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	1		T39	17		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	4		T31	13		T32	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	1		T31	5		T131	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T148	1		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T132	1		T95	1		T18	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T221	1		T249	1		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16647	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T141	12		T274	6		T302	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	2		T32	11		T36	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	10		T150	21		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T25	6		T70	2		T76	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	4		T39	1		T25	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	7		T69	6		T72	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	4		T23	8		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T133	12		T69	3		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	1		T26	8		T69	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	7		T246	8		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	2		T142	8		T169	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T124	3		T133	18		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T236	15		T218	11		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T38	25		T135	5		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T26	11		T178	11		T246	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	13		T137	8		T150	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	2		T32	10		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	13		T131	13		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T131	5		T152	6		T130	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T132	11		T95	3		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T221	11		T249	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T274	6		T302	6		T303	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T132	1		T95	1		T169	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T221	1		T225	1		T192	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T300	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T150	12		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	3		T129	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T24	25		T26	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	1		T216	1		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	4		T39	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	12		T25	1		T28	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	7		T130	1		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	11		T28	10		T69	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T39	1		T23	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	6		T29	1		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T26	1		T28	11		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T12	8		T133	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T148	1		T142	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T124	16		T14	7		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T4	1		T226	1		T277	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T39	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	4		T26	1		T31	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T3	1		T8	1		T10	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	1		T131	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T132	11		T95	3		T169	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T221	11		T225	5		T192	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T300	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T150	15		T299	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T34	2		T36	7		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T26	10		T150	6		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T32	11		T227	13		T178	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	4		T39	1		T25	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	7		T25	6		T69	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	4		T130	7		T36	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T69	3		T72	4		T35	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	1		T23	8		T69	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	7		T133	12		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	8		T124	2		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T133	9		T228	8		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T142	8		T169	4		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T124	3		T14	3		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T178	11		T246	4		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	13		T137	8		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	2		T26	11		T32	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T38	25		T25	13		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T131	5		T152	6		T130	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	1		T34	4		T35	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T24	2		T26	11		T150	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T25	7		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	7		T39	2		T25	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	8		T28	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	5		T23	9		T130	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T28	1		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	1		T39	2		T26	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	8		T29	1		T246	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	1		T124	3		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T12	1		T124	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	1		T148	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T3	1		T8	1		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	1		T26	12		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T39	14		T137	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	5		T31	1		T32	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T25	14		T31	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T148	1		T131	6		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T132	12		T95	4		T18	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T221	12		T249	5		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16737	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T141	1		T274	7		T302	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	4		T36	7		T192	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T24	23		T150	11		T222	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T158	12		T70	2		T76	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	1		T151	4		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	11		T28	14		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	6		T23	14		T36	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	10		T28	9		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T151	17		T69	1		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	5		T250	5		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	10		T124	12		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	7		T124	15		T133	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T143	7		T218	13		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T10	11		T30	39		T175	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T178	15		T212	7		T304	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	16		T150	9		T34	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T13	1		T31	12		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	4		T131	15		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	6		T192	13		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T171	7		T248	12		T253	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	2		T252	2		T286	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T141	11		T274	5		T302	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T132	12		T95	4		T169	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T221	12		T225	6		T192	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T150	16		T299	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T129	1		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T24	2		T26	11		T150	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T216	1		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	7		T39	2		T25	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	8		T25	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	5		T130	8		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T28	1		T69	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	1		T39	2		T23	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	8		T29	1		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T26	9		T28	1		T124	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	1		T12	1		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	1		T148	1		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T124	4		T14	7		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T4	1		T226	1		T277	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T39	14		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	5		T26	12		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T3	1		T8	1		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T148	1		T131	6		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T171	7		T285	3		T105	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T192	13		T37	3		T244	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T150	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T36	7		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	23		T141	11		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	4		T227	11		T178	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T151	4		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	11		T28	14		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	6		T36	6		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	10		T28	9		T69	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T23	14		T151	17		T69	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	5		T133	14		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T28	10		T124	12		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	7		T133	13		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T142	6		T143	7		T218	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T124	15		T14	3		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T178	15		T252	10		T279	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	16		T150	9		T34	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T13	1		T31	12		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T10	11		T30	39		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T152	6		T161	8		T155	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11