Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22417

1

T1

1

T2

2

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T1

1

T4

2

T7

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19869

1

T2

2

T5

13

T6

40

auto[1]

5986

1

T1

2

T3

1

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	416	1			T39	30		T131	19		T69	15
values[0]	46	1			T222	5		T35	7		T220	13
values[1]	626	1			T28	10		T29	1		T31	13
values[2]	483	1			T12	11		T31	5		T148	1
values[3]	684	1			T13	3		T26	11		T124	19
values[4]	896	1			T12	3		T25	7		T26	12
values[5]	685	1			T24	15		T29	1		T139	1
values[6]	651	1			T1	1		T39	2		T132	12
values[7]	828	1			T1	1		T4	1		T7	19
values[8]	2865	1			T3	1		T4	1		T8	1
values[9]	994	1			T2	2		T7	13		T13	3
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	443	1			T12	11		T28	10		T29	1
values[1]	483	1			T13	3		T148	1		T124	19
values[2]	866	1			T12	3		T26	11		T131	35
values[3]	845	1			T25	7		T26	12		T148	1
values[4]	655	1			T1	1		T24	15		T29	1
values[5]	687	1			T11	11		T39	2		T31	9
values[6]	2895	1			T1	1		T3	1		T4	1
values[7]	707	1			T2	1		T4	1		T7	13
values[8]	1021	1			T2	1		T39	30		T13	3
values[9]	217	1			T69	15		T143	9		T217	1
minimum	17036	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T28	10		T31	18		T70	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	11		T29	1		T14	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T124	16		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T148	1		T236	1		T274	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	3		T139	1		T69	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T26	1		T131	17		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	13		T74	7		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	1		T26	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T24	15		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	1		T132	1		T72	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	7		T124	1		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	1		T31	9		T158	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T3	1		T8	1		T9	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T4	1		T7	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T151	23		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T7	6		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	1		T39	17		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T25	1		T26	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T145	11		T239	13		T257	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T69	12		T143	9		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16654	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T152	7		T222	3		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T70	7		T180	12		T267	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T14	3		T236	2		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T124	3		T150	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T236	3		T274	6		T163	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T69	7		T95	3		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	10		T131	18		T178	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	1		T154	11		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T25	6		T26	11		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T130	7		T133	12		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T132	11		T72	10		T246	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	4		T124	1		T150	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	1		T76	8		T134	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T9	4		T38	25		T135	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	7		T124	2		T137	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T130	4		T140	4		T70	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	7		T39	1		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T39	13		T13	1		T23	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T25	13		T26	8		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T181	4		T305	5		T259	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T69	3		T17	1		T261	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T152	6		T222	2		T35	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	17		T131	9		T218	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T69	12		T143	9		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T220	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T222	3		T35	3		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	10		T31	13		T70	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	1		T152	7		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T31	5		T150	10		T72	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	11		T148	1		T231	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	2		T124	16		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	1		T130	1		T35	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	3		T236	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T25	1		T26	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T24	15		T130	1		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	1		T139	1		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T124	1		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	1		T132	1		T158	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	4		T11	7		T28	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T4	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T3	1		T8	1		T10	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T39	1		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	2		T13	2		T23	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T7	6		T25	1		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	13		T131	10		T218	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T69	3		T250	8		T261	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T220	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T222	2		T35	4		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T70	7		T153	4		T180	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T152	6		T14	3		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T150	4		T72	2		T246	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T236	3		T245	13		T274	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T124	3		T69	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T26	10		T178	13		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T236	15		T154	11		T245	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T25	6		T26	11		T131	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	7		T32	10		T170	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T72	10		T170	15		T246	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T124	1		T150	21		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T39	1		T132	11		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	4		T11	4		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	7		T137	8		T72	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T38	25		T135	5		T223	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	1		T124	2		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T23	8		T25	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	7		T25	13		T26	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	1		T31	2		T70	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	1		T29	1		T14	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T124	4		T150	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T148	1		T236	4		T274	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	1		T139	1		T69	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T26	11		T131	20		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	1		T74	1		T153	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T25	7		T26	12		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	1		T24	1		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	1		T132	12		T72	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	5		T124	2		T150	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	2		T31	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T3	1		T8	1		T9	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T4	1		T7	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T151	2		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T7	8		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	1		T39	14		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T25	14		T26	9		T190	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T145	1		T239	1		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T69	4		T143	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16783	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T152	7		T222	3		T35	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	9		T31	16		T70	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	10		T14	3		T231	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	1		T124	15		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T274	5		T163	13		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	2		T69	1		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T131	15		T158	13		T178	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T158	12		T74	6		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T227	11		T170	22		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	14		T133	14		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T72	5		T231	14		T286	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	6		T150	11		T227	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	8		T158	2		T76	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T9	1		T10	11		T28	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	11		T12	7		T28	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	21		T70	13		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	5		T133	11		T70	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T39	16		T23	14		T24	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	7		T217	19		T160	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T145	10		T239	12		T257	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T69	11		T143	8		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T153	6		T245	16		T83	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T152	6		T222	2		T35	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	14		T131	11		T218	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T69	4		T143	1		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T220	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T222	3		T35	6		T249	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	1		T31	1		T70	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	1		T152	7		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	1		T150	5		T72	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T148	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	2		T124	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	11		T130	1		T35	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T236	16		T154	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T25	7		T26	12		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T24	1		T130	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	1		T139	1		T72	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T124	2		T150	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	2		T132	12		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	7		T11	5		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T4	1		T7	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T3	1		T8	1		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T39	2		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	2		T13	3		T23	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	8		T25	14		T26	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	16		T131	8		T218	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T69	11		T143	8		T252	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T222	2		T35	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T28	9		T31	12		T70	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T152	6		T14	3		T16	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	4		T150	9		T72	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	10		T231	1		T245	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T124	15		T69	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T178	7		T160	5		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	2		T235	2		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T131	15		T158	13		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	14		T158	12		T74	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T72	5		T170	22		T173	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T150	11		T133	14		T227	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	2		T143	7		T231	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	1		T11	6		T28	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T12	7		T31	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T10	11		T30	39		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	10		T124	12		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T23	14		T24	9		T151	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	5		T36	7		T217	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11