Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22164

1

T1

2

T3

1

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3691

1

T2

2

T4

1

T7

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19882

1

T4

1

T5

13

T6

40

auto[1]

5973

1

T1

2

T2

2

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	306	1			T24	10		T148	1		T190	1
values[0]	43	1			T150	7		T232	13		T298	23
values[1]	742	1			T4	1		T130	5		T158	13
values[2]	2782	1			T1	1		T3	1		T8	1
values[3]	799	1			T11	11		T12	8		T129	1
values[4]	645	1			T2	1		T7	13		T13	3
values[5]	789	1			T12	3		T39	32		T25	6
values[6]	638	1			T7	19		T9	8		T12	11
values[7]	762	1			T1	1		T4	1		T137	9
values[8]	684	1			T2	1		T13	3		T31	9
values[9]	984	1			T23	23		T28	26		T31	13
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T130	5		T150	7		T69	15
values[1]	2927	1			T1	1		T3	1		T8	1
values[2]	732	1			T12	8		T25	14		T226	1
values[3]	713	1			T2	1		T7	13		T39	30
values[4]	664	1			T12	3		T39	4		T25	6
values[5]	662	1			T4	1		T7	19		T9	8
values[6]	776	1			T1	1		T31	9		T151	18
values[7]	710	1			T2	1		T13	3		T151	5
values[8]	825	1			T23	23		T24	10		T28	26
values[9]	263	1			T148	1		T133	50		T134	7
minimum	16939	1			T4	1		T5	13		T6	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T150	1		T69	12		T34	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	1		T15	3		T153	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	1		T3	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	1		T129	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	1		T226	1		T227	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	8		T170	23		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	17		T13	2		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T7	6		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	3		T39	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	1		T26	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	4		T12	11		T150	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	1		T7	12		T24	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T31	9		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	18		T131	16		T72	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T151	5		T124	13		T152	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T13	2		T124	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	10		T148	1		T69	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T23	15		T28	26		T31	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T16	10		T161	9		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T148	1		T133	29		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16601	1			T4	1		T5	13		T6	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T158	13		T216	1		T143	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T150	6		T69	3		T34	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T130	4		T15	1		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T11	4		T38	25		T135	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	6		T130	7		T14	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	13		T227	13		T170	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T170	15		T144	12		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	13		T13	1		T124	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	7		T26	21		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	1		T25	5		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	1		T26	8		T131	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	4		T150	19		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	7		T190	2		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T137	8		T76	8		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	13		T72	2		T227	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T124	2		T152	6		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T124	3		T72	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T69	6		T170	8		T246	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	8		T131	5		T132	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T16	4		T161	6		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T133	21		T134	6		T222	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	2		T33	3		T34	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T297	11		T306	4		T307	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	10		T190	1		T16	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T148	1		T217	20		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T150	1		T298	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T232	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	1		T69	12		T34	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T130	1		T158	13		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T1	1		T3	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	1		T130	1		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	7		T33	1		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	8		T129	1		T141	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	2		T25	1		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T7	6		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	3		T39	18		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T26	1		T29	1		T70	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	4		T12	11		T150	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	12		T39	1		T24	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T137	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T216	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	9		T151	5		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	1		T13	2		T151	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T148	1		T124	13		T152	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T23	15		T28	26		T31	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T16	4		T155	12		T250	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T217	15		T236	2		T218	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T150	6		T298	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T69	3		T34	5		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	4		T153	10		T236	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T38	25		T135	5		T223	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T25	6		T130	7		T14	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	4		T170	9		T228	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T170	15		T144	12		T160	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T25	13		T124	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	7		T26	21		T140	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	14		T25	5		T95	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	8		T70	11		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	4		T150	19		T222	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	7		T39	1		T131	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T137	8		T76	8		T169	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	8		T227	5		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	4		T69	7		T70	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	1		T131	13		T124	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T124	2		T152	6		T69	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T23	8		T131	5		T132	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T150	7		T69	4		T34	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T130	5		T15	4		T153	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	1		T3	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T25	7		T129	1		T130	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T25	14		T226	1		T227	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T170	16		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	14		T13	2		T124	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T7	8		T26	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T39	2		T25	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	2		T26	9		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	7		T12	1		T150	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	1		T7	8		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	1		T31	1		T137	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T151	1		T131	14		T72	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T151	1		T124	3		T152	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	1		T13	3		T124	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T24	1		T148	1		T69	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T23	9		T28	2		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T16	8		T161	7		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T148	1		T133	23		T134	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16779	1			T4	1		T5	13		T6	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T158	1		T216	1		T143	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T69	11		T32	4		T36	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	12		T245	16		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T10	11		T11	6		T30	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	3		T141	8		T160	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T227	11		T170	11		T178	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	7		T170	22		T160	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	16		T13	1		T74	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	5		T28	9		T36	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	2		T141	11		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	8		T70	13		T218	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T12	10		T150	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	11		T24	14		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	8		T158	2		T76	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T151	17		T131	15		T72	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T151	4		T124	12		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T124	15		T72	5		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	9		T69	6		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T23	14		T28	24		T31	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T16	6		T161	8		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T133	27		T222	2		T217	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T34	3		T232	8		T298	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T158	12		T143	9		T145	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T24	1		T190	1		T16	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T148	1		T217	16		T236	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T150	7		T298	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T69	4		T34	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T130	5		T158	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T1	1		T3	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T25	7		T130	8		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	5		T33	1		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T129	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	2		T25	14		T124	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T7	8		T26	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	1		T39	16		T25	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T26	9		T29	1		T70	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	7		T12	1		T150	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	8		T39	2		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T137	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T216	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T31	1		T151	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	1		T13	3		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T148	1		T124	3		T152	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T23	9		T28	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T24	9		T16	6		T155	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T217	19		T218	13		T266	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T298	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T232	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T69	11		T34	3		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T158	12		T143	9		T145	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T10	11		T30	39		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	3		T245	16		T157	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	6		T170	11		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	7		T141	8		T170	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T74	6		T227	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	5		T28	9		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	2		T39	16		T141	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T70	13		T231	1		T218	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T12	10		T150	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	11		T24	14		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T76	9		T178	7		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T142	6		T227	6		T308	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	8		T151	4		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	17		T131	15		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T124	12		T152	6		T69	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T23	14		T28	24		T31	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11