Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20168

1

T1

1

T2

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

5687

1

T1

1

T2

1

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20031

1

T1

1

T2

1

T5

13

auto[1]

5824

1

T1

1

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	366	1			T12	8		T151	18		T148	1
values[0]	50	1			T130	5		T274	24		T239	19
values[1]	761	1			T1	1		T2	1		T39	32
values[2]	775	1			T4	1		T7	13		T9	8
values[3]	542	1			T4	1		T11	11		T131	6
values[4]	693	1			T12	3		T23	23		T24	10
values[5]	604	1			T24	15		T25	6		T28	11
values[6]	727	1			T7	19		T26	11		T139	1
values[7]	776	1			T1	1		T39	2		T13	3
values[8]	796	1			T2	1		T132	12		T124	19
values[9]	3084	1			T3	1		T8	1		T10	13
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	715	1			T1	1		T2	1		T39	32
values[1]	2875	1			T3	1		T4	1		T7	13
values[2]	517	1			T4	1		T11	11		T12	3
values[3]	732	1			T23	23		T24	10		T25	14
values[4]	768	1			T7	19		T24	15		T25	6
values[5]	606	1			T39	2		T26	11		T148	1
values[6]	830	1			T1	1		T2	1		T13	3
values[7]	757	1			T25	7		T29	1		T131	29
values[8]	968	1			T12	8		T151	18		T148	1
values[9]	184	1			T12	11		T152	13		T150	27
minimum	16903	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T2	1		T31	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	18		T13	2		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	10		T151	5		T70	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1456	1			T3	1		T4	1		T7	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	7		T12	3		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	1		T29	1		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T28	15		T31	13		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T23	15		T24	10		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	15		T28	11		T158	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	12		T25	1		T217	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	1		T26	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	7		T74	7		T76	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T129	1		T130	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T2	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T29	1		T132	1		T124	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	1		T131	16		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	8		T158	14		T150	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T151	18		T148	1		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T12	11		T152	7		T150	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T35	4		T157	11		T268	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16627	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T26	1		T130	1		T274	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T69	3		T222	9		T227	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	14		T13	1		T26	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	11		T72	14		T247	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1071	1			T7	7		T9	4		T38	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T11	4		T124	1		T69	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T131	5		T32	11		T190	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	9		T70	9		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T23	8		T25	13		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T221	11		T224	11		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	7		T25	5		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	1		T26	10		T140	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	3		T76	8		T178	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	4		T36	6		T217	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T137	8		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T132	11		T124	3		T130	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	6		T131	13		T34	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T150	4		T133	12		T227	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T131	10		T124	2		T69	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T152	6		T150	15		T274	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T268	7		T269	3		T270	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T26	8		T130	4		T274	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	8		T152	7		T150	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T151	18		T148	1		T35	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T239	19		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T130	1		T274	12		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T2	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	18		T26	2		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	10		T151	5		T70	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	1		T7	6		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	7		T124	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	1		T131	1		T32	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	3		T28	15		T31	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T23	15		T24	10		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T24	15		T28	11		T158	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	1		T15	3		T217	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	1		T139	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	12		T74	7		T76	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	1		T129	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	1		T13	2		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T132	1		T124	16		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	1		T139	1		T34	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	11		T29	1		T158	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1517	1			T3	1		T8	1		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T152	6		T150	15		T133	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T210	9		T250	14		T309	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T130	4		T274	12		T167	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T69	3		T222	9		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	14		T26	19		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T70	11		T72	14		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	7		T9	4		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T11	4		T124	1		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	5		T32	11		T190	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	9		T69	7		T70	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T23	8		T25	13		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T221	11		T224	11		T155	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T25	5		T15	1		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T26	10		T140	4		T72	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	7		T76	8		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	1		T140	4		T134	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T137	8		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T132	11		T124	3		T130	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	3		T35	4		T246	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T150	4		T227	5		T178	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1101	1			T38	25		T25	6		T131	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T2	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	16		T13	3		T26	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	1		T151	1		T70	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1411	1			T3	1		T4	1		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	5		T12	1		T124	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T29	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	1		T31	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T23	9		T24	1		T25	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	1		T28	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	8		T25	6		T217	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	2		T26	11		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	7		T74	1		T76	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T129	1		T130	1		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	1		T2	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T29	1		T132	12		T124	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	7		T131	14		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T158	1		T150	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T151	1		T148	1		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T12	1		T152	7		T150	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T35	4		T157	1		T268	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T26	9		T130	5		T274	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	8		T69	11		T222	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	16		T141	11		T170	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	9		T151	4		T70	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1116	1			T7	5		T9	1		T10	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T11	6		T12	2		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	4		T141	8		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	14		T31	12		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T23	14		T24	9		T164	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	14		T28	10		T158	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	11		T224	9		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T72	3		T32	4		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	3		T74	6		T76	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	6		T217	19		T178	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T170	23		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T124	15		T133	11		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T131	15		T34	3		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	7		T158	13		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T151	17		T131	8		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T12	10		T152	6		T150	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T157	10		T268	4		T171	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T16	6		T155	9		T232	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T274	11		T310	4		T262	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T12	1		T152	7		T150	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T151	1		T148	1		T35	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T239	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T130	5		T274	13		T167	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T2	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	16		T26	21		T150	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	1		T151	1		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T7	8		T9	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	5		T124	2		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T131	6		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	1		T28	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T23	9		T24	1		T25	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T24	1		T28	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	6		T15	4		T217	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T26	11		T139	1		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	8		T74	1		T76	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	2		T129	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T13	2		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T132	12		T124	4		T130	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T139	1		T34	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	1		T29	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1443	1			T3	1		T8	1		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	7		T152	6		T150	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T151	17		T157	10		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T239	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T274	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	8		T69	11		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	16		T143	8		T170	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T28	9		T151	4		T70	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	5		T9	1		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	6		T160	5		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	4		T146	9		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	2		T28	14		T31	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T23	14		T24	9		T31	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	14		T28	10		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T224	9		T192	15		T218	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T72	3		T32	4		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	11		T74	6		T76	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T217	19		T178	15		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T14	3		T170	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T124	15		T133	11		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T34	3		T35	1		T145	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	10		T158	13		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1175	1			T10	11		T30	39		T175	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11