Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22233

1

T1

1

T2

2

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3622

1

T1

1

T4

2

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19936

1

T1

1

T2

1

T5

13

auto[1]

5919

1

T1

1

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	562	1			T28	11		T151	5		T132	12
values[0]	64	1			T34	2		T217	1		T274	12
values[1]	628	1			T4	1		T39	4		T28	15
values[2]	822	1			T7	19		T12	11		T24	10
values[3]	704	1			T4	1		T12	11		T29	1
values[4]	549	1			T1	1		T24	15		T158	3
values[5]	2854	1			T2	1		T3	1		T8	1
values[6]	748	1			T7	13		T11	11		T13	3
values[7]	692	1			T39	30		T25	7		T26	12
values[8]	737	1			T9	8		T25	14		T26	9
values[9]	814	1			T1	1		T2	1		T13	3
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	816	1			T4	1		T39	4		T28	15
values[1]	718	1			T7	19		T12	11		T24	10
values[2]	650	1			T1	1		T4	1		T12	11
values[3]	2642	1			T3	1		T8	1		T10	13
values[4]	828	1			T2	1		T7	13		T13	3
values[5]	685	1			T11	11		T39	30		T25	7
values[6]	719	1			T9	8		T25	14		T26	12
values[7]	680	1			T1	1		T26	9		T31	18
values[8]	1079	1			T2	1		T13	3		T23	23
values[9]	150	1			T95	4		T141	9		T244	2
minimum	16888	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T39	1		T28	15		T69	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	1		T39	1		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	12		T12	8		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	3		T24	10		T28	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T12	11		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T148	1		T158	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T3	1		T8	1		T10	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T134	1		T153	13		T252	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	1		T13	2		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	6		T124	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	7		T39	17		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T26	1		T124	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	1		T129	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	4		T25	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T26	1		T31	13		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T31	5		T131	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T2	1		T13	2		T23	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T132	1		T152	7		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T141	9		T268	11		T304	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T95	1		T244	1		T18	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16606	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T131	9		T69	2		T34	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	1		T69	3		T217	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	1		T150	15		T133	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	7		T25	5		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	5		T140	4		T142	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T150	4		T227	13		T178	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T133	9		T70	7		T34	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T38	25		T135	5		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T134	6		T153	10		T292	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	1		T14	3		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	7		T124	1		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	4		T39	13		T25	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T26	10		T124	3		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T69	6		T35	4		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	4		T25	13		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T26	8		T140	4		T36	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	13		T72	10		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T23	8		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T132	11		T152	6		T130	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T268	7		T287	1		T311	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T95	3		T244	1		T265	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T131	10		T69	7		T170	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T28	11		T151	5		T141	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	1		T152	7		T76	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T217	1		T290	15		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T34	2		T274	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	1		T28	15		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T39	1		T131	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T7	12		T12	8		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	3		T24	10		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	11		T29	1		T124	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T148	1		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T24	15		T72	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T158	3		T134	1		T153	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T2	1		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T124	1		T33	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	7		T13	2		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	6		T26	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T39	17		T25	1		T151	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	1		T124	16		T158	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	1		T29	1		T31	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	4		T25	1		T131	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	1		T13	2		T23	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T31	5		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T313	9		T188	13		T101	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	11		T152	6		T76	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T290	16		T314	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T274	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	1		T221	2		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T131	10		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	7		T25	5		T69	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T131	5		T32	10		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T124	2		T150	4		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	4		T133	9		T70	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T72	2		T154	11		T274	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T134	6		T153	10		T292	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T38	25		T135	5		T14	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T124	1		T150	6		T70	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	4		T13	1		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	7		T26	10		T137	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	13		T25	6		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	11		T124	3		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	8		T140	4		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	4		T25	13		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T23	8		T220	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T130	7		T70	2		T34	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	2		T28	1		T69	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	1		T39	2		T150	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	8		T12	1		T25	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T24	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T12	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T148	1		T158	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T3	1		T8	1		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	7		T153	11		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	1		T13	2		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	8		T124	2		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	5		T39	14		T25	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T26	11		T124	4		T137	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	1		T129	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T9	7		T25	14		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	9		T31	1		T140	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T31	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	1		T13	3		T23	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T132	12		T152	7		T130	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T141	1		T268	8		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T95	4		T244	2		T18	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16756	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T131	11		T69	8		T34	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	14		T69	11		T217	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	11		T133	13		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	11		T12	7		T124	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	2		T24	9		T28	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	10		T150	9		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T158	15		T133	11		T70	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T10	11		T24	14		T30	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T153	12		T252	2		T292	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T14	3		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	5		T70	13		T72	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	6		T39	16		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T124	15		T133	14		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T69	6		T74	6		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T158	12		T143	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T31	12		T36	7		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	4		T131	15		T72	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T23	14		T28	10		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T152	6		T70	2		T76	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T141	8		T268	10		T304	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T243	10		T239	12		T283	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T155	12		T230	1		T105	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T131	8		T69	1		T170	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	1		T151	1		T141	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	12		T152	7		T76	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T217	1		T290	17		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T34	2		T274	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	2		T28	1		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T39	2		T131	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	8		T12	1		T25	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T24	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T29	1		T124	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T148	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T24	1		T72	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T158	1		T134	7		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T2	1		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T124	2		T33	1		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	5		T13	2		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	8		T26	11		T137	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T39	14		T25	7		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	12		T124	4		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	9		T29	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T9	7		T25	14		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	1		T13	3		T23	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T31	1		T130	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	10		T151	4		T141	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	6		T76	9		T178	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T290	14		T314	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T274	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T28	14		T252	2		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	8		T150	11		T133	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	11		T12	7		T69	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T24	9		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	10		T124	12		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T158	13		T133	11		T70	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	14		T72	3		T293	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T158	2		T153	12		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T10	11		T30	39		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T70	13		T224	9		T157	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	6		T13	1		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	5		T72	10		T170	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	16		T151	17		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T124	15		T158	12		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T31	12		T74	6		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	1		T131	15		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T23	14		T36	7		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	4		T70	2		T227	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11