Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T11	5		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	1		T13	2		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T12	1		T137	9		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	8		T31	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	1		T14	7		T69	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	1		T131	6		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T3	1		T8	1		T9	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	1		T132	12		T124	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T25	6		T150	5		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	8		T31	1		T124	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T150	16		T216	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T25	7		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T26	12		T148	1		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T13	3		T131	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T4	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T39	14		T25	14		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T158	2		T133	10		T72	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T23	9		T28	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T28	1		T234	10		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T24	1		T139	1		T21	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16682	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	6		T151	4		T158	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	1		T28	9		T178	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	7		T72	5		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	11		T31	8		T70	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	3		T69	6		T70	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	9		T141	8		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T9	1		T10	11		T30	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T124	15		T170	22		T160	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T150	9		T36	7		T178	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	5		T31	4		T124	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T150	11		T143	9		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	10		T131	15		T152	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	11		T76	9		T153	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	2		T131	8		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T32	4		T227	6		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	16		T36	6		T227	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T158	14		T133	13		T72	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T23	14		T28	10		T31	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T28	14		T235	2		T242	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T24	14		T243	10		T238	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T157	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T233	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T139	1		T215	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T39	2		T143	1		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	1		T240	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T11	5		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T13	2		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	1		T137	9		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T130	1		T140	5		T70	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T26	9		T14	7		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	8		T31	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T9	7		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	1		T24	1		T131	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T3	1		T8	1		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T124	4		T226	1		T169	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T150	5		T216	1		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	8		T25	7		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T26	12		T148	1		T150	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	2		T13	3		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	1		T29	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	14		T129	1		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T28	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	14		T23	9		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T215	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T143	8		T239	12		T241	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T157	10		T240	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	6		T151	4		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T28	9		T178	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	7		T72	5		T74	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T70	2		T231	14		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	3		T69	6		T70	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	11		T31	8		T141	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	1		T69	11		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	9		T217	19		T170	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T10	11		T30	39		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T124	15		T161	8		T244	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T150	9		T143	9		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	5		T31	4		T131	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	11		T133	11		T76	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	12		T131	8		T231	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	4		T145	10		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T36	6		T227	11		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T28	14		T158	14		T133	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T39	16		T23	14		T24	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11