Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22362

1

T1

1

T2

2

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3493

1

T1

1

T4

2

T7

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19717

1

T2

2

T5

13

T6

40

auto[1]

6138

1

T1

2

T3

1

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T217	12		T255	2		T256	3
values[0]	46	1			T222	5		T220	13		T162	5
values[1]	608	1			T28	10		T29	1		T31	13
values[2]	451	1			T12	11		T31	5		T148	1
values[3]	719	1			T13	3		T26	11		T124	19
values[4]	816	1			T12	3		T25	7		T26	12
values[5]	744	1			T24	15		T29	1		T139	1
values[6]	686	1			T1	1		T39	2		T31	9
values[7]	777	1			T1	1		T4	1		T7	19
values[8]	2856	1			T3	1		T4	1		T8	1
values[9]	1454	1			T2	2		T7	13		T39	30
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T12	11		T28	10		T29	1
values[1]	530	1			T13	3		T148	1		T124	19
values[2]	814	1			T12	3		T26	11		T131	35
values[3]	917	1			T25	7		T148	1		T139	1
values[4]	607	1			T1	1		T24	15		T26	12
values[5]	738	1			T11	11		T31	9		T124	2
values[6]	2829	1			T1	1		T3	1		T4	2
values[7]	708	1			T2	1		T7	13		T39	2
values[8]	1062	1			T2	1		T39	30		T13	3
values[9]	196	1			T69	15		T143	9		T217	1
minimum	16699	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	10		T31	18		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	11		T29	1		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	2		T124	16		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T148	1		T14	7		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	3		T139	1		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	1		T131	17		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T25	1		T158	13		T74	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	1		T139	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T24	15		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	1		T29	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	7		T124	1		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T31	9		T76	10		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T3	1		T8	1		T9	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T4	2		T7	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T151	23		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	6		T39	1		T28	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T2	1		T39	17		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T25	1		T26	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T145	11		T257	19		T181	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T69	12		T143	9		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T222	2		T220	12		T153	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T152	6		T70	7		T35	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T124	3		T150	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	3		T236	3		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T69	7		T95	3		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	10		T131	18		T178	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T25	6		T170	8		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T34	2		T227	13		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	7		T133	12		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	11		T132	11		T72	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	4		T124	1		T150	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T76	8		T134	6		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T9	4		T38	25		T135	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	7		T39	1		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	4		T140	4		T70	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	7		T39	1		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T39	13		T13	1		T23	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	13		T26	8		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T181	4		T259	8		T260	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T69	3		T261	10		T262	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T217	1		T255	2		T256	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T222	3		T220	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T249	1		T263	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T28	10		T31	13		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	1		T152	7		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T31	5		T150	10		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	11		T148	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	2		T124	16		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	1		T130	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	3		T25	1		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T26	1		T148	1		T131	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	15		T130	1		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	1		T139	1		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T124	1		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	1		T31	9		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	4		T11	7		T28	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T4	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T3	1		T8	1		T10	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T39	1		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	442	1			T2	2		T39	17		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T7	6		T25	1		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T217	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T222	2		T220	12		T162	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T249	6		T263	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T153	4		T245	14		T265	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T152	6		T14	3		T70	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T150	4		T246	4		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T236	3		T258	9		T245	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T124	3		T69	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T26	10		T160	7		T188	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	6		T236	15		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T26	11		T131	18		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T130	7		T32	10		T170	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T72	10		T170	15		T246	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T124	1		T150	21		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T39	1		T132	11		T134	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	4		T11	4		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	7		T137	8		T72	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T38	25		T135	5		T130	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	1		T124	2		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T39	13		T13	1		T23	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T7	7		T25	13		T26	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	1		T31	2		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T29	1		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T124	4		T150	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T148	1		T14	7		T236	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	1		T139	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T26	11		T131	20		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	7		T158	1		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T148	1		T139	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T24	1		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	12		T29	1		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	5		T124	2		T150	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	1		T76	9		T134	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T3	1		T8	1		T9	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T4	2		T7	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T151	2		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	8		T39	2		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T2	1		T39	14		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T25	14		T26	9		T190	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T145	1		T257	1		T181	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T69	4		T143	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16682	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T28	9		T31	16		T222	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	10		T152	6		T70	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	1		T124	15		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T14	3		T258	7		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	2		T158	13		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	15		T178	7		T160	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T158	12		T74	6		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T227	11		T170	22		T163	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	14		T133	14		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T158	2		T72	5		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	6		T150	11		T227	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T31	8		T76	9		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T9	1		T10	11		T28	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	11		T12	7		T124	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	21		T70	13		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	5		T28	10		T133	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T39	16		T23	14		T24	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T36	7		T160	14		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T145	10		T257	18		T181	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T69	11		T143	8		T261	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T83	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T217	12		T255	2		T256	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T222	3		T220	13		T162	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T249	7		T263	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T28	1		T31	1		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	1		T152	7		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	1		T150	5		T246	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T148	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	2		T124	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	11		T130	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T25	7		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T26	12		T148	1		T131	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	1		T130	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	1		T139	1		T72	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T124	2		T150	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	2		T31	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	7		T11	5		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T4	1		T7	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T3	1		T8	1		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	1		T39	2		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T2	2		T39	14		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T7	8		T25	14		T26	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T256	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T222	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T263	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	9		T31	12		T153	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T152	6		T14	3		T70	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T31	4		T150	9		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	10		T231	1		T258	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T124	15		T69	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T160	5		T188	12		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	2		T158	13		T235	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T131	15		T227	11		T178	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T24	14		T158	12		T74	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T72	5		T170	22		T173	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T150	11		T133	14		T227	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T31	8		T158	2		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T11	6		T28	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	11		T12	7		T72	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T10	11		T30	39		T151	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	10		T124	12		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T39	16		T23	14		T24	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T7	5		T69	11		T36	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11