Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20240

1

T1

1

T2

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

5615

1

T1

1

T2

1

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20078

1

T1

1

T2

1

T5

13

auto[1]

5777

1

T1

1

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T35	4		T37	1		T248	25
values[0]	48	1			T26	9		T130	5		T155	22
values[1]	690	1			T1	1		T2	1		T39	32
values[2]	856	1			T4	1		T7	13		T9	8
values[3]	532	1			T4	1		T11	11		T25	14
values[4]	620	1			T12	3		T23	23		T24	10
values[5]	748	1			T24	15		T25	6		T28	26
values[6]	637	1			T7	19		T26	11		T139	1
values[7]	764	1			T1	1		T39	2		T13	3
values[8]	802	1			T2	1		T132	12		T139	1
values[9]	3437	1			T3	1		T8	1		T10	13
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	862	1			T1	1		T2	1		T39	32
values[1]	2958	1			T3	1		T4	1		T7	13
values[2]	526	1			T4	1		T11	11		T12	3
values[3]	746	1			T23	23		T24	10		T28	26
values[4]	715	1			T7	19		T24	15		T25	6
values[5]	581	1			T39	2		T26	11		T148	1
values[6]	859	1			T1	1		T2	1		T13	3
values[7]	723	1			T25	7		T131	29		T132	12
values[8]	992	1			T12	8		T29	1		T151	18
values[9]	190	1			T12	11		T152	13		T133	27
minimum	16703	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	1		T2	1		T31	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	18		T13	2		T26	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T28	10		T151	5		T70	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1489	1			T3	1		T4	1		T7	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	7		T12	3		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	1		T25	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	26		T31	13		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T23	15		T24	10		T70	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T24	15		T158	3		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	12		T25	1		T76	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	1		T26	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	7		T74	7		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T129	1		T130	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T2	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T132	1		T124	16		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	1		T131	16		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T12	8		T29	1		T158	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T151	18		T148	1		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T12	11		T152	7		T133	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T35	4		T266	3		T157	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16556	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T69	3		T222	9		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	14		T13	1		T26	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T70	11		T72	14		T247	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1080	1			T7	7		T9	4		T38	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	4		T124	1		T69	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	13		T131	5		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T133	9		T70	7		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T23	8		T70	2		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T224	11		T236	2		T218	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	7		T25	5		T76	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	1		T26	10		T140	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	3		T178	11		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T140	4		T36	6		T217	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T137	8		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T132	11		T124	3		T130	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	6		T131	13		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T150	19		T133	9		T227	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T131	10		T124	2		T69	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T152	6		T133	12		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T268	7		T269	3		T270	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T37	1		T248	16		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T35	4		T271	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T155	10		T172	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T26	1		T130	1		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T2	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	18		T26	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	10		T151	5		T70	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	1		T7	6		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	7		T124	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T25	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	3		T31	13		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T23	15		T24	10		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T24	15		T28	26		T158	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T25	1		T15	3		T217	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	1		T139	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	12		T74	7		T76	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	1		T129	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T13	2		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T132	1		T130	1		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	1		T139	1		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T12	19		T29	1		T124	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1651	1			T3	1		T8	1		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T248	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T155	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T26	8		T130	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T69	3		T222	9		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	14		T26	11		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T70	11		T72	14		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	7		T9	4		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	4		T124	1		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	13		T131	5		T32	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T133	9		T69	7		T70	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T23	8		T70	2		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T221	11		T224	11		T218	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	5		T15	1		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	10		T140	4		T72	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	7		T76	8		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	1		T140	4		T134	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T137	8		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T132	11		T130	7		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	4		T246	8		T154	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T124	3		T152	6		T150	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1145	1			T38	25		T25	6		T131	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T2	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T39	16		T13	3		T26	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T28	1		T151	1		T70	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1420	1			T3	1		T4	1		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	5		T12	1		T124	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T25	14		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T28	2		T31	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	9		T24	1		T70	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T24	1		T158	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	8		T25	6		T76	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	2		T26	11		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	7		T74	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T129	1		T130	1		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	1		T2	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T132	12		T124	4		T130	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T25	7		T131	14		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	1		T29	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T151	1		T148	1		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T12	1		T152	7		T133	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	4		T266	1		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16694	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T31	8		T69	11		T222	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	16		T141	11		T170	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	9		T151	4		T70	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1149	1			T7	5		T9	1		T10	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T11	6		T12	2		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T31	4		T141	8		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	24		T31	12		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T23	14		T24	9		T70	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	14		T158	2		T224	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	11		T76	9		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T72	3		T32	4		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	3		T74	6		T178	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	6		T217	19		T178	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T170	23		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T124	15		T34	3		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T131	15		T35	1		T145	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	7		T158	13		T150	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T151	17		T131	8		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T12	10		T152	6		T133	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T266	2		T157	10		T268	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T155	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T37	1		T248	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T35	4		T271	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T155	13		T172	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T26	9		T130	5		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T2	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	16		T26	12		T150	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	1		T151	1		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	1		T7	8		T9	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	5		T124	2		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	1		T25	14		T131	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T31	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T23	9		T24	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	1		T28	2		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	6		T15	4		T217	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	11		T139	1		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	8		T74	1		T76	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	2		T129	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T13	2		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T132	12		T130	8		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T139	1		T35	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T12	2		T29	1		T124	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1502	1			T3	1		T8	1		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T248	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T271	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T155	9		T172	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	8		T69	11		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T39	16		T143	8		T170	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T28	9		T151	4		T70	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	5		T9	1		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	6		T160	5		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T32	4		T146	9		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	2		T31	12		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T23	14		T24	9		T31	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T24	14		T28	24		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T224	9		T192	15		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T72	3		T32	4		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	11		T74	6		T76	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T217	19		T252	2		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T14	3		T170	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T133	11		T34	3		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T35	1		T145	16		T258	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T12	17		T124	15		T152	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T10	11		T30	39		T151	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11