Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21980

1

T2

2

T3

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3875

1

T1

2

T4

2

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19855

1

T1

2

T2

2

T4

2

auto[1]

6000

1

T3

1

T8

1

T9

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	650	1			T1	1		T9	10		T26	9
values[0]	9	1			T249	7		T167	2		-	-
values[1]	921	1			T2	1		T4	1		T7	13
values[2]	2800	1			T3	1		T8	1		T10	13
values[3]	755	1			T25	6		T28	15		T137	9
values[4]	760	1			T29	1		T31	9		T33	1
values[5]	694	1			T2	1		T11	11		T151	18
values[6]	678	1			T1	1		T12	8		T39	2
values[7]	640	1			T28	11		T31	5		T148	1
values[8]	539	1			T7	19		T39	30		T129	1
values[9]	1064	1			T4	1		T12	3		T13	3
minimum	16345	1			T5	13		T6	40		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	894	1			T2	1		T7	13		T23	23
values[1]	2716	1			T3	1		T8	1		T10	13
values[2]	805	1			T25	6		T28	15		T137	9
values[3]	742	1			T29	1		T31	9		T124	19
values[4]	826	1			T2	1		T11	11		T151	18
values[5]	499	1			T1	1		T12	8		T39	2
values[6]	634	1			T31	5		T148	1		T152	13
values[7]	702	1			T7	19		T39	30		T129	1
values[8]	1033	1			T1	1		T4	1		T9	8
values[9]	109	1			T227	12		T236	16		T264	1
minimum	16895	1			T4	1		T5	13		T6	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	1		T25	1		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	6		T23	15		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T3	1		T8	1		T10	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	11		T151	5		T69	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	1		T28	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T130	1		T69	7		T72	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	1		T31	9		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T124	16		T33	1		T141	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	1		T11	7		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T151	18		T131	16		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	1		T74	7		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T12	8		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T148	1		T14	7		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	5		T152	7		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	12		T129	1		T139	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	17		T131	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	3		T13	2		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T1	1		T4	1		T9	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T264	1		T254	4		T272	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T227	7		T236	1		T252	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T4	1		T163	12		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T25	13		T124	1		T140	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	7		T23	8		T26	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T38	25		T39	1		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T69	3		T76	8		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T25	5		T137	8		T178	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T130	4		T69	6		T72	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T130	7		T133	9		T72	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T124	3		T220	12		T170	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	4		T133	12		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T131	13		T132	11		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T25	6		T95	3		T244	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T39	1		T131	10		T153	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	3		T32	11		T36	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T152	6		T19	1		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	7		T222	2		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	13		T131	5		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T26	8		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T9	4		T124	2		T150	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T254	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T227	5		T236	15		T273	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T155	12		T249	6		T251	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T9	2		T26	1		T27	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	1		T9	4		T36	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	1		T167	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	1		T24	10		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T4	1		T7	6		T23	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T3	1		T8	1		T10	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	11		T28	10		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	1		T28	15		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T130	1		T72	6		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T29	1		T31	9		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	1		T69	7		T141	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T11	7		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T151	18		T132	1		T124	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	1		T14	7		T74	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T12	8		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T148	1		T158	14		T32	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	11		T31	5		T152	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	12		T129	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	17		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	3		T13	2		T69	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	457	1			T4	1		T31	13		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16210	1			T5	13		T6	40		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T26	8		T70	11		T160	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T9	4		T36	7		T227	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T249	6		T167	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	13		T124	1		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	7		T23	8		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T38	25		T39	1		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T76	8		T35	4		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T25	5		T137	8		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	4		T72	10		T134	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T130	7		T133	9		T190	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T69	6		T222	9		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	4		T133	12		T72	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	11		T124	3		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	6		T14	3		T95	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	1		T131	23		T227	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	11		T36	6		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T152	6		T153	1		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	7		T150	6		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T39	13		T131	5		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T69	7		T169	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T124	2		T150	19		T70	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	1		T25	14		T124	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T23	9		T26	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T3	1		T8	1		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T151	1		T69	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	6		T28	1		T137	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T130	5		T69	7		T72	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T29	1		T31	1		T130	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T124	4		T33	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	1		T11	5		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	1		T131	14		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T25	7		T74	1		T95	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T12	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	1		T14	7		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	1		T152	7		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	8		T129	1		T139	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	14		T131	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T13	3		T26	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T1	1		T4	1		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T264	1		T254	4		T272	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T227	6		T236	16		T252	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16720	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T4	1		T163	1		T155	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	3		T224	9		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	5		T23	14		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T10	11		T13	1		T24	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	10		T151	4		T69	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	14		T178	7		T252	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T69	6		T72	5		T178	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	8		T133	11		T72	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T124	15		T141	11		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	6		T133	14		T141	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	17		T131	15		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T74	6		T143	7		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	7		T28	10		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	3		T158	13		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	4		T152	6		T157	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	11		T222	2		T170	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	16		T150	9		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	2		T158	2		T69	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	1		T31	12		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T254	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T227	6		T252	10		T273	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T24	9		T258	7		T164	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T163	11		T155	9		T251	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T9	2		T26	9		T27	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	1		T9	7		T36	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T249	7		T167	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	1		T24	1		T25	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	1		T7	8		T23	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T3	1		T8	1		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T28	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T25	6		T28	1		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T130	5		T72	11		T134	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	1		T31	1		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	1		T69	7		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	1		T11	5		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T151	1		T132	12		T124	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	7		T14	7		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T12	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	1		T158	1		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	1		T31	1		T152	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	8		T129	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	14		T131	6		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T13	3		T69	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T4	1		T31	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16345	1			T5	13		T6	40		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T158	2		T70	13		T160	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T9	1		T36	7		T227	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	9		T34	3		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	5		T23	14		T69	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T10	11		T13	1		T24	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T12	10		T28	9		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	14		T178	7		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T72	5		T178	16		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T31	8		T133	11		T141	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T69	6		T141	11		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	6		T133	14		T72	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	17		T124	15		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	3		T74	6		T275	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	7		T131	23		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	13		T32	4		T36	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	10		T31	4		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	11		T222	2		T170	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	16		T16	6		T192	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	2		T69	1		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T31	12		T124	12		T150	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11