Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22216

1

T2

1

T3

1

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3639

1

T1

2

T2

1

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19805

1

T1

2

T2

1

T5

13

auto[1]

6050

1

T2

1

T3

1

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T13	3		T150	14		T133	21
values[0]	15	1			T39	2		T220	13		-	-
values[1]	724	1			T72	16		T216	1		T95	4
values[2]	754	1			T12	8		T13	3		T24	15
values[3]	618	1			T4	1		T12	11		T31	22
values[4]	3023	1			T2	1		T3	1		T7	13
values[5]	625	1			T25	7		T31	5		T129	1
values[6]	811	1			T4	1		T29	2		T158	14
values[7]	721	1			T12	3		T26	12		T148	1
values[8]	660	1			T1	1		T7	19		T39	2
values[9]	941	1			T1	1		T2	1		T9	8
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	657	1			T26	11		T72	16		T216	2
values[1]	784	1			T12	8		T13	3		T24	15
values[2]	726	1			T2	1		T4	1		T7	13
values[3]	2933	1			T3	1		T8	1		T10	13
values[4]	647	1			T11	11		T25	7		T29	2
values[5]	834	1			T4	1		T130	1		T158	14
values[6]	630	1			T7	19		T12	3		T39	2
values[7]	730	1			T1	1		T2	1		T23	23
values[8]	861	1			T1	1		T9	8		T39	30
values[9]	135	1			T137	9		T217	35		T276	1
minimum	16918	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T216	2		T95	1		T277	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T26	1		T72	6		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T131	16		T139	1		T72	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	8		T13	2		T24	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	1		T4	1		T7	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	11		T69	2		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T3	1		T8	1		T10	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T25	1		T28	15		T151	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	7		T29	1		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T25	1		T29	1		T70	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T4	1		T158	14		T70	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T130	1		T150	1		T34	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	1		T131	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	12		T12	3		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T69	12		T70	3		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T2	1		T23	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T39	17		T24	10		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T9	4		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T137	1		T217	20		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T276	1		T278	14		T279	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16592	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T221	1		T207	13		T239	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T95	3		T169	11		T155	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	10		T72	10		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	13		T72	2		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T25	5		T131	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	7		T133	12		T76	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T69	7		T34	2		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T38	25		T135	5		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T25	13		T124	1		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	4		T152	6		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	6		T70	2		T178	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T70	11		T36	6		T170	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	6		T34	3		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	1		T131	5		T130	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	7		T26	11		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T69	3		T70	7		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T23	8		T124	2		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	13		T26	8		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	4		T13	1		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T137	8		T217	15		T188	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	1		T13	2		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T221	2		T207	12		T280	21

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T150	10		T133	12		T69	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T13	2		T225	1		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	1		T220	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T216	1		T95	1		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T72	6		T217	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T131	16		T139	1		T72	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	8		T13	2		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T31	22		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	11		T69	2		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T2	1		T3	1		T7	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T25	1		T28	15		T151	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	5		T129	1		T152	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	1		T124	1		T70	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T4	1		T29	1		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	1		T150	1		T34	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	1		T139	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	3		T26	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	1		T70	3		T178	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T7	12		T23	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T39	17		T24	10		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	1		T2	1		T9	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T150	4		T133	9		T69	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T13	1		T225	5		T265	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T39	1		T220	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T95	3		T169	11		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T72	10		T221	2		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	13		T72	2		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T25	5		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T133	12		T76	8		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T69	7		T34	2		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T7	7		T11	4		T38	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T25	13		T14	3		T134	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	6		T190	2		T247	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T25	6		T124	1		T70	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T140	4		T36	6		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	6		T34	3		T224	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T131	5		T130	4		T70	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	11		T132	11		T124	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	1		T70	7		T178	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	7		T23	8		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	13		T26	8		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	4		T150	15		T35	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T216	2		T95	4		T277	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T26	11		T72	11		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T131	14		T139	1		T72	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T13	3		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T4	1		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T69	8		T34	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T3	1		T8	1		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T25	14		T28	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	5		T29	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T25	7		T29	1		T70	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	1		T158	1		T70	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T130	1		T150	7		T34	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	2		T131	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	8		T12	1		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T69	4		T70	8		T221	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T2	1		T23	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	14		T24	1		T26	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T9	7		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	9		T217	16		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T276	1		T278	1		T279	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16724	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T221	3		T207	13		T239	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T155	7		T243	10		T281	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T72	5		T231	14		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	15		T72	3		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	7		T24	14		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	5		T31	20		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	10		T69	1		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T10	11		T30	39		T175	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T28	14		T151	17		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	6		T31	4		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T70	2		T178	16		T160	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T158	13		T70	13		T74	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	3		T141	8		T231	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T158	12		T32	4		T178	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	11		T12	2		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T69	11		T70	2		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T23	14		T28	19		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	16		T24	9		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T13	1		T218	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T217	19		T188	12		T212	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T278	13		T279	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T164	17		T230	1		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T207	12		T239	18		T215	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T150	5		T133	10		T69	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T13	2		T225	6		T265	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T39	2		T220	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T216	1		T95	4		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T72	11		T217	1		T221	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	14		T139	1		T72	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	1		T13	3		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T31	2		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T69	8		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T2	1		T3	1		T7	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T25	14		T28	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T31	1		T129	1		T152	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T25	7		T124	2		T70	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	1		T29	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	1		T150	7		T34	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	6		T139	1		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T26	12		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	2		T70	8		T178	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T7	8		T23	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	14		T24	1		T26	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T1	1		T2	1		T9	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T150	9		T133	11		T69	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T13	1		T251	10		T238	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T155	7		T164	17		T230	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T72	5		T231	14		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	15		T72	3		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	7		T24	14		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	20		T133	14		T76	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	10		T69	1		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T7	5		T10	11		T11	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T28	14		T151	17		T14	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T31	4		T152	6		T218	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T70	2		T178	16		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T158	13		T36	6		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	3		T141	8		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T158	12		T70	13		T74	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	2		T124	15		T72	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	2		T178	15		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	11		T23	14		T28	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	16		T24	9		T69	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	1		T158	2		T150	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11