Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21886

1

T2

2

T3

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3969

1

T1

2

T4

2

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19667

1

T2

1

T4

2

T5

13

auto[1]

6188

1

T1

2

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T9	2		T27	1		T33	7
values[0]	44	1			T233	19		T163	12		T249	7
values[1]	898	1			T2	1		T4	1		T7	13
values[2]	2799	1			T3	1		T8	1		T10	13
values[3]	725	1			T25	6		T28	15		T137	9
values[4]	766	1			T29	1		T31	9		T33	1
values[5]	662	1			T2	1		T11	11		T131	19
values[6]	682	1			T1	1		T12	8		T39	2
values[7]	684	1			T28	11		T31	5		T148	1
values[8]	512	1			T7	19		T39	30		T129	1
values[9]	1391	1			T1	1		T4	1		T9	8
minimum	16345	1			T5	13		T6	40		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1084	1			T2	1		T4	1		T7	13
values[1]	2688	1			T3	1		T8	1		T10	13
values[2]	864	1			T24	15		T25	6		T28	15
values[3]	722	1			T29	1		T31	9		T124	19
values[4]	825	1			T2	1		T11	11		T151	18
values[5]	511	1			T1	1		T12	8		T25	7
values[6]	615	1			T39	2		T31	5		T148	1
values[7]	660	1			T7	19		T39	30		T129	1
values[8]	1029	1			T1	1		T4	1		T9	8
values[9]	155	1			T13	3		T227	12		T236	16
minimum	16702	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T2	1		T24	10		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T4	1		T7	6		T23	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T3	1		T8	1		T10	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	1		T13	2		T151	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T24	15		T137	1		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T25	1		T28	15		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	4		T93	1		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T29	1		T31	9		T124	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T11	7		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T151	18		T131	16		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	1		T74	7		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T12	8		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T39	1		T31	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T148	1		T152	7		T226	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	12		T129	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	17		T131	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T124	13		T158	3		T69	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	1		T4	1		T9	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T13	2		T227	7		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T236	1		T252	11		T85	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T251	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T25	13		T124	1		T140	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	7		T23	8		T26	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T38	25		T26	10		T135	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	1		T13	1		T69	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T137	8		T130	11		T134	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T25	5		T69	6		T72	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T72	2		T190	6		T169	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T124	3		T133	9		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	4		T132	11		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T131	13		T34	2		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T25	6		T95	3		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	10		T153	1		T236	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	1		T14	3		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T152	6		T207	12		T177	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	7		T150	6		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	13		T131	5		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T124	2		T69	7		T70	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T9	4		T26	8		T150	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T13	1		T227	5		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T236	15		T283	7		T273	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T9	2		T27	1		T33	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T252	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T167	1		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T233	19		T163	12		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T24	10		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	1		T7	6		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T3	1		T8	1		T10	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	1		T28	10		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T137	1		T130	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T25	1		T28	15		T72	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T130	1		T93	1		T141	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T29	1		T31	9		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T11	7		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T131	9		T124	16		T158	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	1		T25	1		T133	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T12	8		T151	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T31	5		T14	7		T158	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T28	11		T148	1		T152	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	12		T129	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	17		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	2		T124	13		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	433	1			T1	1		T4	1		T9	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16210	1			T5	13		T6	40		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T167	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T249	6		T219	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T25	13		T26	10		T124	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	7		T13	1		T23	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T38	25		T135	5		T223	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	1		T76	8		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T137	8		T130	4		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	5		T72	10		T170	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	7		T190	6		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T133	9		T69	6		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	4		T132	11		T72	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	10		T124	3		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T39	1		T25	6		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	13		T227	13		T160	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	3		T32	11		T36	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T152	6		T153	1		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	7		T222	2		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	13		T131	5		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	1		T124	2		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T9	4		T26	8		T150	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T2	1		T24	1		T25	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T4	1		T7	8		T23	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T3	1		T8	1		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	2		T13	2		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	1		T137	9		T130	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T25	6		T28	1		T69	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T72	3		T93	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	1		T31	1		T124	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	1		T11	5		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T151	1		T131	14		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T25	7		T74	1		T95	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T12	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	2		T31	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T148	1		T152	7		T226	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	8		T129	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	14		T131	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T124	3		T158	1		T69	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T1	1		T4	1		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T13	3		T227	6		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T236	16		T252	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T251	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T24	9		T133	13		T34	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	5		T23	14		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T10	11		T12	10		T30	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	1		T151	4		T69	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T24	14		T142	6		T178	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T28	14		T69	6		T72	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T72	3		T141	11		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T31	8		T124	15		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	6		T133	14		T141	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T151	17		T131	15		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T74	6		T143	7		T239	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	7		T28	10		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T31	4		T14	3		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T152	6		T231	1		T157	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	11		T222	2		T32	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	16		T150	9		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T124	12		T158	2		T69	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T12	2		T31	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T227	6		T252	2		T285	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T252	10		T85	2		T283	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T9	2		T27	1		T33	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T167	2		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T233	1		T163	1		T249	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T24	1		T25	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	1		T7	8		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T3	1		T8	1		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	2		T28	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	9		T130	5		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T25	6		T28	1		T72	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	8		T93	1		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T29	1		T31	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T11	5		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	11		T124	4		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	2		T25	7		T133	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T12	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	1		T14	7		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T28	1		T148	1		T152	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	8		T129	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	14		T131	6		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	3		T124	3		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	494	1			T1	1		T4	1		T9	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16345	1			T5	13		T6	40		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T252	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T233	18		T163	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	9		T258	7		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	5		T13	1		T23	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T10	11		T12	10		T24	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	9		T151	4		T76	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T178	23		T252	2		T286	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	14		T72	5		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	19		T142	6		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	8		T133	11		T69	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	6		T72	3		T188	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T131	8		T124	15		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T133	14		T74	6		T275	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	7		T151	17		T131	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T31	4		T14	3		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	10		T152	6		T231	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	11		T222	2		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	16		T16	6		T170	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T124	12		T158	2		T69	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T9	1		T12	2		T31	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11