Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25855

1

T1

2

T2

2

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22218

1

T1

1

T2

2

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3637

1

T1

1

T4

2

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19915

1

T1

1

T2

1

T5

13

auto[1]

5940

1

T1

1

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

2

T2

2

T3

1

auto[1]

4113

1

T7

14

T9

4

T11

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	73	1			T76	18		T239	13		T257	19
values[0]	110	1			T133	23		T34	2		T274	12
values[1]	649	1			T4	1		T39	4		T28	15
values[2]	784	1			T7	19		T12	11		T24	10
values[3]	683	1			T1	1		T4	1		T12	11
values[4]	544	1			T24	15		T29	1		T158	14
values[5]	2845	1			T2	1		T3	1		T8	1
values[6]	765	1			T7	13		T11	11		T13	3
values[7]	588	1			T39	30		T25	7		T26	12
values[8]	823	1			T9	8		T25	14		T26	9
values[9]	1310	1			T1	1		T2	1		T13	3
minimum	16681	1			T5	13		T6	40		T9	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	982	1			T4	1		T39	2		T28	15
values[1]	713	1			T12	11		T39	2		T24	10
values[2]	706	1			T4	1		T7	19		T12	11
values[3]	2692	1			T1	1		T2	1		T3	1
values[4]	714	1			T7	13		T13	3		T124	2
values[5]	748	1			T11	11		T39	30		T25	7
values[6]	742	1			T9	8		T25	14		T26	12
values[7]	659	1			T1	1		T26	9		T31	18
values[8]	1012	1			T23	23		T28	11		T151	5
values[9]	205	1			T2	1		T13	3		T152	13
minimum	16682	1			T5	13		T6	40		T9	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

4132

1

T7

16

T9

1

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T39	1		T28	15		T69	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	1		T131	9		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	8		T25	1		T124	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	3		T39	1		T24	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	12		T12	11		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T148	1		T158	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T1	1		T2	1		T3	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T70	14		T134	1		T153	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	2		T14	7		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	6		T124	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	7		T39	17		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	1		T124	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T29	1		T129	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	4		T25	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	1		T31	13		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T31	5		T131	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T23	15		T28	11		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T132	1		T130	1		T76	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T2	1		T13	2		T141	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T152	7		T70	3		T227	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16547	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T39	1		T69	3		T217	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T131	10		T150	15		T133	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T25	5		T124	2		T36	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	1		T131	5		T140	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	7		T150	4		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	9		T70	7		T34	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T38	25		T135	5		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T70	11		T134	6		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T14	3		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	7		T124	1		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	4		T39	13		T25	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T26	10		T124	3		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T69	6		T35	4		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	4		T25	13		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	8		T140	4		T36	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	13		T72	10		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	8		T220	12		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T132	11		T130	7		T76	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T13	1		T268	7		T86	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T152	6		T70	2		T227	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T257	19		T287	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T76	10		T239	13		T288	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T230	3		T251	4		T289	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T133	14		T34	2		T274	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	1		T28	15		T217	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	1		T39	1		T131	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	12		T12	8		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	3		T24	10		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T12	11		T124	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T148	1		T158	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	15		T29	1		T72	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T158	14		T216	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T2	1		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	1		T124	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	7		T13	2		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	6		T137	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T39	17		T25	1		T151	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T26	1		T124	16		T158	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T26	1		T29	1		T31	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	4		T25	1		T31	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T2	1		T13	2		T23	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T1	1		T132	1		T152	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T287	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T76	8		T288	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T230	1		T251	3		T290	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T133	9		T274	6		T291	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	1		T217	15		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	1		T131	10		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	7		T25	5		T69	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	5		T142	8		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T124	2		T150	4		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	4		T133	9		T70	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T72	2		T154	11		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T134	6		T153	10		T292	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T38	25		T135	5		T14	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	10		T124	1		T70	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	4		T13	1		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	7		T137	8		T130	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	13		T25	6		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	11		T124	3		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T26	8		T140	4		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	4		T25	13		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	1		T23	8		T220	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T132	11		T152	6		T130	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T39	2		T28	1		T69	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	1		T131	11		T150	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T25	6		T124	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	1		T39	2		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	8		T12	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T148	1		T158	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	1		T2	1		T3	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T70	12		T134	7		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	2		T14	7		T246	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	8		T124	2		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	5		T39	14		T25	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T26	11		T124	4		T137	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	1		T129	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	7		T25	14		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	9		T31	1		T140	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T31	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T23	9		T28	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T132	12		T130	8		T76	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T2	1		T13	3		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T152	7		T70	3		T227	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16682	1			T5	13		T6	40		T9	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T28	14		T69	11		T217	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T131	8		T150	11		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	7		T124	12		T36	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	2		T24	9		T28	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	11		T12	10		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T158	15		T133	11		T70	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T10	11		T24	14		T30	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T70	13		T153	12		T252	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T14	3		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	5		T72	10		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	6		T39	16		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T124	15		T170	11		T192	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T69	6		T74	6		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T158	12		T133	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T31	12		T36	7		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T31	4		T131	15		T72	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T23	14		T28	10		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T76	9		T170	22		T178	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T141	8		T268	10		T86	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T152	6		T70	2		T227	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T257	1		T287	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T76	9		T239	1		T288	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T230	3		T251	4		T289	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T133	10		T34	2		T274	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	2		T28	1		T217	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T39	2		T131	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	8		T12	1		T25	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T24	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T12	1		T124	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T148	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T24	1		T29	1		T72	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T158	1		T216	1		T134	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T2	1		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	11		T124	2		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	5		T13	2		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	8		T137	9		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	14		T25	7		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T26	12		T124	4		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	9		T29	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	7		T25	14		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T2	1		T13	3		T23	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T1	1		T132	12		T152	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16681	1			T5	13		T6	40		T9	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T257	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T76	9		T239	12		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T230	1		T251	3		T289	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T133	13		T274	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T28	14		T217	19		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	8		T150	11		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	11		T12	7		T69	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	2		T24	9		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	10		T124	12		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T158	2		T133	11		T70	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T24	14		T72	3		T293	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T158	13		T153	12		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T10	11		T30	39		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T70	13		T224	9		T157	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	6		T13	1		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	5		T72	10		T170	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	16		T151	17		T69	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T124	15		T158	12		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	12		T74	6		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	1		T31	4		T131	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T23	14		T28	10		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T152	6		T70	2		T143	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21723

1

T1

2

T2

2

T3

1

auto[1]

auto[0]

4132

1

T7

16

T9

1

T10

11