Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T790 /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1865209597 Jul 29 05:39:52 PM PDT 24 Jul 29 05:43:25 PM PDT 24 376243080342 ps
T791 /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1174957495 Jul 29 05:47:02 PM PDT 24 Jul 29 05:53:40 PM PDT 24 333881904183 ps
T200 /workspace/coverage/default/49.adc_ctrl_fsm_reset.3374495316 Jul 29 05:47:50 PM PDT 24 Jul 29 05:57:36 PM PDT 24 97277562560 ps
T792 /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1134026001 Jul 29 05:40:35 PM PDT 24 Jul 29 05:43:13 PM PDT 24 169551912576 ps
T51 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3525629285 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 595247970 ps
T52 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1205085381 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:52 PM PDT 24 450562252 ps
T46 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2842903878 Jul 29 06:39:55 PM PDT 24 Jul 29 06:39:57 PM PDT 24 446387277 ps
T793 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4116395126 Jul 29 06:39:06 PM PDT 24 Jul 29 06:39:07 PM PDT 24 300562279 ps
T108 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1238298000 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:01 PM PDT 24 477429914 ps
T794 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2022047912 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:08 PM PDT 24 403913288 ps
T43 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.911916567 Jul 29 06:38:51 PM PDT 24 Jul 29 06:38:54 PM PDT 24 4037024146 ps
T53 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.747583897 Jul 29 06:39:18 PM PDT 24 Jul 29 06:39:20 PM PDT 24 322950609 ps
T64 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3705777592 Jul 29 06:39:57 PM PDT 24 Jul 29 06:39:58 PM PDT 24 488720435 ps
T795 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.559108650 Jul 29 06:40:10 PM PDT 24 Jul 29 06:40:11 PM PDT 24 541023689 ps
T60 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3697725955 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:51 PM PDT 24 453580882 ps
T47 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3584095783 Jul 29 06:39:51 PM PDT 24 Jul 29 06:40:02 PM PDT 24 4293415197 ps
T48 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1033905242 Jul 29 06:39:06 PM PDT 24 Jul 29 06:39:13 PM PDT 24 8177232056 ps
T796 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4209008677 Jul 29 06:40:26 PM PDT 24 Jul 29 06:40:27 PM PDT 24 466693291 ps
T797 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1646071460 Jul 29 06:40:28 PM PDT 24 Jul 29 06:40:30 PM PDT 24 350169134 ps
T798 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4286381394 Jul 29 06:40:26 PM PDT 24 Jul 29 06:40:28 PM PDT 24 326783322 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1632219542 Jul 29 06:39:04 PM PDT 24 Jul 29 06:39:06 PM PDT 24 437511788 ps
T799 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3329674015 Jul 29 06:39:08 PM PDT 24 Jul 29 06:39:09 PM PDT 24 405956683 ps
T65 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2207783141 Jul 29 06:38:51 PM PDT 24 Jul 29 06:38:53 PM PDT 24 505718988 ps
T79 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2431533742 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:50 PM PDT 24 564828682 ps
T49 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.402416655 Jul 29 06:39:20 PM PDT 24 Jul 29 06:39:31 PM PDT 24 4430927976 ps
T800 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.937833796 Jul 29 06:40:09 PM PDT 24 Jul 29 06:40:10 PM PDT 24 390312512 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3292265530 Jul 29 06:39:05 PM PDT 24 Jul 29 06:39:08 PM PDT 24 1210471240 ps
T50 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1535113758 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:51 PM PDT 24 4648980861 ps
T88 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.923492096 Jul 29 06:39:04 PM PDT 24 Jul 29 06:39:06 PM PDT 24 358837883 ps
T801 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1501332848 Jul 29 06:38:50 PM PDT 24 Jul 29 06:38:53 PM PDT 24 1022776512 ps
T119 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4281116849 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:13 PM PDT 24 2810702253 ps
T802 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2272630570 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:51 PM PDT 24 450572999 ps
T803 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1246128443 Jul 29 06:40:25 PM PDT 24 Jul 29 06:40:26 PM PDT 24 311939871 ps
T804 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.357998265 Jul 29 06:40:17 PM PDT 24 Jul 29 06:40:18 PM PDT 24 419464483 ps
T44 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1670159367 Jul 29 06:39:06 PM PDT 24 Jul 29 06:39:07 PM PDT 24 475410797 ps
T805 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3484185255 Jul 29 06:40:25 PM PDT 24 Jul 29 06:40:27 PM PDT 24 441545652 ps
T110 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1070102906 Jul 29 06:39:03 PM PDT 24 Jul 29 06:39:05 PM PDT 24 434400958 ps
T45 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1916324791 Jul 29 06:39:54 PM PDT 24 Jul 29 06:39:57 PM PDT 24 3832444234 ps
T120 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.374236825 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:58 PM PDT 24 4430080445 ps
T806 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3197063778 Jul 29 06:40:09 PM PDT 24 Jul 29 06:40:10 PM PDT 24 307902109 ps
T807 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.978267025 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:52 PM PDT 24 768745893 ps
T808 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.362027418 Jul 29 06:40:29 PM PDT 24 Jul 29 06:40:30 PM PDT 24 504719744 ps
T809 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1392314769 Jul 29 06:40:27 PM PDT 24 Jul 29 06:40:28 PM PDT 24 389815262 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4107876301 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:50 PM PDT 24 887546504 ps
T121 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.442272585 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:03 PM PDT 24 1893296906 ps
T810 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1091779895 Jul 29 06:39:54 PM PDT 24 Jul 29 06:39:56 PM PDT 24 401043486 ps
T54 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1366003715 Jul 29 06:39:56 PM PDT 24 Jul 29 06:40:03 PM PDT 24 4390344351 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3866231947 Jul 29 06:38:51 PM PDT 24 Jul 29 06:38:55 PM PDT 24 1072345058 ps
T811 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.915466719 Jul 29 06:40:26 PM PDT 24 Jul 29 06:40:27 PM PDT 24 475121554 ps
T812 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3368907948 Jul 29 06:40:17 PM PDT 24 Jul 29 06:40:18 PM PDT 24 343673314 ps
T813 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.363061276 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:51 PM PDT 24 545731343 ps
T55 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3757273727 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:55 PM PDT 24 8353071359 ps
T814 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4176900129 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:50 PM PDT 24 519458563 ps
T122 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1346096179 Jul 29 06:39:20 PM PDT 24 Jul 29 06:39:22 PM PDT 24 4737101039 ps
T815 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1768785776 Jul 29 06:38:49 PM PDT 24 Jul 29 06:39:07 PM PDT 24 25853491541 ps
T816 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2184296900 Jul 29 06:40:08 PM PDT 24 Jul 29 06:40:10 PM PDT 24 299012547 ps
T817 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2343459029 Jul 29 06:39:48 PM PDT 24 Jul 29 06:39:49 PM PDT 24 484341871 ps
T123 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3046155163 Jul 29 06:39:06 PM PDT 24 Jul 29 06:39:09 PM PDT 24 2782323502 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3234797345 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:50 PM PDT 24 528229565 ps
T819 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2127008999 Jul 29 06:39:57 PM PDT 24 Jul 29 06:39:58 PM PDT 24 410219315 ps
T113 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3600206586 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 503916329 ps
T820 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.566828010 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:51 PM PDT 24 466552771 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2212387590 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 545550090 ps
T822 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.728091624 Jul 29 06:39:18 PM PDT 24 Jul 29 06:39:19 PM PDT 24 512201961 ps
T823 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4223626795 Jul 29 06:39:08 PM PDT 24 Jul 29 06:39:11 PM PDT 24 1009834808 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2376432787 Jul 29 06:39:55 PM PDT 24 Jul 29 06:39:58 PM PDT 24 510081189 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1474112709 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:50 PM PDT 24 862619210 ps
T825 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4014987200 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:48 PM PDT 24 526839539 ps
T826 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.861997023 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:07 PM PDT 24 4044582247 ps
T827 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2350453730 Jul 29 06:39:49 PM PDT 24 Jul 29 06:40:00 PM PDT 24 4343153026 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1915329925 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:51 PM PDT 24 550476560 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1191675404 Jul 29 06:39:05 PM PDT 24 Jul 29 06:39:06 PM PDT 24 503692240 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3406293429 Jul 29 06:39:55 PM PDT 24 Jul 29 06:39:57 PM PDT 24 689345246 ps
T315 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4165072842 Jul 29 06:38:51 PM PDT 24 Jul 29 06:38:55 PM PDT 24 4378491238 ps
T830 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.630220511 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 346108226 ps
T831 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3833451684 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:51 PM PDT 24 533934029 ps
T832 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1922771734 Jul 29 06:38:50 PM PDT 24 Jul 29 06:38:51 PM PDT 24 473921538 ps
T316 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3889507261 Jul 29 06:39:34 PM PDT 24 Jul 29 06:39:41 PM PDT 24 8751383006 ps
T833 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.892013323 Jul 29 06:40:09 PM PDT 24 Jul 29 06:40:11 PM PDT 24 480389220 ps
T834 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3241013525 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:57 PM PDT 24 5223101912 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2449451815 Jul 29 06:38:50 PM PDT 24 Jul 29 06:40:43 PM PDT 24 27101504486 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3875966170 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:53 PM PDT 24 1257547028 ps
T837 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2153494824 Jul 29 06:39:54 PM PDT 24 Jul 29 06:39:56 PM PDT 24 485879019 ps
T838 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3720958626 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:08 PM PDT 24 8232714600 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2115370123 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:50 PM PDT 24 552210087 ps
T117 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1112787050 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:52 PM PDT 24 436715731 ps
T839 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2890439680 Jul 29 06:40:18 PM PDT 24 Jul 29 06:40:20 PM PDT 24 524920336 ps
T840 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1099835555 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:01 PM PDT 24 446483189 ps
T841 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2247074678 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:53 PM PDT 24 643589073 ps
T842 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.538738426 Jul 29 06:40:08 PM PDT 24 Jul 29 06:40:10 PM PDT 24 287059469 ps
T843 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.389307247 Jul 29 06:39:52 PM PDT 24 Jul 29 06:39:55 PM PDT 24 376255425 ps
T844 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3249429666 Jul 29 06:39:47 PM PDT 24 Jul 29 06:39:49 PM PDT 24 584706397 ps
T845 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2405492812 Jul 29 06:40:27 PM PDT 24 Jul 29 06:40:28 PM PDT 24 471466586 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2604887914 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:02 PM PDT 24 386168571 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2065538478 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:51 PM PDT 24 383014347 ps
T848 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1563176086 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:53 PM PDT 24 472680280 ps
T849 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4286521616 Jul 29 06:39:47 PM PDT 24 Jul 29 06:39:48 PM PDT 24 568437087 ps
T850 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1724060005 Jul 29 06:39:47 PM PDT 24 Jul 29 06:40:01 PM PDT 24 4583512210 ps
T851 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2415783675 Jul 29 06:39:54 PM PDT 24 Jul 29 06:39:56 PM PDT 24 659981690 ps
T118 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1277258891 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:53 PM PDT 24 467985969 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1582668544 Jul 29 06:39:58 PM PDT 24 Jul 29 06:40:17 PM PDT 24 8098650331 ps
T853 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1293528116 Jul 29 06:40:10 PM PDT 24 Jul 29 06:40:11 PM PDT 24 498986818 ps
T854 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1785564232 Jul 29 06:39:05 PM PDT 24 Jul 29 06:39:10 PM PDT 24 4606840102 ps
T855 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4064960180 Jul 29 06:40:27 PM PDT 24 Jul 29 06:40:28 PM PDT 24 499467505 ps
T856 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.501566757 Jul 29 06:40:17 PM PDT 24 Jul 29 06:40:19 PM PDT 24 463395270 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1461975846 Jul 29 06:39:57 PM PDT 24 Jul 29 06:39:58 PM PDT 24 465923115 ps
T858 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.536775400 Jul 29 06:40:27 PM PDT 24 Jul 29 06:40:28 PM PDT 24 447821198 ps
T859 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1029050987 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:52 PM PDT 24 989839298 ps
T860 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4256982768 Jul 29 06:38:48 PM PDT 24 Jul 29 06:40:02 PM PDT 24 53339524011 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2233990332 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:53 PM PDT 24 4894830438 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.399529863 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:49 PM PDT 24 939278753 ps
T863 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1710928791 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:08 PM PDT 24 306306964 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.701426157 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:55 PM PDT 24 4546936489 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1334344690 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:49 PM PDT 24 422650948 ps
T866 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2098437437 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:50 PM PDT 24 1215823806 ps
T867 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3453659621 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:53 PM PDT 24 2558349738 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1045571682 Jul 29 06:38:52 PM PDT 24 Jul 29 06:39:07 PM PDT 24 8554892078 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3195009182 Jul 29 06:38:55 PM PDT 24 Jul 29 06:38:57 PM PDT 24 1359579075 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.346244216 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:02 PM PDT 24 327035928 ps
T871 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4129742024 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 456966585 ps
T872 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1680961072 Jul 29 06:38:52 PM PDT 24 Jul 29 06:39:04 PM PDT 24 2559480610 ps
T873 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.510562830 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:57 PM PDT 24 2275150927 ps
T874 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.709164544 Jul 29 06:40:19 PM PDT 24 Jul 29 06:40:21 PM PDT 24 434583868 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4286531442 Jul 29 06:39:48 PM PDT 24 Jul 29 06:39:50 PM PDT 24 534803117 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.642321120 Jul 29 06:38:50 PM PDT 24 Jul 29 06:38:53 PM PDT 24 1108144999 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2432874183 Jul 29 06:40:09 PM PDT 24 Jul 29 06:40:10 PM PDT 24 341463363 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.743747516 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:54 PM PDT 24 9378002101 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1756584186 Jul 29 06:38:49 PM PDT 24 Jul 29 06:38:50 PM PDT 24 479188293 ps
T880 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3344866929 Jul 29 06:40:10 PM PDT 24 Jul 29 06:40:11 PM PDT 24 363911977 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4070039024 Jul 29 06:38:46 PM PDT 24 Jul 29 06:38:50 PM PDT 24 431586965 ps
T882 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3950061735 Jul 29 06:39:58 PM PDT 24 Jul 29 06:40:09 PM PDT 24 5036859998 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.274192820 Jul 29 06:38:50 PM PDT 24 Jul 29 06:38:52 PM PDT 24 615550700 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2424410603 Jul 29 06:39:09 PM PDT 24 Jul 29 06:39:11 PM PDT 24 480261242 ps
T885 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1982763666 Jul 29 06:39:25 PM PDT 24 Jul 29 06:39:27 PM PDT 24 615509880 ps
T886 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2024731718 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:09 PM PDT 24 319046453 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1980086091 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:52 PM PDT 24 437446716 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.655101345 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:57 PM PDT 24 4336338143 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2492301032 Jul 29 06:39:03 PM PDT 24 Jul 29 06:40:27 PM PDT 24 42103885700 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4292907796 Jul 29 06:38:51 PM PDT 24 Jul 29 06:39:33 PM PDT 24 24679061832 ps
T891 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3147824794 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:01 PM PDT 24 515738939 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1346496350 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:51 PM PDT 24 475319245 ps
T893 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.260215900 Jul 29 06:39:49 PM PDT 24 Jul 29 06:39:50 PM PDT 24 462805784 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1487973194 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:05 PM PDT 24 4487358803 ps
T895 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1778754757 Jul 29 06:39:06 PM PDT 24 Jul 29 06:39:07 PM PDT 24 289607285 ps
T896 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2885051989 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:08 PM PDT 24 345180331 ps
T897 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4283704864 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:48 PM PDT 24 479983852 ps
T898 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.885267188 Jul 29 06:40:07 PM PDT 24 Jul 29 06:40:08 PM PDT 24 651929436 ps
T899 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1108473058 Jul 29 06:39:50 PM PDT 24 Jul 29 06:39:51 PM PDT 24 533069024 ps
T900 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3674977052 Jul 29 06:40:09 PM PDT 24 Jul 29 06:40:11 PM PDT 24 539292025 ps
T901 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2559128000 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:52 PM PDT 24 429720389 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3297436244 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:03 PM PDT 24 2042789880 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3036005621 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:50 PM PDT 24 733381053 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1204361784 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:59 PM PDT 24 8786498892 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3559889521 Jul 29 06:39:09 PM PDT 24 Jul 29 06:39:13 PM PDT 24 4848124621 ps
T905 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.652037696 Jul 29 06:39:41 PM PDT 24 Jul 29 06:39:44 PM PDT 24 4260688667 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1305849043 Jul 29 06:38:48 PM PDT 24 Jul 29 06:38:53 PM PDT 24 3976924880 ps
T907 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.246235672 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:01 PM PDT 24 617682112 ps
T908 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2342062366 Jul 29 06:39:51 PM PDT 24 Jul 29 06:39:52 PM PDT 24 366860241 ps
T909 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3616746829 Jul 29 06:39:52 PM PDT 24 Jul 29 06:39:57 PM PDT 24 4183701370 ps
T910 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1313836132 Jul 29 06:40:25 PM PDT 24 Jul 29 06:40:27 PM PDT 24 499979476 ps
T911 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1694423419 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:03 PM PDT 24 572583328 ps
T912 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2281184829 Jul 29 06:40:01 PM PDT 24 Jul 29 06:40:03 PM PDT 24 667706203 ps
T913 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4244778896 Jul 29 06:39:59 PM PDT 24 Jul 29 06:40:03 PM PDT 24 2507040872 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2466929834 Jul 29 06:38:47 PM PDT 24 Jul 29 06:38:48 PM PDT 24 310342535 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3257027119 Jul 29 06:38:51 PM PDT 24 Jul 29 06:38:52 PM PDT 24 399494161 ps
T916 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4198712269 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:17 PM PDT 24 4492156191 ps
T917 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1195823387 Jul 29 06:39:48 PM PDT 24 Jul 29 06:39:52 PM PDT 24 470169870 ps
T918 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3372524198 Jul 29 06:40:00 PM PDT 24 Jul 29 06:40:02 PM PDT 24 425508983 ps
T919 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3812675025 Jul 29 06:40:18 PM PDT 24 Jul 29 06:40:20 PM PDT 24 503977993 ps

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.296437993
Short name T9
Test name
Test status
Simulation time 70666317832 ps
CPU time 145.91 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:42:36 PM PDT 24
Peak memory 210124 kb
Host smart-ea92d89f-a00d-4d3a-8bbc-13675ba65983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296437993 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.296437993
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3320422836
Short name T27
Test name
Test status
Simulation time 123430399913 ps
CPU time 636.88 seconds
Started Jul 29 05:45:44 PM PDT 24
Finished Jul 29 05:56:21 PM PDT 24
Peak memory 201808 kb
Host smart-f572a8af-2d35-4bfd-bd70-93b4490dba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320422836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3320422836
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.271725531
Short name T12
Test name
Test status
Simulation time 547597755548 ps
CPU time 624.54 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 201452 kb
Host smart-13318d46-7ffa-4b01-83e3-c16d45370de2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271725531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.271725531
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3531300624
Short name T17
Test name
Test status
Simulation time 166522118053 ps
CPU time 246.66 seconds
Started Jul 29 05:45:41 PM PDT 24
Finished Jul 29 05:49:47 PM PDT 24
Peak memory 210376 kb
Host smart-87974a29-8a12-46d9-8dd0-802ff8a9857b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531300624 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3531300624
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.141502458
Short name T124
Test name
Test status
Simulation time 545527252864 ps
CPU time 191.16 seconds
Started Jul 29 05:45:24 PM PDT 24
Finished Jul 29 05:48:35 PM PDT 24
Peak memory 201384 kb
Host smart-27a11799-2a8c-47f3-b955-4f4bd803247b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141502458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.141502458
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3888851238
Short name T39
Test name
Test status
Simulation time 524405117682 ps
CPU time 56.22 seconds
Started Jul 29 05:43:52 PM PDT 24
Finished Jul 29 05:44:48 PM PDT 24
Peak memory 201416 kb
Host smart-4bb8ebd5-2694-4827-bf33-8d9b941dd063
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888851238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3888851238
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3474013429
Short name T70
Test name
Test status
Simulation time 518153511973 ps
CPU time 526.05 seconds
Started Jul 29 05:44:00 PM PDT 24
Finished Jul 29 05:52:46 PM PDT 24
Peak memory 201432 kb
Host smart-ef6c6265-2c7a-4103-88dc-f1b72dfdc740
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474013429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3474013429
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1705810167
Short name T153
Test name
Test status
Simulation time 492070730115 ps
CPU time 718.5 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:52:38 PM PDT 24
Peak memory 201460 kb
Host smart-b0c11ccc-d551-408d-a5d5-b9bb9af57104
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705810167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1705810167
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.524404661
Short name T34
Test name
Test status
Simulation time 373435804801 ps
CPU time 203.68 seconds
Started Jul 29 05:46:39 PM PDT 24
Finished Jul 29 05:50:02 PM PDT 24
Peak memory 209828 kb
Host smart-d6688fba-66f3-4fab-a7f9-22e01ebb4130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524404661 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.524404661
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.35273825
Short name T31
Test name
Test status
Simulation time 604718154155 ps
CPU time 710.21 seconds
Started Jul 29 05:47:33 PM PDT 24
Finished Jul 29 05:59:24 PM PDT 24
Peak memory 201460 kb
Host smart-2be7ddee-326f-4d44-a1c0-f34017ba585b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35273825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_w
akeup.35273825
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1376183646
Short name T178
Test name
Test status
Simulation time 534113474400 ps
CPU time 140.89 seconds
Started Jul 29 05:41:29 PM PDT 24
Finished Jul 29 05:43:50 PM PDT 24
Peak memory 201392 kb
Host smart-d473e876-8135-4e0b-87b1-d30bbdf4861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376183646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1376183646
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1205085381
Short name T52
Test name
Test status
Simulation time 450562252 ps
CPU time 2.85 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 201628 kb
Host smart-3f38cc12-a90a-4ab1-9a4d-9eae678729f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205085381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1205085381
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3825430574
Short name T56
Test name
Test status
Simulation time 4418871933 ps
CPU time 6.17 seconds
Started Jul 29 05:39:54 PM PDT 24
Finished Jul 29 05:40:00 PM PDT 24
Peak memory 217280 kb
Host smart-b2236730-e6fb-49ac-8e12-b6cb5d64d4b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825430574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3825430574
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.768858932
Short name T72
Test name
Test status
Simulation time 570190780122 ps
CPU time 309.98 seconds
Started Jul 29 05:39:51 PM PDT 24
Finished Jul 29 05:45:01 PM PDT 24
Peak memory 201404 kb
Host smart-3c59a61a-0021-4fa6-a063-07a3718530c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768858932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.768858932
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.850854783
Short name T217
Test name
Test status
Simulation time 827542072923 ps
CPU time 599.41 seconds
Started Jul 29 05:46:06 PM PDT 24
Finished Jul 29 05:56:06 PM PDT 24
Peak memory 201376 kb
Host smart-fc86305e-e8d5-444f-bb44-62fa39393d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850854783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
850854783
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2611273258
Short name T155
Test name
Test status
Simulation time 601366980741 ps
CPU time 619.97 seconds
Started Jul 29 05:40:58 PM PDT 24
Finished Jul 29 05:51:18 PM PDT 24
Peak memory 201368 kb
Host smart-89313ff3-2e60-4cf8-98c8-0c930c6607c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611273258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2611273258
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.981443635
Short name T10
Test name
Test status
Simulation time 402779361075 ps
CPU time 912.31 seconds
Started Jul 29 05:46:32 PM PDT 24
Finished Jul 29 06:01:44 PM PDT 24
Peak memory 201460 kb
Host smart-4ecb9709-7e36-47a6-aedb-c3bd992a9404
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981443635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.981443635
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1670159367
Short name T44
Test name
Test status
Simulation time 475410797 ps
CPU time 0.97 seconds
Started Jul 29 06:39:06 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 201368 kb
Host smart-1a1e0aa6-9af8-4ff7-9c6f-5a9839767a9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670159367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1670159367
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.280822279
Short name T150
Test name
Test status
Simulation time 562336963735 ps
CPU time 329.89 seconds
Started Jul 29 05:39:55 PM PDT 24
Finished Jul 29 05:45:25 PM PDT 24
Peak memory 201400 kb
Host smart-b40c888d-120e-4e60-8cdf-f5b54297053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280822279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.280822279
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3667231010
Short name T145
Test name
Test status
Simulation time 554614821913 ps
CPU time 1059.44 seconds
Started Jul 29 05:41:02 PM PDT 24
Finished Jul 29 05:58:42 PM PDT 24
Peak memory 201432 kb
Host smart-00e8a9fe-6c25-4550-8fb6-3231bde42a1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667231010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3667231010
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.212670237
Short name T244
Test name
Test status
Simulation time 510822660967 ps
CPU time 130.47 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:42:18 PM PDT 24
Peak memory 201484 kb
Host smart-da167912-b5f0-465f-9e0a-ae7429acdde2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212670237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.212670237
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.670442420
Short name T274
Test name
Test status
Simulation time 359895979568 ps
CPU time 781.73 seconds
Started Jul 29 05:40:57 PM PDT 24
Finished Jul 29 05:53:59 PM PDT 24
Peak memory 201444 kb
Host smart-16a786fa-d1f1-403b-ba3a-3627bb5ea579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670442420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.670442420
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1515410758
Short name T160
Test name
Test status
Simulation time 508982345435 ps
CPU time 88.48 seconds
Started Jul 29 05:46:03 PM PDT 24
Finished Jul 29 05:47:32 PM PDT 24
Peak memory 201424 kb
Host smart-91996faf-4e3f-43ac-87f2-efa677d9a8d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515410758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1515410758
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1876483246
Short name T251
Test name
Test status
Simulation time 343555180702 ps
CPU time 776.05 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 05:53:30 PM PDT 24
Peak memory 201408 kb
Host smart-df44b201-1b21-48d2-b780-db9f5d545136
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876483246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1876483246
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3715772898
Short name T207
Test name
Test status
Simulation time 609613335107 ps
CPU time 818.86 seconds
Started Jul 29 05:43:18 PM PDT 24
Finished Jul 29 05:56:57 PM PDT 24
Peak memory 201764 kb
Host smart-09d83743-cd6f-47b0-91d0-9fb2bb2ca01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715772898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3715772898
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.914282204
Short name T35
Test name
Test status
Simulation time 235649300848 ps
CPU time 123.32 seconds
Started Jul 29 05:46:45 PM PDT 24
Finished Jul 29 05:48:48 PM PDT 24
Peak memory 218308 kb
Host smart-5fcdd89c-c846-4397-a693-301f0fbd7bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914282204 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.914282204
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4249298829
Short name T28
Test name
Test status
Simulation time 548585946217 ps
CPU time 1324.3 seconds
Started Jul 29 05:40:31 PM PDT 24
Finished Jul 29 06:02:36 PM PDT 24
Peak memory 201404 kb
Host smart-cfd98050-88df-4a9a-a749-bd381a40d5a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249298829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4249298829
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.223030069
Short name T239
Test name
Test status
Simulation time 583595041334 ps
CPU time 178.49 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:43:35 PM PDT 24
Peak memory 201428 kb
Host smart-1e426c38-2496-49ce-a7fe-82c8ad62f0d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223030069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.223030069
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.218659796
Short name T218
Test name
Test status
Simulation time 498716417571 ps
CPU time 326.73 seconds
Started Jul 29 05:40:32 PM PDT 24
Finished Jul 29 05:45:59 PM PDT 24
Peak memory 201436 kb
Host smart-7d576391-89f0-47a9-98c0-e75b2094363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218659796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.218659796
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1919198299
Short name T249
Test name
Test status
Simulation time 488659208082 ps
CPU time 319.25 seconds
Started Jul 29 05:43:24 PM PDT 24
Finished Jul 29 05:48:43 PM PDT 24
Peak memory 201504 kb
Host smart-6925481f-cc62-46ae-9a3c-51a554e8663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919198299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1919198299
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2262478729
Short name T32
Test name
Test status
Simulation time 393292777884 ps
CPU time 205.73 seconds
Started Jul 29 05:45:00 PM PDT 24
Finished Jul 29 05:48:26 PM PDT 24
Peak memory 201444 kb
Host smart-cc52d2e6-4897-4ee2-9642-a90f62fa0b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262478729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2262478729
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3889507261
Short name T316
Test name
Test status
Simulation time 8751383006 ps
CPU time 7.38 seconds
Started Jul 29 06:39:34 PM PDT 24
Finished Jul 29 06:39:41 PM PDT 24
Peak memory 201696 kb
Host smart-8dac2259-3fb3-49e6-8730-b5918f9c4a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889507261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3889507261
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1947361618
Short name T328
Test name
Test status
Simulation time 412911756 ps
CPU time 1.4 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:40:35 PM PDT 24
Peak memory 201232 kb
Host smart-1d366fe7-a6f4-4138-94d4-b7592572db48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947361618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1947361618
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2638802199
Short name T227
Test name
Test status
Simulation time 334598060896 ps
CPU time 216.63 seconds
Started Jul 29 05:43:51 PM PDT 24
Finished Jul 29 05:47:27 PM PDT 24
Peak memory 201400 kb
Host smart-81c13987-573b-4656-90b7-96f2260709be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638802199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2638802199
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.592750969
Short name T171
Test name
Test status
Simulation time 515546124285 ps
CPU time 296.03 seconds
Started Jul 29 05:41:23 PM PDT 24
Finished Jul 29 05:46:19 PM PDT 24
Peak memory 201476 kb
Host smart-d7fe243a-6a5a-4f55-84a8-f8032969ef00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592750969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.592750969
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.240829175
Short name T268
Test name
Test status
Simulation time 502133982773 ps
CPU time 823.3 seconds
Started Jul 29 05:41:55 PM PDT 24
Finished Jul 29 05:55:38 PM PDT 24
Peak memory 201428 kb
Host smart-df9d546d-65f4-4879-815a-46b22da04236
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240829175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.240829175
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4202777923
Short name T283
Test name
Test status
Simulation time 365321241018 ps
CPU time 859.91 seconds
Started Jul 29 05:47:20 PM PDT 24
Finished Jul 29 06:01:40 PM PDT 24
Peak memory 201468 kb
Host smart-3b0db0d8-68c8-4f3b-8090-258d778a221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202777923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4202777923
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2233102413
Short name T75
Test name
Test status
Simulation time 159499842739 ps
CPU time 357.23 seconds
Started Jul 29 05:42:54 PM PDT 24
Finished Jul 29 05:48:52 PM PDT 24
Peak memory 201436 kb
Host smart-552704d0-5f12-4a4a-8e6d-498beb929503
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233102413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2233102413
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3081947465
Short name T139
Test name
Test status
Simulation time 498650132914 ps
CPU time 1133.29 seconds
Started Jul 29 05:44:43 PM PDT 24
Finished Jul 29 06:03:37 PM PDT 24
Peak memory 201436 kb
Host smart-1d05e559-0099-456f-9c00-47a79a81a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081947465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3081947465
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2440434848
Short name T69
Test name
Test status
Simulation time 554415010691 ps
CPU time 137.73 seconds
Started Jul 29 05:42:18 PM PDT 24
Finished Jul 29 05:44:36 PM PDT 24
Peak memory 201452 kb
Host smart-96261757-da45-419a-83ea-f704ecd4a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440434848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2440434848
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1601514306
Short name T222
Test name
Test status
Simulation time 460060772152 ps
CPU time 111.38 seconds
Started Jul 29 05:46:34 PM PDT 24
Finished Jul 29 05:48:25 PM PDT 24
Peak memory 201420 kb
Host smart-a8d2a3cb-7b51-4a1a-affb-7c77a7fe71cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601514306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1601514306
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1142866913
Short name T210
Test name
Test status
Simulation time 304423522015 ps
CPU time 1091.67 seconds
Started Jul 29 05:46:51 PM PDT 24
Finished Jul 29 06:05:02 PM PDT 24
Peak memory 201816 kb
Host smart-62f9ce60-42d0-4e07-a825-e9a33006dae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142866913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1142866913
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.122837968
Short name T23
Test name
Test status
Simulation time 168494186709 ps
CPU time 178.93 seconds
Started Jul 29 05:46:53 PM PDT 24
Finished Jul 29 05:49:52 PM PDT 24
Peak memory 201520 kb
Host smart-b47e2427-9b60-4d52-ba2f-f03330571f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122837968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.122837968
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2946833681
Short name T248
Test name
Test status
Simulation time 557718003079 ps
CPU time 1239.11 seconds
Started Jul 29 05:45:37 PM PDT 24
Finished Jul 29 06:06:17 PM PDT 24
Peak memory 201452 kb
Host smart-9b560b6a-017a-4585-aa5d-0b40954cadbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946833681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2946833681
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3298991692
Short name T167
Test name
Test status
Simulation time 525718293557 ps
CPU time 106.99 seconds
Started Jul 29 05:47:14 PM PDT 24
Finished Jul 29 05:49:02 PM PDT 24
Peak memory 201448 kb
Host smart-3db7b61a-c905-4a31-91ff-59a1d392c4cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298991692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3298991692
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2764758421
Short name T300
Test name
Test status
Simulation time 363280362819 ps
CPU time 63.09 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:40:55 PM PDT 24
Peak memory 201540 kb
Host smart-7efa668f-7b20-418a-859d-f3751f2154ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764758421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2764758421
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1692982753
Short name T157
Test name
Test status
Simulation time 542943068013 ps
CPU time 189.96 seconds
Started Jul 29 05:42:27 PM PDT 24
Finished Jul 29 05:45:37 PM PDT 24
Peak memory 201372 kb
Host smart-8e8fc5c2-f539-45ea-88a2-ef52c0346e96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692982753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1692982753
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.932606680
Short name T215
Test name
Test status
Simulation time 353127868053 ps
CPU time 137.74 seconds
Started Jul 29 05:40:15 PM PDT 24
Finished Jul 29 05:42:33 PM PDT 24
Peak memory 201392 kb
Host smart-9e70767e-1010-4471-8557-800dd1f7f15c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932606680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.932606680
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3406293429
Short name T829
Test name
Test status
Simulation time 689345246 ps
CPU time 2.53 seconds
Started Jul 29 06:39:55 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 217892 kb
Host smart-fe7dd011-7c52-4a17-92ad-42a413b6005e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406293429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3406293429
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.22977214
Short name T26
Test name
Test status
Simulation time 487464439502 ps
CPU time 1156.52 seconds
Started Jul 29 05:41:07 PM PDT 24
Finished Jul 29 06:00:24 PM PDT 24
Peak memory 201440 kb
Host smart-8558fc0d-c015-405d-a076-d6812d400121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22977214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.22977214
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.647304290
Short name T212
Test name
Test status
Simulation time 370387167955 ps
CPU time 759.48 seconds
Started Jul 29 05:42:45 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 201496 kb
Host smart-7a41d525-4ded-4fa9-9c6f-c0200ac299d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647304290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.647304290
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.891064804
Short name T295
Test name
Test status
Simulation time 516729187255 ps
CPU time 480.75 seconds
Started Jul 29 05:42:56 PM PDT 24
Finished Jul 29 05:50:56 PM PDT 24
Peak memory 201444 kb
Host smart-a14c479b-6684-4783-bebb-2fd94fa1fcb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891064804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.891064804
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2007414570
Short name T297
Test name
Test status
Simulation time 160899788818 ps
CPU time 183.29 seconds
Started Jul 29 05:45:49 PM PDT 24
Finished Jul 29 05:48:52 PM PDT 24
Peak memory 201388 kb
Host smart-e20ab373-43ba-45d6-af8d-527cbe94d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007414570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2007414570
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.475062506
Short name T279
Test name
Test status
Simulation time 608461053436 ps
CPU time 1099.45 seconds
Started Jul 29 05:46:16 PM PDT 24
Finished Jul 29 06:04:35 PM PDT 24
Peak memory 201424 kb
Host smart-2adf6d1b-a7d3-4e2f-b124-d0ae782781a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475062506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.475062506
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3256008239
Short name T254
Test name
Test status
Simulation time 508359487590 ps
CPU time 1064.36 seconds
Started Jul 29 05:40:24 PM PDT 24
Finished Jul 29 05:58:09 PM PDT 24
Peak memory 201404 kb
Host smart-e9e9bad9-d1f1-4222-95c9-09aa90d82a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256008239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3256008239
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1727534810
Short name T287
Test name
Test status
Simulation time 679962621851 ps
CPU time 273.94 seconds
Started Jul 29 05:40:32 PM PDT 24
Finished Jul 29 05:45:06 PM PDT 24
Peak memory 210108 kb
Host smart-dd7e100f-cf82-479d-8ff3-3227eb0bf92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727534810 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1727534810
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.516445421
Short name T425
Test name
Test status
Simulation time 66206275142 ps
CPU time 224.87 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:45:13 PM PDT 24
Peak memory 201916 kb
Host smart-d3bd7001-d0c1-4531-82e1-85111082d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516445421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.516445421
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2518693235
Short name T156
Test name
Test status
Simulation time 483582858893 ps
CPU time 577.1 seconds
Started Jul 29 05:43:50 PM PDT 24
Finished Jul 29 05:53:28 PM PDT 24
Peak memory 201596 kb
Host smart-300be506-3c2a-4fec-9d8b-bc47a63ec3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518693235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2518693235
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1791978109
Short name T252
Test name
Test status
Simulation time 583596889575 ps
CPU time 1338.87 seconds
Started Jul 29 05:46:03 PM PDT 24
Finished Jul 29 06:08:22 PM PDT 24
Peak memory 201476 kb
Host smart-7b03059c-405e-4be8-925c-c17134ae1f0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791978109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1791978109
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.951482537
Short name T260
Test name
Test status
Simulation time 98792698357 ps
CPU time 189.53 seconds
Started Jul 29 05:46:07 PM PDT 24
Finished Jul 29 05:49:16 PM PDT 24
Peak memory 209664 kb
Host smart-b08e0130-fe8e-4a31-aa5d-3d01f29a97de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951482537 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.951482537
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1695083523
Short name T232
Test name
Test status
Simulation time 370600812825 ps
CPU time 433.98 seconds
Started Jul 29 05:46:40 PM PDT 24
Finished Jul 29 05:53:54 PM PDT 24
Peak memory 201384 kb
Host smart-4d7e7aec-0999-4188-b864-a685c12cff28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695083523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1695083523
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.540564438
Short name T314
Test name
Test status
Simulation time 516617474813 ps
CPU time 1095.37 seconds
Started Jul 29 05:46:54 PM PDT 24
Finished Jul 29 06:05:10 PM PDT 24
Peak memory 201388 kb
Host smart-2be31e87-21a3-47d5-a3e3-f08adca121e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540564438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.540564438
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.502993336
Short name T143
Test name
Test status
Simulation time 550830531422 ps
CPU time 1318.67 seconds
Started Jul 29 05:47:16 PM PDT 24
Finished Jul 29 06:09:15 PM PDT 24
Peak memory 201472 kb
Host smart-caf488a1-fdec-4e8a-96d4-608cad73521b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502993336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.502993336
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2282209074
Short name T233
Test name
Test status
Simulation time 441388101652 ps
CPU time 472.08 seconds
Started Jul 29 05:47:32 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 201384 kb
Host smart-cdef4e77-268d-4a0e-8430-cf8ef37dbfc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282209074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2282209074
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3371681286
Short name T192
Test name
Test status
Simulation time 437799916620 ps
CPU time 1405.7 seconds
Started Jul 29 05:47:44 PM PDT 24
Finished Jul 29 06:11:10 PM PDT 24
Peak memory 210080 kb
Host smart-e87f7628-5847-471d-9e92-fbe1bfd5d402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371681286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3371681286
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2868088825
Short name T220
Test name
Test status
Simulation time 163202360074 ps
CPU time 202.21 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:43:46 PM PDT 24
Peak memory 201452 kb
Host smart-0e9f0ada-0f86-407b-8c71-b4acc4c7e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868088825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2868088825
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.119584862
Short name T213
Test name
Test status
Simulation time 334657573602 ps
CPU time 201.04 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:43:19 PM PDT 24
Peak memory 201404 kb
Host smart-da6db9f5-7c74-4a3c-964a-28bb62203ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119584862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.119584862
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1802399998
Short name T238
Test name
Test status
Simulation time 528102491801 ps
CPU time 1183.84 seconds
Started Jul 29 05:44:00 PM PDT 24
Finished Jul 29 06:03:44 PM PDT 24
Peak memory 201516 kb
Host smart-cd457dbe-6087-4bce-bd3c-33f02aa5d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802399998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1802399998
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.133171242
Short name T782
Test name
Test status
Simulation time 102203669695 ps
CPU time 285.26 seconds
Started Jul 29 05:46:21 PM PDT 24
Finished Jul 29 05:51:07 PM PDT 24
Peak memory 201844 kb
Host smart-ac46d406-229c-4b2c-a13a-f2810852c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133171242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.133171242
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1346560443
Short name T214
Test name
Test status
Simulation time 489340088860 ps
CPU time 1074.42 seconds
Started Jul 29 05:47:24 PM PDT 24
Finished Jul 29 06:05:19 PM PDT 24
Peak memory 201448 kb
Host smart-420763ef-3569-428c-9fc5-84bb64ad2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346560443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1346560443
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3703188747
Short name T298
Test name
Test status
Simulation time 197589425036 ps
CPU time 104.05 seconds
Started Jul 29 05:40:13 PM PDT 24
Finished Jul 29 05:41:57 PM PDT 24
Peak memory 201480 kb
Host smart-0b0fbe1c-d18c-4239-99a2-530518726a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703188747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3703188747
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1204361784
Short name T66
Test name
Test status
Simulation time 8786498892 ps
CPU time 7.4 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:59 PM PDT 24
Peak memory 201640 kb
Host smart-dbdb7442-3924-4296-9cfb-8821f87002a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204361784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1204361784
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1306351570
Short name T42
Test name
Test status
Simulation time 136157389036 ps
CPU time 455.95 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:48:09 PM PDT 24
Peak memory 201764 kb
Host smart-fa196b3f-4a6e-4cb3-bdae-7f67803afe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306351570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1306351570
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3181821930
Short name T187
Test name
Test status
Simulation time 127779338671 ps
CPU time 378.35 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:46:54 PM PDT 24
Peak memory 201744 kb
Host smart-cbc24b0a-65f3-4202-82cd-38a2e51ba38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181821930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3181821930
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1300126854
Short name T158
Test name
Test status
Simulation time 571166206876 ps
CPU time 312.66 seconds
Started Jul 29 05:40:54 PM PDT 24
Finished Jul 29 05:46:07 PM PDT 24
Peak memory 201412 kb
Host smart-6bb0cda0-9afa-4c95-9966-13a91565e6e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300126854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1300126854
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3457994960
Short name T257
Test name
Test status
Simulation time 341200557742 ps
CPU time 796 seconds
Started Jul 29 05:41:38 PM PDT 24
Finished Jul 29 05:54:54 PM PDT 24
Peak memory 201476 kb
Host smart-bb1c08b2-b8e8-4340-aca7-a904655d4c3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457994960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3457994960
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.806405449
Short name T76
Test name
Test status
Simulation time 167580818033 ps
CPU time 56.04 seconds
Started Jul 29 05:42:30 PM PDT 24
Finished Jul 29 05:43:26 PM PDT 24
Peak memory 201424 kb
Host smart-97be784a-fe48-48f7-ae2b-728e801603e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806405449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.806405449
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2260232549
Short name T83
Test name
Test status
Simulation time 165602211099 ps
CPU time 361.01 seconds
Started Jul 29 05:43:12 PM PDT 24
Finished Jul 29 05:49:13 PM PDT 24
Peak memory 201468 kb
Host smart-a123ad5b-2bc9-478c-bed4-e902406de511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260232549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2260232549
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1220727945
Short name T256
Test name
Test status
Simulation time 533953999279 ps
CPU time 591.78 seconds
Started Jul 29 05:44:34 PM PDT 24
Finished Jul 29 05:54:26 PM PDT 24
Peak memory 201484 kb
Host smart-e1dd50a2-f592-4679-b575-4a7440a6b01a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220727945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1220727945
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3346086680
Short name T271
Test name
Test status
Simulation time 173727031842 ps
CPU time 66.77 seconds
Started Jul 29 05:44:52 PM PDT 24
Finished Jul 29 05:45:59 PM PDT 24
Peak memory 201456 kb
Host smart-99e4d798-ba5b-4ace-b588-76b53423f824
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346086680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3346086680
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3893517111
Short name T263
Test name
Test status
Simulation time 371093882916 ps
CPU time 212.39 seconds
Started Jul 29 05:47:15 PM PDT 24
Finished Jul 29 05:50:48 PM PDT 24
Peak memory 201400 kb
Host smart-c8feba6f-ce0e-4eb8-90c8-7f057eac3e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893517111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3893517111
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.963981952
Short name T241
Test name
Test status
Simulation time 346023213118 ps
CPU time 766.73 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:53:10 PM PDT 24
Peak memory 201436 kb
Host smart-602dc36d-0964-411c-8098-116ef103a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963981952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.963981952
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1474112709
Short name T114
Test name
Test status
Simulation time 862619210 ps
CPU time 3.15 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201572 kb
Host smart-7691e1a0-9b6c-49b2-b944-dc6d6fa711cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474112709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1474112709
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4256982768
Short name T860
Test name
Test status
Simulation time 53339524011 ps
CPU time 74.12 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:40:02 PM PDT 24
Peak memory 201580 kb
Host smart-111824b8-5c46-47ae-8685-bce744e49ea5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256982768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4256982768
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4107876301
Short name T111
Test name
Test status
Simulation time 887546504 ps
CPU time 2.62 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201384 kb
Host smart-d687517d-f9f3-4e51-a5cc-4969c4b8a9bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107876301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4107876301
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2431533742
Short name T79
Test name
Test status
Simulation time 564828682 ps
CPU time 2.15 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201456 kb
Host smart-a0c276ce-8afe-434b-a7f6-584619e0e3f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431533742 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2431533742
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4014987200
Short name T825
Test name
Test status
Simulation time 526839539 ps
CPU time 1.12 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:48 PM PDT 24
Peak memory 201336 kb
Host smart-aede2e83-4681-4aba-af64-a45d5dc0d966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014987200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4014987200
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2466929834
Short name T914
Test name
Test status
Simulation time 310342535 ps
CPU time 1.05 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:48 PM PDT 24
Peak memory 201512 kb
Host smart-5d7e6212-3e5c-46ac-8bb1-955968d03904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466929834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2466929834
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1305849043
Short name T906
Test name
Test status
Simulation time 3976924880 ps
CPU time 5.53 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:53 PM PDT 24
Peak memory 201564 kb
Host smart-9321a215-10c4-43e3-8dd4-f6146f08c6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305849043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1305849043
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4070039024
Short name T881
Test name
Test status
Simulation time 431586965 ps
CPU time 3.53 seconds
Started Jul 29 06:38:46 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201648 kb
Host smart-f7896ad2-621f-4494-a241-da6774c4b5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070039024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4070039024
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1535113758
Short name T50
Test name
Test status
Simulation time 4648980861 ps
CPU time 3.46 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:51 PM PDT 24
Peak memory 201680 kb
Host smart-2c581b53-f8df-4b93-8d5e-036d220106c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535113758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1535113758
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.399529863
Short name T862
Test name
Test status
Simulation time 939278753 ps
CPU time 1.9 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:49 PM PDT 24
Peak memory 201480 kb
Host smart-a52a3851-9f33-4268-b5d4-65bfbc6d2b78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399529863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.399529863
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1768785776
Short name T815
Test name
Test status
Simulation time 25853491541 ps
CPU time 18.05 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 201620 kb
Host smart-92976b1e-64f2-4c75-8f8b-f85e4927a7ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768785776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1768785776
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2098437437
Short name T866
Test name
Test status
Simulation time 1215823806 ps
CPU time 1.43 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201372 kb
Host smart-cfdc4f74-ddad-405c-a84b-99cbea972852
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098437437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2098437437
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3234797345
Short name T818
Test name
Test status
Simulation time 528229565 ps
CPU time 1.02 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201452 kb
Host smart-6923bd5d-7da2-45c2-888d-0148747f0c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234797345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3234797345
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1334344690
Short name T865
Test name
Test status
Simulation time 422650948 ps
CPU time 0.95 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:49 PM PDT 24
Peak memory 201368 kb
Host smart-b077ad3d-6a5f-4409-9e42-dbe8bda2ac31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334344690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1334344690
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4283704864
Short name T897
Test name
Test status
Simulation time 479983852 ps
CPU time 0.73 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:48 PM PDT 24
Peak memory 201376 kb
Host smart-49db80b6-dfe4-4d31-960f-4d018d464bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283704864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4283704864
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3241013525
Short name T834
Test name
Test status
Simulation time 5223101912 ps
CPU time 9.2 seconds
Started Jul 29 06:38:47 PM PDT 24
Finished Jul 29 06:38:57 PM PDT 24
Peak memory 201592 kb
Host smart-bf6bd58f-dcdc-426f-ad0a-7b4b45465dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241013525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3241013525
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3036005621
Short name T903
Test name
Test status
Simulation time 733381053 ps
CPU time 1.56 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201800 kb
Host smart-c82aa270-3338-45e6-a3d1-a0e88bd03178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036005621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3036005621
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.701426157
Short name T864
Test name
Test status
Simulation time 4546936489 ps
CPU time 7.34 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:55 PM PDT 24
Peak memory 201604 kb
Host smart-f781c199-eddc-4020-846b-391742ec1231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701426157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.701426157
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2559128000
Short name T901
Test name
Test status
Simulation time 429720389 ps
CPU time 1.24 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 201504 kb
Host smart-a84e4ef1-89a6-4485-9c99-d704d9a8566b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559128000 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2559128000
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.260215900
Short name T893
Test name
Test status
Simulation time 462805784 ps
CPU time 1.29 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:50 PM PDT 24
Peak memory 201372 kb
Host smart-9474b822-01f8-4f91-b8b7-80554a08351b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260215900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.260215900
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.363061276
Short name T813
Test name
Test status
Simulation time 545731343 ps
CPU time 0.91 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201368 kb
Host smart-ad873167-3122-4e7e-bdc2-b5c2f7e40262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363061276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.363061276
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.510562830
Short name T873
Test name
Test status
Simulation time 2275150927 ps
CPU time 7.56 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 201452 kb
Host smart-f8860082-3fb2-48bc-8fec-601ca936f17c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510562830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.510562830
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1195823387
Short name T917
Test name
Test status
Simulation time 470169870 ps
CPU time 3.27 seconds
Started Jul 29 06:39:48 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 210844 kb
Host smart-18184231-7e58-4a71-94bc-2029d9bb2d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195823387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1195823387
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.743747516
Short name T878
Test name
Test status
Simulation time 9378002101 ps
CPU time 4.39 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:54 PM PDT 24
Peak memory 201644 kb
Host smart-26b5cbc6-3441-404d-b4e0-661e4d78a339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743747516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.743747516
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1563176086
Short name T848
Test name
Test status
Simulation time 472680280 ps
CPU time 2.06 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201496 kb
Host smart-96bbe78b-ff98-4e1b-a771-55704166ece6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563176086 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1563176086
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2342062366
Short name T908
Test name
Test status
Simulation time 366860241 ps
CPU time 0.93 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 201360 kb
Host smart-f8d8686b-bfd3-4acd-b034-a758c91493a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342062366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2342062366
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1108473058
Short name T899
Test name
Test status
Simulation time 533069024 ps
CPU time 0.94 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201328 kb
Host smart-c42137b5-2abf-4241-8bae-c8039407e2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108473058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1108473058
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3584095783
Short name T47
Test name
Test status
Simulation time 4293415197 ps
CPU time 9.96 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:40:02 PM PDT 24
Peak memory 201560 kb
Host smart-0737ff6b-8d4f-4fc2-8bd9-742d35920f5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584095783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3584095783
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3616746829
Short name T909
Test name
Test status
Simulation time 4183701370 ps
CPU time 4.47 seconds
Started Jul 29 06:39:52 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 201680 kb
Host smart-db70849e-5d26-490c-9530-33a86a34d237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616746829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3616746829
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2247074678
Short name T841
Test name
Test status
Simulation time 643589073 ps
CPU time 1.17 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201520 kb
Host smart-a63a9abd-0e76-4207-85ac-e4111c504946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247074678 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2247074678
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2153494824
Short name T837
Test name
Test status
Simulation time 485879019 ps
CPU time 1.2 seconds
Started Jul 29 06:39:54 PM PDT 24
Finished Jul 29 06:39:56 PM PDT 24
Peak memory 201368 kb
Host smart-d83808da-1fab-45b5-a929-d9a2b853bbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153494824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2153494824
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1980086091
Short name T887
Test name
Test status
Simulation time 437446716 ps
CPU time 0.82 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 201328 kb
Host smart-f41aa580-9402-4329-b4bd-117945e3d271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980086091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1980086091
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1916324791
Short name T45
Test name
Test status
Simulation time 3832444234 ps
CPU time 3.14 seconds
Started Jul 29 06:39:54 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 201632 kb
Host smart-1670902f-7cb7-4aee-a587-2d0c9646dfd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916324791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1916324791
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3875966170
Short name T836
Test name
Test status
Simulation time 1257547028 ps
CPU time 2.65 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201596 kb
Host smart-57f6e598-959d-42ff-8a25-4742af43fdb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875966170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3875966170
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3833451684
Short name T831
Test name
Test status
Simulation time 533934029 ps
CPU time 1.19 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201468 kb
Host smart-a32a630b-b84e-4304-8b8d-8fc18aeb271f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833451684 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3833451684
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1277258891
Short name T118
Test name
Test status
Simulation time 467985969 ps
CPU time 1.99 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201300 kb
Host smart-204f0c64-fad0-4f0b-95fd-48198dd0338b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277258891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1277258891
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1091779895
Short name T810
Test name
Test status
Simulation time 401043486 ps
CPU time 1.5 seconds
Started Jul 29 06:39:54 PM PDT 24
Finished Jul 29 06:39:56 PM PDT 24
Peak memory 201360 kb
Host smart-ec521fa9-4a63-433b-9472-d1adf8eb819b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091779895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1091779895
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.374236825
Short name T120
Test name
Test status
Simulation time 4430080445 ps
CPU time 8.86 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:58 PM PDT 24
Peak memory 201600 kb
Host smart-ce2f6227-8e4f-4f0f-be77-8a173cdb4153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374236825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.374236825
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2415783675
Short name T851
Test name
Test status
Simulation time 659981690 ps
CPU time 1.62 seconds
Started Jul 29 06:39:54 PM PDT 24
Finished Jul 29 06:39:56 PM PDT 24
Peak memory 201696 kb
Host smart-14d49c59-bd7b-4bfa-ac76-c2d03dd8d349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415783675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2415783675
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.655101345
Short name T888
Test name
Test status
Simulation time 4336338143 ps
CPU time 5.76 seconds
Started Jul 29 06:39:51 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 201648 kb
Host smart-62810cc8-f24f-4f0c-ad4d-099340821b80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655101345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.655101345
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4129742024
Short name T871
Test name
Test status
Simulation time 456966585 ps
CPU time 1.78 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201516 kb
Host smart-6f14bda9-1386-4da9-a3b5-da4dae28bc3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129742024 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4129742024
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1238298000
Short name T108
Test name
Test status
Simulation time 477429914 ps
CPU time 0.91 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201372 kb
Host smart-9d2bc3f7-282e-4b97-b0d9-eca2c5a2691e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238298000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1238298000
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.246235672
Short name T907
Test name
Test status
Simulation time 617682112 ps
CPU time 0.75 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201388 kb
Host smart-586c95fa-bf0f-48e4-a301-e5e9e896c028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246235672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.246235672
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3950061735
Short name T882
Test name
Test status
Simulation time 5036859998 ps
CPU time 11.64 seconds
Started Jul 29 06:39:58 PM PDT 24
Finished Jul 29 06:40:09 PM PDT 24
Peak memory 201576 kb
Host smart-4bf1b708-ebc4-4c7b-85ef-c352a1bf6e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950061735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3950061735
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.389307247
Short name T843
Test name
Test status
Simulation time 376255425 ps
CPU time 2.59 seconds
Started Jul 29 06:39:52 PM PDT 24
Finished Jul 29 06:39:55 PM PDT 24
Peak memory 201644 kb
Host smart-a36c9b62-8d33-4772-a51c-2aacfd22760b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389307247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.389307247
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.652037696
Short name T905
Test name
Test status
Simulation time 4260688667 ps
CPU time 2.73 seconds
Started Jul 29 06:39:41 PM PDT 24
Finished Jul 29 06:39:44 PM PDT 24
Peak memory 201596 kb
Host smart-1baa9e82-4b0d-43ec-9374-f686d879363f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652037696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.652037696
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3147824794
Short name T891
Test name
Test status
Simulation time 515738939 ps
CPU time 2.2 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201468 kb
Host smart-052267ca-9b17-4983-9cce-9cd5d6480cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147824794 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3147824794
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3600206586
Short name T113
Test name
Test status
Simulation time 503916329 ps
CPU time 1.77 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201344 kb
Host smart-63e298e4-3d3d-4378-830d-1c6c268203df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600206586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3600206586
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.630220511
Short name T830
Test name
Test status
Simulation time 346108226 ps
CPU time 1.17 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201372 kb
Host smart-c061bd7f-9b8c-483e-bcda-1a22337387bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630220511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.630220511
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3297436244
Short name T902
Test name
Test status
Simulation time 2042789880 ps
CPU time 2.08 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 201524 kb
Host smart-d35223c9-70de-451e-9057-7ddf735d001b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297436244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3297436244
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3525629285
Short name T51
Test name
Test status
Simulation time 595247970 ps
CPU time 1.81 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201668 kb
Host smart-ffd1cf61-6477-4f3b-985d-08549cdc2677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525629285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3525629285
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1487973194
Short name T894
Test name
Test status
Simulation time 4487358803 ps
CPU time 6.63 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:05 PM PDT 24
Peak memory 201532 kb
Host smart-6472af1b-bb90-4eef-b49c-9219f6075257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487973194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1487973194
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2604887914
Short name T846
Test name
Test status
Simulation time 386168571 ps
CPU time 1.64 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:02 PM PDT 24
Peak memory 201472 kb
Host smart-ca9dc8db-e980-4a12-9206-c5b03da9d7fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604887914 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2604887914
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3372524198
Short name T918
Test name
Test status
Simulation time 425508983 ps
CPU time 1.17 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:02 PM PDT 24
Peak memory 201364 kb
Host smart-ca08e71b-a62b-4e76-a5fa-bfce3f30c962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372524198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3372524198
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1099835555
Short name T840
Test name
Test status
Simulation time 446483189 ps
CPU time 0.88 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201284 kb
Host smart-101d41a3-c433-49f1-ade2-7a77c757bfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099835555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1099835555
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.442272585
Short name T121
Test name
Test status
Simulation time 1893296906 ps
CPU time 2 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 201524 kb
Host smart-0b63afad-2554-4935-aa20-9889cd0bb7a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442272585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.442272585
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2281184829
Short name T912
Test name
Test status
Simulation time 667706203 ps
CPU time 2.52 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 201580 kb
Host smart-eab0319b-07fc-49d3-9df8-29d0f092b50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281184829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2281184829
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.861997023
Short name T826
Test name
Test status
Simulation time 4044582247 ps
CPU time 5.72 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:07 PM PDT 24
Peak memory 201636 kb
Host smart-bdf9a65a-74d3-4c1e-90e1-b59b92cb29a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861997023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.861997023
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3705777592
Short name T64
Test name
Test status
Simulation time 488720435 ps
CPU time 1.3 seconds
Started Jul 29 06:39:57 PM PDT 24
Finished Jul 29 06:39:58 PM PDT 24
Peak memory 201500 kb
Host smart-d4cd0a42-4e1d-4f0b-bbbe-c3eb2ff02ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705777592 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3705777592
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2212387590
Short name T821
Test name
Test status
Simulation time 545550090 ps
CPU time 1.99 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201408 kb
Host smart-97389f1d-897f-44a0-a0c5-9372395c1255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212387590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2212387590
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.346244216
Short name T870
Test name
Test status
Simulation time 327035928 ps
CPU time 1.04 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:02 PM PDT 24
Peak memory 201388 kb
Host smart-913f1af1-691c-4685-9da0-ac23d0230b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346244216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.346244216
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4198712269
Short name T916
Test name
Test status
Simulation time 4492156191 ps
CPU time 16.99 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:17 PM PDT 24
Peak memory 201616 kb
Host smart-d71194f6-3bc9-4058-8161-50144480182d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198712269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4198712269
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1694423419
Short name T911
Test name
Test status
Simulation time 572583328 ps
CPU time 3.38 seconds
Started Jul 29 06:40:00 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 209876 kb
Host smart-6533b723-244b-43a4-a1cb-32ab4406c1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694423419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1694423419
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3720958626
Short name T838
Test name
Test status
Simulation time 8232714600 ps
CPU time 6.84 seconds
Started Jul 29 06:40:01 PM PDT 24
Finished Jul 29 06:40:08 PM PDT 24
Peak memory 201704 kb
Host smart-601e1a87-b9af-4e6f-b58f-7080858c86eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720958626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3720958626
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2376432787
Short name T824
Test name
Test status
Simulation time 510081189 ps
CPU time 2.02 seconds
Started Jul 29 06:39:55 PM PDT 24
Finished Jul 29 06:39:58 PM PDT 24
Peak memory 201520 kb
Host smart-7dc59d56-4ae3-4277-9f5c-9f520cf85c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376432787 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2376432787
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2842903878
Short name T46
Test name
Test status
Simulation time 446387277 ps
CPU time 1.85 seconds
Started Jul 29 06:39:55 PM PDT 24
Finished Jul 29 06:39:57 PM PDT 24
Peak memory 201300 kb
Host smart-ac5d8a3a-e80f-428d-a40f-a470f3a050ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842903878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2842903878
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2127008999
Short name T819
Test name
Test status
Simulation time 410219315 ps
CPU time 1.09 seconds
Started Jul 29 06:39:57 PM PDT 24
Finished Jul 29 06:39:58 PM PDT 24
Peak memory 201352 kb
Host smart-a97296c5-2acc-444b-a837-1cc954a0630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127008999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2127008999
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4244778896
Short name T913
Test name
Test status
Simulation time 2507040872 ps
CPU time 3.74 seconds
Started Jul 29 06:39:59 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 201280 kb
Host smart-0c419a10-79ea-4090-86b9-6d90c2c8e948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244778896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4244778896
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1582668544
Short name T852
Test name
Test status
Simulation time 8098650331 ps
CPU time 19.75 seconds
Started Jul 29 06:39:58 PM PDT 24
Finished Jul 29 06:40:17 PM PDT 24
Peak memory 201624 kb
Host smart-d86b7b87-54a4-4e2f-9ac7-931b5abbe4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582668544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1582668544
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.885267188
Short name T898
Test name
Test status
Simulation time 651929436 ps
CPU time 1.1 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:08 PM PDT 24
Peak memory 201468 kb
Host smart-b2b8570b-d377-4194-b515-90bc3852b733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885267188 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.885267188
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2432874183
Short name T877
Test name
Test status
Simulation time 341463363 ps
CPU time 1.55 seconds
Started Jul 29 06:40:09 PM PDT 24
Finished Jul 29 06:40:10 PM PDT 24
Peak memory 201336 kb
Host smart-4a30a383-c5dd-4cd0-b1f0-67a7ce782b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432874183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2432874183
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1710928791
Short name T863
Test name
Test status
Simulation time 306306964 ps
CPU time 0.85 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:08 PM PDT 24
Peak memory 201348 kb
Host smart-704d40e3-f69f-4493-9e4f-661948872995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710928791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1710928791
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4281116849
Short name T119
Test name
Test status
Simulation time 2810702253 ps
CPU time 6.46 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:13 PM PDT 24
Peak memory 201520 kb
Host smart-6a73e2bc-e081-4fce-b163-191540ba74b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281116849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4281116849
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1461975846
Short name T857
Test name
Test status
Simulation time 465923115 ps
CPU time 1.4 seconds
Started Jul 29 06:39:57 PM PDT 24
Finished Jul 29 06:39:58 PM PDT 24
Peak memory 201628 kb
Host smart-41f6d50c-765a-4c06-b3b0-89c2e1b2c240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461975846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1461975846
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1366003715
Short name T54
Test name
Test status
Simulation time 4390344351 ps
CPU time 6.75 seconds
Started Jul 29 06:39:56 PM PDT 24
Finished Jul 29 06:40:03 PM PDT 24
Peak memory 201668 kb
Host smart-85fcd803-0e2b-45c3-928e-3c9c6f8ccbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366003715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1366003715
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1029050987
Short name T859
Test name
Test status
Simulation time 989839298 ps
CPU time 2.19 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:52 PM PDT 24
Peak memory 201496 kb
Host smart-2ebd13b5-7fbf-46f7-871b-d17eab393bcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029050987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1029050987
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2449451815
Short name T835
Test name
Test status
Simulation time 27101504486 ps
CPU time 112.9 seconds
Started Jul 29 06:38:50 PM PDT 24
Finished Jul 29 06:40:43 PM PDT 24
Peak memory 201544 kb
Host smart-fb7f5055-43fb-4392-9ad4-ba71b5be1668
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449451815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2449451815
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.978267025
Short name T807
Test name
Test status
Simulation time 768745893 ps
CPU time 2.44 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:52 PM PDT 24
Peak memory 201360 kb
Host smart-9e4663e6-b4c8-4192-b05f-c84d305ea7bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978267025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.978267025
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4176900129
Short name T814
Test name
Test status
Simulation time 519458563 ps
CPU time 1.16 seconds
Started Jul 29 06:38:48 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201480 kb
Host smart-e31d7b48-5c35-47af-95b1-b0965f6e4381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176900129 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4176900129
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1756584186
Short name T879
Test name
Test status
Simulation time 479188293 ps
CPU time 1.35 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201312 kb
Host smart-6a4552e1-1fa5-4552-8535-fb813c8ad650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756584186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1756584186
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1922771734
Short name T832
Test name
Test status
Simulation time 473921538 ps
CPU time 0.75 seconds
Started Jul 29 06:38:50 PM PDT 24
Finished Jul 29 06:38:51 PM PDT 24
Peak memory 201348 kb
Host smart-3cf5eb34-1e16-4b59-8c7f-4a4cfd9888ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922771734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1922771734
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.911916567
Short name T43
Test name
Test status
Simulation time 4037024146 ps
CPU time 3.2 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:38:54 PM PDT 24
Peak memory 201568 kb
Host smart-b1393d84-36bc-4b16-ae54-8ec152fb2e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911916567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.911916567
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2207783141
Short name T65
Test name
Test status
Simulation time 505718988 ps
CPU time 2.1 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:38:53 PM PDT 24
Peak memory 201644 kb
Host smart-ffbfb702-f999-45f5-aae0-a8daf85f8d11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207783141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2207783141
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3757273727
Short name T55
Test name
Test status
Simulation time 8353071359 ps
CPU time 6.14 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:55 PM PDT 24
Peak memory 201620 kb
Host smart-96f1f22f-68e4-49fb-9864-db282c6b92d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757273727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3757273727
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2024731718
Short name T886
Test name
Test status
Simulation time 319046453 ps
CPU time 1.43 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:09 PM PDT 24
Peak memory 201308 kb
Host smart-d98f8914-4d3c-4bce-9320-aa488866be79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024731718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2024731718
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2022047912
Short name T794
Test name
Test status
Simulation time 403913288 ps
CPU time 0.89 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:08 PM PDT 24
Peak memory 201412 kb
Host smart-35b979a8-032b-46cb-ba67-6d44b7d29b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022047912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2022047912
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2885051989
Short name T896
Test name
Test status
Simulation time 345180331 ps
CPU time 0.97 seconds
Started Jul 29 06:40:07 PM PDT 24
Finished Jul 29 06:40:08 PM PDT 24
Peak memory 201320 kb
Host smart-29a2da08-abd4-4be9-9d8c-7b62d48398b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885051989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2885051989
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.538738426
Short name T842
Test name
Test status
Simulation time 287059469 ps
CPU time 1.28 seconds
Started Jul 29 06:40:08 PM PDT 24
Finished Jul 29 06:40:10 PM PDT 24
Peak memory 201332 kb
Host smart-b700704a-6875-4678-9117-39988c21ba3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538738426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.538738426
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1293528116
Short name T853
Test name
Test status
Simulation time 498986818 ps
CPU time 0.96 seconds
Started Jul 29 06:40:10 PM PDT 24
Finished Jul 29 06:40:11 PM PDT 24
Peak memory 201388 kb
Host smart-536133bb-0dd4-4ecc-bf3f-d38f903e500a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293528116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1293528116
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.559108650
Short name T795
Test name
Test status
Simulation time 541023689 ps
CPU time 0.82 seconds
Started Jul 29 06:40:10 PM PDT 24
Finished Jul 29 06:40:11 PM PDT 24
Peak memory 201380 kb
Host smart-350b675a-89d4-4450-ad46-eb74b9537278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559108650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.559108650
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.892013323
Short name T833
Test name
Test status
Simulation time 480389220 ps
CPU time 1.79 seconds
Started Jul 29 06:40:09 PM PDT 24
Finished Jul 29 06:40:11 PM PDT 24
Peak memory 201140 kb
Host smart-5649e12d-fc53-4538-868d-9e20124f7266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892013323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.892013323
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2184296900
Short name T816
Test name
Test status
Simulation time 299012547 ps
CPU time 1.08 seconds
Started Jul 29 06:40:08 PM PDT 24
Finished Jul 29 06:40:10 PM PDT 24
Peak memory 201324 kb
Host smart-d6f9c166-6e0a-49e5-b28a-9379d80411bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184296900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2184296900
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3344866929
Short name T880
Test name
Test status
Simulation time 363911977 ps
CPU time 1.05 seconds
Started Jul 29 06:40:10 PM PDT 24
Finished Jul 29 06:40:11 PM PDT 24
Peak memory 201388 kb
Host smart-3cc3871e-229e-4414-a234-1fbf908e5a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344866929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3344866929
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3674977052
Short name T900
Test name
Test status
Simulation time 539292025 ps
CPU time 1.21 seconds
Started Jul 29 06:40:09 PM PDT 24
Finished Jul 29 06:40:11 PM PDT 24
Peak memory 201380 kb
Host smart-66583b0e-e7a6-4b11-8c92-3162e13643b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674977052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3674977052
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3866231947
Short name T112
Test name
Test status
Simulation time 1072345058 ps
CPU time 3.27 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:38:55 PM PDT 24
Peak memory 201552 kb
Host smart-f43c6503-7f07-459a-bc29-1ca914f5c33c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866231947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3866231947
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4292907796
Short name T890
Test name
Test status
Simulation time 24679061832 ps
CPU time 42.24 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:39:33 PM PDT 24
Peak memory 201604 kb
Host smart-2ca21392-9f92-441f-b06a-555583045f28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292907796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4292907796
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.642321120
Short name T876
Test name
Test status
Simulation time 1108144999 ps
CPU time 3.22 seconds
Started Jul 29 06:38:50 PM PDT 24
Finished Jul 29 06:38:53 PM PDT 24
Peak memory 201304 kb
Host smart-ff57d658-218e-46d5-9c12-f517ed1c18ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642321120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.642321120
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3257027119
Short name T915
Test name
Test status
Simulation time 399494161 ps
CPU time 1.29 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:38:52 PM PDT 24
Peak memory 201492 kb
Host smart-53504cc7-357f-409c-a31b-9debea5d1a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257027119 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3257027119
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2115370123
Short name T116
Test name
Test status
Simulation time 552210087 ps
CPU time 1.28 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:50 PM PDT 24
Peak memory 201388 kb
Host smart-c5bb1bbf-ebce-457a-8dff-af6128b47bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115370123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2115370123
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2065538478
Short name T847
Test name
Test status
Simulation time 383014347 ps
CPU time 1.44 seconds
Started Jul 29 06:38:49 PM PDT 24
Finished Jul 29 06:38:51 PM PDT 24
Peak memory 201272 kb
Host smart-ba391b31-cb00-46e6-9f55-56267addae1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065538478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2065538478
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1680961072
Short name T872
Test name
Test status
Simulation time 2559480610 ps
CPU time 12.26 seconds
Started Jul 29 06:38:52 PM PDT 24
Finished Jul 29 06:39:04 PM PDT 24
Peak memory 201440 kb
Host smart-e648e8b3-a95c-4d5b-9937-265d0bd7401b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680961072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1680961072
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.274192820
Short name T883
Test name
Test status
Simulation time 615550700 ps
CPU time 2.43 seconds
Started Jul 29 06:38:50 PM PDT 24
Finished Jul 29 06:38:52 PM PDT 24
Peak memory 201616 kb
Host smart-4595549f-11c4-49fb-bd89-b324a988b3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274192820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.274192820
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1045571682
Short name T868
Test name
Test status
Simulation time 8554892078 ps
CPU time 15.04 seconds
Started Jul 29 06:38:52 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 201672 kb
Host smart-83b4cbd8-ab3f-434e-b3d6-28f641e84059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045571682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1045571682
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.937833796
Short name T800
Test name
Test status
Simulation time 390312512 ps
CPU time 0.89 seconds
Started Jul 29 06:40:09 PM PDT 24
Finished Jul 29 06:40:10 PM PDT 24
Peak memory 201072 kb
Host smart-a6bf429b-e674-4571-81c1-ea4dfdad1343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937833796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.937833796
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3197063778
Short name T806
Test name
Test status
Simulation time 307902109 ps
CPU time 0.98 seconds
Started Jul 29 06:40:09 PM PDT 24
Finished Jul 29 06:40:10 PM PDT 24
Peak memory 201384 kb
Host smart-8acbb421-cd12-4ee0-865e-b89b98e0d58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197063778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3197063778
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2890439680
Short name T839
Test name
Test status
Simulation time 524920336 ps
CPU time 1.81 seconds
Started Jul 29 06:40:18 PM PDT 24
Finished Jul 29 06:40:20 PM PDT 24
Peak memory 201356 kb
Host smart-0be8cb71-0e3a-494d-85ee-4d89c25ccf37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890439680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2890439680
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3812675025
Short name T919
Test name
Test status
Simulation time 503977993 ps
CPU time 1.74 seconds
Started Jul 29 06:40:18 PM PDT 24
Finished Jul 29 06:40:20 PM PDT 24
Peak memory 201384 kb
Host smart-61ce1f6a-8042-496b-891f-d5b01a2e41bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812675025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3812675025
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3368907948
Short name T812
Test name
Test status
Simulation time 343673314 ps
CPU time 0.99 seconds
Started Jul 29 06:40:17 PM PDT 24
Finished Jul 29 06:40:18 PM PDT 24
Peak memory 201360 kb
Host smart-0a3cdcc4-1935-4b66-b25b-cd84af0c02b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368907948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3368907948
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.709164544
Short name T874
Test name
Test status
Simulation time 434583868 ps
CPU time 1.29 seconds
Started Jul 29 06:40:19 PM PDT 24
Finished Jul 29 06:40:21 PM PDT 24
Peak memory 201348 kb
Host smart-a3fd3170-6b21-48b3-92d3-6ef1577fc74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709164544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.709164544
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.357998265
Short name T804
Test name
Test status
Simulation time 419464483 ps
CPU time 1.14 seconds
Started Jul 29 06:40:17 PM PDT 24
Finished Jul 29 06:40:18 PM PDT 24
Peak memory 201380 kb
Host smart-f781dce7-48c5-464d-9db9-8b5fe18b6f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357998265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.357998265
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.501566757
Short name T856
Test name
Test status
Simulation time 463395270 ps
CPU time 1.74 seconds
Started Jul 29 06:40:17 PM PDT 24
Finished Jul 29 06:40:19 PM PDT 24
Peak memory 201324 kb
Host smart-447e4ccc-bf85-4433-88fb-28199fd06406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501566757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.501566757
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3484185255
Short name T805
Test name
Test status
Simulation time 441545652 ps
CPU time 1.51 seconds
Started Jul 29 06:40:25 PM PDT 24
Finished Jul 29 06:40:27 PM PDT 24
Peak memory 201360 kb
Host smart-cfd849c2-f9c7-4de6-8fdb-e8ef9d154404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484185255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3484185255
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.915466719
Short name T811
Test name
Test status
Simulation time 475121554 ps
CPU time 1.11 seconds
Started Jul 29 06:40:26 PM PDT 24
Finished Jul 29 06:40:27 PM PDT 24
Peak memory 201352 kb
Host smart-99dc3b88-ba22-4778-921f-9116a6dda848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915466719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.915466719
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3292265530
Short name T109
Test name
Test status
Simulation time 1210471240 ps
CPU time 3.44 seconds
Started Jul 29 06:39:05 PM PDT 24
Finished Jul 29 06:39:08 PM PDT 24
Peak memory 201488 kb
Host smart-1600e8ea-1942-40bf-8bef-7937bba10f07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292265530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3292265530
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2492301032
Short name T889
Test name
Test status
Simulation time 42103885700 ps
CPU time 84.77 seconds
Started Jul 29 06:39:03 PM PDT 24
Finished Jul 29 06:40:27 PM PDT 24
Peak memory 201488 kb
Host smart-8016402a-7d68-4e25-9aee-8767dd5709db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492301032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2492301032
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3195009182
Short name T869
Test name
Test status
Simulation time 1359579075 ps
CPU time 2.2 seconds
Started Jul 29 06:38:55 PM PDT 24
Finished Jul 29 06:38:57 PM PDT 24
Peak memory 201368 kb
Host smart-8fb336e9-1ded-481a-9cf7-05539ca81269
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195009182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3195009182
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.923492096
Short name T88
Test name
Test status
Simulation time 358837883 ps
CPU time 1.56 seconds
Started Jul 29 06:39:04 PM PDT 24
Finished Jul 29 06:39:06 PM PDT 24
Peak memory 201412 kb
Host smart-4c386724-923b-4707-8b17-b8c0454fec96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923492096 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.923492096
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1191675404
Short name T115
Test name
Test status
Simulation time 503692240 ps
CPU time 0.83 seconds
Started Jul 29 06:39:05 PM PDT 24
Finished Jul 29 06:39:06 PM PDT 24
Peak memory 201372 kb
Host smart-99ff85c9-fe96-4dee-92ce-29f98c08d4fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191675404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1191675404
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4116395126
Short name T793
Test name
Test status
Simulation time 300562279 ps
CPU time 0.96 seconds
Started Jul 29 06:39:06 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 201380 kb
Host smart-221b8d6f-016c-4324-ad70-4a5376e9e5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116395126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4116395126
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1785564232
Short name T854
Test name
Test status
Simulation time 4606840102 ps
CPU time 4.27 seconds
Started Jul 29 06:39:05 PM PDT 24
Finished Jul 29 06:39:10 PM PDT 24
Peak memory 201576 kb
Host smart-1b227117-d9f5-4dbf-8377-06665b80384e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785564232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1785564232
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1501332848
Short name T801
Test name
Test status
Simulation time 1022776512 ps
CPU time 2.82 seconds
Started Jul 29 06:38:50 PM PDT 24
Finished Jul 29 06:38:53 PM PDT 24
Peak memory 210908 kb
Host smart-1ddf88c2-4c90-42fa-9ad7-06349c107241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501332848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1501332848
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4165072842
Short name T315
Test name
Test status
Simulation time 4378491238 ps
CPU time 3.78 seconds
Started Jul 29 06:38:51 PM PDT 24
Finished Jul 29 06:38:55 PM PDT 24
Peak memory 201680 kb
Host smart-e409e017-612a-4a3c-99f4-342cdea35b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165072842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4165072842
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.536775400
Short name T858
Test name
Test status
Simulation time 447821198 ps
CPU time 1.19 seconds
Started Jul 29 06:40:27 PM PDT 24
Finished Jul 29 06:40:28 PM PDT 24
Peak memory 201312 kb
Host smart-b24736be-9a52-4ce3-af01-a8edda7eeff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536775400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.536775400
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1246128443
Short name T803
Test name
Test status
Simulation time 311939871 ps
CPU time 0.8 seconds
Started Jul 29 06:40:25 PM PDT 24
Finished Jul 29 06:40:26 PM PDT 24
Peak memory 201328 kb
Host smart-2bda122c-c5b5-4073-a911-c22b5d01c9ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246128443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1246128443
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1646071460
Short name T797
Test name
Test status
Simulation time 350169134 ps
CPU time 1.11 seconds
Started Jul 29 06:40:28 PM PDT 24
Finished Jul 29 06:40:30 PM PDT 24
Peak memory 201380 kb
Host smart-5a4380d6-5d42-4e6f-bdcb-ddc37a3534d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646071460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1646071460
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.362027418
Short name T808
Test name
Test status
Simulation time 504719744 ps
CPU time 0.77 seconds
Started Jul 29 06:40:29 PM PDT 24
Finished Jul 29 06:40:30 PM PDT 24
Peak memory 201368 kb
Host smart-3eab198e-c0a7-4030-b8ad-15662a02757d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362027418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.362027418
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1392314769
Short name T809
Test name
Test status
Simulation time 389815262 ps
CPU time 0.74 seconds
Started Jul 29 06:40:27 PM PDT 24
Finished Jul 29 06:40:28 PM PDT 24
Peak memory 201324 kb
Host smart-454521fc-e94d-4d81-a203-ae7b6f4005ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392314769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1392314769
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2405492812
Short name T845
Test name
Test status
Simulation time 471466586 ps
CPU time 1.12 seconds
Started Jul 29 06:40:27 PM PDT 24
Finished Jul 29 06:40:28 PM PDT 24
Peak memory 201340 kb
Host smart-b926f84d-68dc-4a78-8886-4d7b87018877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405492812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2405492812
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4286381394
Short name T798
Test name
Test status
Simulation time 326783322 ps
CPU time 1.22 seconds
Started Jul 29 06:40:26 PM PDT 24
Finished Jul 29 06:40:28 PM PDT 24
Peak memory 201380 kb
Host smart-3694e8c7-8bae-4100-aaf6-f57518609a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286381394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4286381394
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4209008677
Short name T796
Test name
Test status
Simulation time 466693291 ps
CPU time 0.93 seconds
Started Jul 29 06:40:26 PM PDT 24
Finished Jul 29 06:40:27 PM PDT 24
Peak memory 201372 kb
Host smart-d84368b3-c25d-4236-93a6-82b577b59465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209008677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4209008677
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1313836132
Short name T910
Test name
Test status
Simulation time 499979476 ps
CPU time 1.69 seconds
Started Jul 29 06:40:25 PM PDT 24
Finished Jul 29 06:40:27 PM PDT 24
Peak memory 201340 kb
Host smart-46dcca79-0eee-4dff-8c4c-2b472d0cdfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313836132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1313836132
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4064960180
Short name T855
Test name
Test status
Simulation time 499467505 ps
CPU time 1.24 seconds
Started Jul 29 06:40:27 PM PDT 24
Finished Jul 29 06:40:28 PM PDT 24
Peak memory 201360 kb
Host smart-11e99ab4-81de-4e77-8b89-bd69c142b590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064960180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4064960180
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2424410603
Short name T884
Test name
Test status
Simulation time 480261242 ps
CPU time 1.99 seconds
Started Jul 29 06:39:09 PM PDT 24
Finished Jul 29 06:39:11 PM PDT 24
Peak memory 201508 kb
Host smart-1f060e94-d08f-443c-9a58-3b856efdd1b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424410603 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2424410603
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1070102906
Short name T110
Test name
Test status
Simulation time 434400958 ps
CPU time 1.79 seconds
Started Jul 29 06:39:03 PM PDT 24
Finished Jul 29 06:39:05 PM PDT 24
Peak memory 201292 kb
Host smart-a5359e86-c1fa-4405-a1c6-2217b1ef2279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070102906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1070102906
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1778754757
Short name T895
Test name
Test status
Simulation time 289607285 ps
CPU time 1.24 seconds
Started Jul 29 06:39:06 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 201376 kb
Host smart-49f62cc4-f1fe-40c1-a0b6-9ae31d41836c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778754757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1778754757
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3046155163
Short name T123
Test name
Test status
Simulation time 2782323502 ps
CPU time 2.92 seconds
Started Jul 29 06:39:06 PM PDT 24
Finished Jul 29 06:39:09 PM PDT 24
Peak memory 201456 kb
Host smart-5be456e8-3afd-49dc-b94e-001993d6650a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046155163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3046155163
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1632219542
Short name T59
Test name
Test status
Simulation time 437511788 ps
CPU time 1.95 seconds
Started Jul 29 06:39:04 PM PDT 24
Finished Jul 29 06:39:06 PM PDT 24
Peak memory 201668 kb
Host smart-4953fbd7-b551-4b09-bc55-4e39f4efc847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632219542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1632219542
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1033905242
Short name T48
Test name
Test status
Simulation time 8177232056 ps
CPU time 6.87 seconds
Started Jul 29 06:39:06 PM PDT 24
Finished Jul 29 06:39:13 PM PDT 24
Peak memory 201668 kb
Host smart-56805e61-e659-4902-a03e-5895be9b3fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033905242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1033905242
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.728091624
Short name T822
Test name
Test status
Simulation time 512201961 ps
CPU time 1.27 seconds
Started Jul 29 06:39:18 PM PDT 24
Finished Jul 29 06:39:19 PM PDT 24
Peak memory 201464 kb
Host smart-3c7c6f6e-f97a-4737-8a2a-ef1dfa63a91f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728091624 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.728091624
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3329674015
Short name T799
Test name
Test status
Simulation time 405956683 ps
CPU time 0.82 seconds
Started Jul 29 06:39:08 PM PDT 24
Finished Jul 29 06:39:09 PM PDT 24
Peak memory 201376 kb
Host smart-bde246c9-026e-4c12-89e5-bf4024db44d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329674015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3329674015
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1346096179
Short name T122
Test name
Test status
Simulation time 4737101039 ps
CPU time 1.88 seconds
Started Jul 29 06:39:20 PM PDT 24
Finished Jul 29 06:39:22 PM PDT 24
Peak memory 201668 kb
Host smart-b1a24f8e-dd02-4693-abf9-24e3e13c39f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346096179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1346096179
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4223626795
Short name T823
Test name
Test status
Simulation time 1009834808 ps
CPU time 3.14 seconds
Started Jul 29 06:39:08 PM PDT 24
Finished Jul 29 06:39:11 PM PDT 24
Peak memory 218056 kb
Host smart-76379368-b8db-4323-b8b8-8a7e5617d76c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223626795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.4223626795
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3559889521
Short name T904
Test name
Test status
Simulation time 4848124621 ps
CPU time 4.45 seconds
Started Jul 29 06:39:09 PM PDT 24
Finished Jul 29 06:39:13 PM PDT 24
Peak memory 201688 kb
Host smart-140ffa0a-25fe-435d-9188-44811eabeee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559889521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3559889521
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3249429666
Short name T844
Test name
Test status
Simulation time 584706397 ps
CPU time 2.17 seconds
Started Jul 29 06:39:47 PM PDT 24
Finished Jul 29 06:39:49 PM PDT 24
Peak memory 201512 kb
Host smart-f00b0c4c-d5b4-4aa6-bd17-9a60334b0182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249429666 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3249429666
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.566828010
Short name T820
Test name
Test status
Simulation time 466552771 ps
CPU time 1.49 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201364 kb
Host smart-d3bfdd09-056c-46b5-8d7d-70043d3600d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566828010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.566828010
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2343459029
Short name T817
Test name
Test status
Simulation time 484341871 ps
CPU time 0.8 seconds
Started Jul 29 06:39:48 PM PDT 24
Finished Jul 29 06:39:49 PM PDT 24
Peak memory 201320 kb
Host smart-2f1d6200-a01f-46eb-b22d-a7ffaf82abf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343459029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2343459029
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1724060005
Short name T850
Test name
Test status
Simulation time 4583512210 ps
CPU time 13.82 seconds
Started Jul 29 06:39:47 PM PDT 24
Finished Jul 29 06:40:01 PM PDT 24
Peak memory 201588 kb
Host smart-07486dbe-9956-49ba-9d0f-98195b271562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724060005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1724060005
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.747583897
Short name T53
Test name
Test status
Simulation time 322950609 ps
CPU time 1.93 seconds
Started Jul 29 06:39:18 PM PDT 24
Finished Jul 29 06:39:20 PM PDT 24
Peak memory 201632 kb
Host smart-5722d1e5-2256-40a8-a347-ae6f7d156cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747583897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.747583897
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.402416655
Short name T49
Test name
Test status
Simulation time 4430927976 ps
CPU time 10.72 seconds
Started Jul 29 06:39:20 PM PDT 24
Finished Jul 29 06:39:31 PM PDT 24
Peak memory 201736 kb
Host smart-66cad982-adb7-4b3d-95c3-6905335d1ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402416655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.402416655
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1915329925
Short name T828
Test name
Test status
Simulation time 550476560 ps
CPU time 1.42 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201472 kb
Host smart-58eccb2d-dd6f-4d68-a035-917a091aba40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915329925 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1915329925
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4286531442
Short name T875
Test name
Test status
Simulation time 534803117 ps
CPU time 1.34 seconds
Started Jul 29 06:39:48 PM PDT 24
Finished Jul 29 06:39:50 PM PDT 24
Peak memory 201384 kb
Host smart-aa237431-7d43-4939-b867-131a6873240b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286531442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4286531442
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4286521616
Short name T849
Test name
Test status
Simulation time 568437087 ps
CPU time 0.76 seconds
Started Jul 29 06:39:47 PM PDT 24
Finished Jul 29 06:39:48 PM PDT 24
Peak memory 201376 kb
Host smart-f668595e-659c-4689-9317-d6824fec6677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286521616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4286521616
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2233990332
Short name T861
Test name
Test status
Simulation time 4894830438 ps
CPU time 4.25 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201616 kb
Host smart-d0926cff-4e0b-47b4-b7fb-47fb80eddcbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233990332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2233990332
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3697725955
Short name T60
Test name
Test status
Simulation time 453580882 ps
CPU time 2.78 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201624 kb
Host smart-681ced3b-54bc-41f7-93ae-4e2aa3c909c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697725955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3697725955
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2350453730
Short name T827
Test name
Test status
Simulation time 4343153026 ps
CPU time 10.89 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:40:00 PM PDT 24
Peak memory 201696 kb
Host smart-b245229e-50f6-4788-b256-28b015dec72c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350453730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2350453730
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2272630570
Short name T802
Test name
Test status
Simulation time 450572999 ps
CPU time 1.87 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201504 kb
Host smart-d0442b87-30fe-4cad-8fba-d6d87cf6cbbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272630570 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2272630570
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1112787050
Short name T117
Test name
Test status
Simulation time 436715731 ps
CPU time 1.8 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:52 PM PDT 24
Peak memory 201516 kb
Host smart-db76e8bf-26af-4ac6-bcf4-51259ba884a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112787050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1112787050
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1346496350
Short name T892
Test name
Test status
Simulation time 475319245 ps
CPU time 1.63 seconds
Started Jul 29 06:39:49 PM PDT 24
Finished Jul 29 06:39:51 PM PDT 24
Peak memory 201348 kb
Host smart-fbfe7b82-b49c-45b7-9e8f-492dda31cbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346496350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1346496350
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3453659621
Short name T867
Test name
Test status
Simulation time 2558349738 ps
CPU time 2.84 seconds
Started Jul 29 06:39:50 PM PDT 24
Finished Jul 29 06:39:53 PM PDT 24
Peak memory 201420 kb
Host smart-3c6277b7-1cd0-4f18-8091-09dcc7145171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453659621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3453659621
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1982763666
Short name T885
Test name
Test status
Simulation time 615509880 ps
CPU time 1.51 seconds
Started Jul 29 06:39:25 PM PDT 24
Finished Jul 29 06:39:27 PM PDT 24
Peak memory 201644 kb
Host smart-6f09cd62-597a-4c0d-987c-bcbd2235bf66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982763666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1982763666
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4186821666
Short name T755
Test name
Test status
Simulation time 343449034 ps
CPU time 0.86 seconds
Started Jul 29 05:39:55 PM PDT 24
Finished Jul 29 05:39:56 PM PDT 24
Peak memory 201196 kb
Host smart-65b6e538-5671-4044-92e2-b474c80d85c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186821666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4186821666
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4132676233
Short name T629
Test name
Test status
Simulation time 160839002256 ps
CPU time 99.92 seconds
Started Jul 29 05:39:53 PM PDT 24
Finished Jul 29 05:41:33 PM PDT 24
Peak memory 201380 kb
Host smart-97bb6a86-74d0-4134-8f8a-71edd1182960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132676233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4132676233
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2934233368
Short name T716
Test name
Test status
Simulation time 498346643514 ps
CPU time 1135.05 seconds
Started Jul 29 05:39:48 PM PDT 24
Finished Jul 29 05:58:43 PM PDT 24
Peak memory 201400 kb
Host smart-767911b8-8442-4d93-bdaa-af7de7ed9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934233368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2934233368
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.798394277
Short name T620
Test name
Test status
Simulation time 319627890689 ps
CPU time 691.62 seconds
Started Jul 29 05:39:46 PM PDT 24
Finished Jul 29 05:51:18 PM PDT 24
Peak memory 201452 kb
Host smart-b064058c-c625-4fcf-b4cf-a980fedab64b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=798394277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.798394277
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4176045982
Short name T272
Test name
Test status
Simulation time 482407801347 ps
CPU time 1030.28 seconds
Started Jul 29 05:39:51 PM PDT 24
Finished Jul 29 05:57:02 PM PDT 24
Peak memory 201444 kb
Host smart-da3a0782-7648-4762-800c-38523f67ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176045982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4176045982
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3382619944
Short name T681
Test name
Test status
Simulation time 486699458234 ps
CPU time 543.57 seconds
Started Jul 29 05:39:47 PM PDT 24
Finished Jul 29 05:48:51 PM PDT 24
Peak memory 201432 kb
Host smart-37d1e251-86af-4962-98fc-4faa26528dd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382619944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3382619944
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1448055042
Short name T592
Test name
Test status
Simulation time 177592915149 ps
CPU time 397.55 seconds
Started Jul 29 05:39:51 PM PDT 24
Finished Jul 29 05:46:28 PM PDT 24
Peak memory 201536 kb
Host smart-08c1a3f2-6da5-49a5-ab49-acd85ced3c24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448055042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1448055042
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3453038221
Short name T738
Test name
Test status
Simulation time 402556438471 ps
CPU time 169.44 seconds
Started Jul 29 05:39:49 PM PDT 24
Finished Jul 29 05:42:39 PM PDT 24
Peak memory 201432 kb
Host smart-49703897-8685-46ea-a837-765592119d4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453038221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3453038221
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3265432267
Short name T193
Test name
Test status
Simulation time 108128997934 ps
CPU time 406.64 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:46:39 PM PDT 24
Peak memory 201796 kb
Host smart-3b49c2b6-5341-4d20-9d57-01f18c1b8738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265432267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3265432267
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3753352115
Short name T448
Test name
Test status
Simulation time 46117460101 ps
CPU time 85.98 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:41:18 PM PDT 24
Peak memory 201276 kb
Host smart-6db6ebb8-8429-478d-9ae8-fdd9cd3c3b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753352115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3753352115
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2081853071
Short name T577
Test name
Test status
Simulation time 5244314937 ps
CPU time 3.75 seconds
Started Jul 29 05:39:53 PM PDT 24
Finished Jul 29 05:39:57 PM PDT 24
Peak memory 201360 kb
Host smart-58d57131-1817-4ef3-b52e-17fad4727737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081853071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2081853071
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3640613082
Short name T427
Test name
Test status
Simulation time 6062750628 ps
CPU time 15.03 seconds
Started Jul 29 05:39:48 PM PDT 24
Finished Jul 29 05:40:03 PM PDT 24
Peak memory 201380 kb
Host smart-8398c229-3fd4-4fcc-8aca-5718b266292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640613082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3640613082
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.129349372
Short name T177
Test name
Test status
Simulation time 463540059899 ps
CPU time 1489.6 seconds
Started Jul 29 05:39:55 PM PDT 24
Finished Jul 29 06:04:45 PM PDT 24
Peak memory 212612 kb
Host smart-316f09d1-f401-47ee-897d-e13a4da7bad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129349372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.129349372
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3814368298
Short name T364
Test name
Test status
Simulation time 47201258735 ps
CPU time 28.46 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:40:21 PM PDT 24
Peak memory 209844 kb
Host smart-2962879c-2ef5-4ac3-9649-fd7024d340f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814368298 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3814368298
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.954964430
Short name T606
Test name
Test status
Simulation time 518847258 ps
CPU time 1.81 seconds
Started Jul 29 05:39:56 PM PDT 24
Finished Jul 29 05:39:58 PM PDT 24
Peak memory 201168 kb
Host smart-22bd2de5-7c5c-49d3-a607-aaa04a7ae3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954964430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.954964430
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4277344719
Short name T234
Test name
Test status
Simulation time 491701468599 ps
CPU time 549.89 seconds
Started Jul 29 05:39:56 PM PDT 24
Finished Jul 29 05:49:06 PM PDT 24
Peak memory 201520 kb
Host smart-d02f4c7a-32bb-4ba7-9590-1772d9708f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277344719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4277344719
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2634770580
Short name T726
Test name
Test status
Simulation time 167049954158 ps
CPU time 90.92 seconds
Started Jul 29 05:39:53 PM PDT 24
Finished Jul 29 05:41:24 PM PDT 24
Peak memory 201460 kb
Host smart-d412b226-1625-42bf-9d39-a434d62d8cd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634770580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2634770580
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.157177851
Short name T583
Test name
Test status
Simulation time 158461890612 ps
CPU time 93.82 seconds
Started Jul 29 05:39:55 PM PDT 24
Finished Jul 29 05:41:29 PM PDT 24
Peak memory 201444 kb
Host smart-90f171f5-0ab0-4622-afbf-95fe7ea1dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157177851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.157177851
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2125197370
Short name T322
Test name
Test status
Simulation time 486973813858 ps
CPU time 1204.5 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:59:57 PM PDT 24
Peak memory 201468 kb
Host smart-00c4b272-a222-4e38-89bf-82904815f967
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125197370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2125197370
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1865209597
Short name T790
Test name
Test status
Simulation time 376243080342 ps
CPU time 213.54 seconds
Started Jul 29 05:39:52 PM PDT 24
Finished Jul 29 05:43:25 PM PDT 24
Peak memory 201612 kb
Host smart-6d086e23-0167-4c95-89a0-0f9f7a01c5f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865209597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1865209597
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2844974411
Short name T534
Test name
Test status
Simulation time 205861214834 ps
CPU time 443.32 seconds
Started Jul 29 05:39:53 PM PDT 24
Finished Jul 29 05:47:16 PM PDT 24
Peak memory 201440 kb
Host smart-79004cde-8591-43ba-99bd-720b8a62e735
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844974411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2844974411
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3504311601
Short name T41
Test name
Test status
Simulation time 71841121571 ps
CPU time 283.67 seconds
Started Jul 29 05:39:59 PM PDT 24
Finished Jul 29 05:44:42 PM PDT 24
Peak memory 201824 kb
Host smart-0b2384c6-bd2e-4bcc-b1b3-58a074ed5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504311601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3504311601
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1204831269
Short name T345
Test name
Test status
Simulation time 42933467948 ps
CPU time 90.85 seconds
Started Jul 29 05:39:56 PM PDT 24
Finished Jul 29 05:41:27 PM PDT 24
Peak memory 201312 kb
Host smart-896e4b36-a066-41e6-937a-dffd4141a557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204831269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1204831269
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2762257993
Short name T640
Test name
Test status
Simulation time 3960609929 ps
CPU time 5.13 seconds
Started Jul 29 05:39:54 PM PDT 24
Finished Jul 29 05:39:59 PM PDT 24
Peak memory 201332 kb
Host smart-f57684e6-981d-4cc5-abc4-3bc9845ded88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762257993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2762257993
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3466235211
Short name T68
Test name
Test status
Simulation time 8352085714 ps
CPU time 20.25 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:40:18 PM PDT 24
Peak memory 218180 kb
Host smart-f9887fd5-bfc4-4e82-984d-76faf1f3dc94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466235211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3466235211
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.105822227
Short name T330
Test name
Test status
Simulation time 5687698442 ps
CPU time 4.44 seconds
Started Jul 29 05:39:56 PM PDT 24
Finished Jul 29 05:40:01 PM PDT 24
Peak memory 201364 kb
Host smart-b9bc9d5f-d4a5-4baf-9654-a478a4a486f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105822227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.105822227
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1960403076
Short name T206
Test name
Test status
Simulation time 97258804923 ps
CPU time 287.63 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:44:46 PM PDT 24
Peak memory 202040 kb
Host smart-2f692ed0-5c7e-462e-910b-09e0d94cd56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960403076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1960403076
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3128248472
Short name T13
Test name
Test status
Simulation time 25251105038 ps
CPU time 28.37 seconds
Started Jul 29 05:39:57 PM PDT 24
Finished Jul 29 05:40:25 PM PDT 24
Peak memory 209760 kb
Host smart-59982de1-6e75-46fe-8dba-37c23abe220f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128248472 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3128248472
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.219147919
Short name T740
Test name
Test status
Simulation time 373933408 ps
CPU time 0.75 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:40:38 PM PDT 24
Peak memory 201224 kb
Host smart-ed498eab-a8cc-4e23-a2b3-6911343ea36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219147919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.219147919
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1465259897
Short name T431
Test name
Test status
Simulation time 163407126048 ps
CPU time 100.26 seconds
Started Jul 29 05:40:29 PM PDT 24
Finished Jul 29 05:42:09 PM PDT 24
Peak memory 201452 kb
Host smart-e574b7fa-9648-4ead-a84b-534f7e6ed120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465259897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1465259897
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2656922328
Short name T379
Test name
Test status
Simulation time 483475515497 ps
CPU time 265.23 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:45:02 PM PDT 24
Peak memory 200476 kb
Host smart-5688046c-45eb-47e3-a80d-6977db5a4c5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656922328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2656922328
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3099173510
Short name T700
Test name
Test status
Simulation time 166814056496 ps
CPU time 97.3 seconds
Started Jul 29 05:40:32 PM PDT 24
Finished Jul 29 05:42:09 PM PDT 24
Peak memory 201388 kb
Host smart-be82c710-4b97-4c27-83ee-18b2490d7d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099173510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3099173510
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1560033892
Short name T727
Test name
Test status
Simulation time 325666232939 ps
CPU time 203.42 seconds
Started Jul 29 05:40:31 PM PDT 24
Finished Jul 29 05:43:55 PM PDT 24
Peak memory 201388 kb
Host smart-4b8ea646-a0c4-40dd-b919-b233f7a680b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560033892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1560033892
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2393974237
Short name T30
Test name
Test status
Simulation time 608800791504 ps
CPU time 359.47 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:46:33 PM PDT 24
Peak memory 201464 kb
Host smart-87240790-f14f-4e6f-bb72-6e52b084fa88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393974237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2393974237
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2544473768
Short name T697
Test name
Test status
Simulation time 80533047124 ps
CPU time 310.09 seconds
Started Jul 29 05:40:32 PM PDT 24
Finished Jul 29 05:45:42 PM PDT 24
Peak memory 201752 kb
Host smart-ed16fe9b-afe9-434d-88a1-10a2d59411e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544473768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2544473768
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1192100949
Short name T688
Test name
Test status
Simulation time 34919929249 ps
CPU time 81.43 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:41:54 PM PDT 24
Peak memory 201356 kb
Host smart-419ebe74-96c7-4e94-89e4-4881d0d0b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192100949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1192100949
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.818747410
Short name T531
Test name
Test status
Simulation time 2940011313 ps
CPU time 7.57 seconds
Started Jul 29 05:40:35 PM PDT 24
Finished Jul 29 05:40:43 PM PDT 24
Peak memory 201348 kb
Host smart-8e194212-8c6d-492e-b206-425f81ea60d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818747410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.818747410
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1169042913
Short name T87
Test name
Test status
Simulation time 5994870920 ps
CPU time 4.87 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:40:32 PM PDT 24
Peak memory 201368 kb
Host smart-712c5cba-6b28-4025-846c-67c0110574a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169042913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1169042913
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.78957572
Short name T188
Test name
Test status
Simulation time 304432838105 ps
CPU time 565.18 seconds
Started Jul 29 05:40:35 PM PDT 24
Finished Jul 29 05:50:01 PM PDT 24
Peak memory 201832 kb
Host smart-a8130b4c-3f0c-4e8b-bd55-e7aa69a40999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78957572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.78957572
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.158331647
Short name T659
Test name
Test status
Simulation time 118064332046 ps
CPU time 77.91 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:41:51 PM PDT 24
Peak memory 209836 kb
Host smart-f08d67e4-6007-43eb-83b8-c47af7b47947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158331647 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.158331647
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3686290815
Short name T413
Test name
Test status
Simulation time 349190632 ps
CPU time 0.98 seconds
Started Jul 29 05:40:35 PM PDT 24
Finished Jul 29 05:40:36 PM PDT 24
Peak memory 201240 kb
Host smart-9d108779-9621-4bd2-b21f-6e02eb09c1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686290815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3686290815
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4114165932
Short name T275
Test name
Test status
Simulation time 194950778417 ps
CPU time 203.96 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:43:58 PM PDT 24
Peak memory 201480 kb
Host smart-4c66d5da-188b-4e17-b157-5d51111c1793
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114165932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4114165932
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3577015109
Short name T520
Test name
Test status
Simulation time 168777530126 ps
CPU time 44.35 seconds
Started Jul 29 05:40:32 PM PDT 24
Finished Jul 29 05:41:16 PM PDT 24
Peak memory 201412 kb
Host smart-bb73669d-72e1-48c5-b98b-e4ba1b74853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577015109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3577015109
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2516702043
Short name T162
Test name
Test status
Simulation time 495212838117 ps
CPU time 314.26 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 05:45:49 PM PDT 24
Peak memory 201500 kb
Host smart-92c13099-7047-4dea-8586-f8ee094d54fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516702043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2516702043
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2297950522
Short name T519
Test name
Test status
Simulation time 487722384881 ps
CPU time 603.77 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:50:41 PM PDT 24
Peak memory 201432 kb
Host smart-517ea5a4-b550-47fc-bc96-e3698a982e24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297950522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2297950522
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4152838078
Short name T399
Test name
Test status
Simulation time 498666152446 ps
CPU time 1128.43 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:59:21 PM PDT 24
Peak memory 201444 kb
Host smart-9d9055f7-1b7a-42a8-9e44-1d25fcb7ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152838078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4152838078
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3711435017
Short name T351
Test name
Test status
Simulation time 163015126513 ps
CPU time 347.07 seconds
Started Jul 29 05:40:35 PM PDT 24
Finished Jul 29 05:46:22 PM PDT 24
Peak memory 201344 kb
Host smart-64fbe537-d0d9-4d0c-ba1d-9135e0cce8bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711435017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3711435017
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3813782658
Short name T24
Test name
Test status
Simulation time 337099697504 ps
CPU time 790.86 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:53:44 PM PDT 24
Peak memory 201448 kb
Host smart-d321d8ef-c359-437d-9f93-e25f9a11a7aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813782658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3813782658
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3866596391
Short name T625
Test name
Test status
Simulation time 587133516557 ps
CPU time 1193.01 seconds
Started Jul 29 05:40:38 PM PDT 24
Finished Jul 29 06:00:32 PM PDT 24
Peak memory 201388 kb
Host smart-479bb9b1-cfd0-4750-a8a9-f51959e0b8a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866596391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3866596391
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3839116923
Short name T348
Test name
Test status
Simulation time 41470976514 ps
CPU time 24.04 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:40:57 PM PDT 24
Peak memory 201300 kb
Host smart-0378e4c9-543a-44e6-ae90-b5857aed22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839116923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3839116923
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3746564413
Short name T419
Test name
Test status
Simulation time 4981884221 ps
CPU time 6.21 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 05:40:40 PM PDT 24
Peak memory 201248 kb
Host smart-c9b27ab9-506d-430c-a675-117754f17811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746564413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3746564413
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.326760773
Short name T340
Test name
Test status
Simulation time 6193445140 ps
CPU time 4.1 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:40:42 PM PDT 24
Peak memory 201360 kb
Host smart-4528d9d6-8ad4-430e-87f1-fd9d0549108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326760773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.326760773
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3045832939
Short name T517
Test name
Test status
Simulation time 546400809555 ps
CPU time 1028.82 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 05:57:43 PM PDT 24
Peak memory 201504 kb
Host smart-b66aa742-5e3a-49a4-8597-75f1067c5d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045832939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3045832939
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4220913063
Short name T732
Test name
Test status
Simulation time 150320244381 ps
CPU time 44.91 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:41:23 PM PDT 24
Peak memory 209744 kb
Host smart-887f27f4-52df-40f7-a20d-7fbc77c0af9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220913063 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4220913063
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2704455263
Short name T7
Test name
Test status
Simulation time 367546265734 ps
CPU time 830.13 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:54:24 PM PDT 24
Peak memory 201472 kb
Host smart-64992a98-a2c2-4f5a-a2e7-47ec0a1c7b29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704455263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2704455263
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1606216472
Short name T294
Test name
Test status
Simulation time 512977113955 ps
CPU time 609.63 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:50:45 PM PDT 24
Peak memory 201500 kb
Host smart-02921469-4d63-44cb-bffa-fa98315016dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606216472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1606216472
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.543987898
Short name T221
Test name
Test status
Simulation time 314804962073 ps
CPU time 304.14 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:45:37 PM PDT 24
Peak memory 201444 kb
Host smart-144668f6-9975-448c-93f0-35cf100ca3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543987898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.543987898
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1134026001
Short name T792
Test name
Test status
Simulation time 169551912576 ps
CPU time 158.1 seconds
Started Jul 29 05:40:35 PM PDT 24
Finished Jul 29 05:43:13 PM PDT 24
Peak memory 201436 kb
Host smart-fd79507b-8ef3-4d5f-b1ce-e71c6bc46e52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134026001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1134026001
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1411770876
Short name T473
Test name
Test status
Simulation time 166126496393 ps
CPU time 360.34 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:46:38 PM PDT 24
Peak memory 201420 kb
Host smart-64deaf7e-c07a-4f02-8329-7a96a38af10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411770876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1411770876
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2000932494
Short name T644
Test name
Test status
Simulation time 496589730683 ps
CPU time 1222.35 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 06:00:56 PM PDT 24
Peak memory 201588 kb
Host smart-848ec66e-0684-42f5-8b28-1856edb08e41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000932494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2000932494
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1798284655
Short name T151
Test name
Test status
Simulation time 355469505085 ps
CPU time 852.07 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 201404 kb
Host smart-0af30b29-68c1-4663-b687-7cd4e7663705
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798284655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1798284655
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3432400362
Short name T478
Test name
Test status
Simulation time 203227923738 ps
CPU time 127.26 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:42:41 PM PDT 24
Peak memory 201440 kb
Host smart-7a1211e9-8ee4-452e-a5af-1d62d00a2384
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432400362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3432400362
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4277559828
Short name T334
Test name
Test status
Simulation time 39233770498 ps
CPU time 82.26 seconds
Started Jul 29 05:40:34 PM PDT 24
Finished Jul 29 05:41:56 PM PDT 24
Peak memory 201308 kb
Host smart-86a8f8e6-d843-4ebe-8294-975a41f4c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277559828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4277559828
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.17138872
Short name T542
Test name
Test status
Simulation time 3501920301 ps
CPU time 2.51 seconds
Started Jul 29 05:40:33 PM PDT 24
Finished Jul 29 05:40:35 PM PDT 24
Peak memory 201308 kb
Host smart-bc6fbfac-cf19-4389-9873-28ff56f7016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17138872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.17138872
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1557980149
Short name T125
Test name
Test status
Simulation time 5791251917 ps
CPU time 2.6 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:40:41 PM PDT 24
Peak memory 201304 kb
Host smart-1a8a156e-acd1-4662-9ea9-a83830a3dc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557980149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1557980149
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3081371892
Short name T724
Test name
Test status
Simulation time 173079306794 ps
CPU time 418.15 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:47:35 PM PDT 24
Peak memory 201456 kb
Host smart-0b47a08c-fea5-4b08-a838-dd40e3200e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081371892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3081371892
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.595842756
Short name T438
Test name
Test status
Simulation time 386795740 ps
CPU time 1.45 seconds
Started Jul 29 05:40:43 PM PDT 24
Finished Jul 29 05:40:45 PM PDT 24
Peak memory 201172 kb
Host smart-5c2b5561-9557-49f5-91b6-49badf2b9f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595842756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.595842756
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.109023025
Short name T499
Test name
Test status
Simulation time 336846370688 ps
CPU time 192.97 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:43:52 PM PDT 24
Peak memory 201444 kb
Host smart-05bd1297-a932-425d-8422-b5d9fb807fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109023025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.109023025
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3773154868
Short name T169
Test name
Test status
Simulation time 321403755915 ps
CPU time 378.53 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:46:56 PM PDT 24
Peak memory 201464 kb
Host smart-464ea512-e0ef-411a-a9ab-323615afddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773154868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3773154868
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2423331805
Short name T497
Test name
Test status
Simulation time 491506821568 ps
CPU time 1056.1 seconds
Started Jul 29 05:40:38 PM PDT 24
Finished Jul 29 05:58:14 PM PDT 24
Peak memory 201360 kb
Host smart-073cfdca-c921-47d8-ad8e-6bc16e627ef0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423331805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2423331805
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2673824101
Short name T312
Test name
Test status
Simulation time 332971327379 ps
CPU time 345.74 seconds
Started Jul 29 05:40:38 PM PDT 24
Finished Jul 29 05:46:24 PM PDT 24
Peak memory 201512 kb
Host smart-deb3811f-0309-4bc4-b228-4aceec91fafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673824101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2673824101
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3360724684
Short name T523
Test name
Test status
Simulation time 335362901617 ps
CPU time 809.64 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:54:09 PM PDT 24
Peak memory 201372 kb
Host smart-42e6863d-4b96-4778-9a06-6510a1f386d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360724684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3360724684
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.247426815
Short name T704
Test name
Test status
Simulation time 630842663785 ps
CPU time 726.86 seconds
Started Jul 29 05:40:41 PM PDT 24
Finished Jul 29 05:52:48 PM PDT 24
Peak memory 201484 kb
Host smart-31595553-5555-46d0-810a-46ff6fdf1b84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247426815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.247426815
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3369721497
Short name T185
Test name
Test status
Simulation time 92299799813 ps
CPU time 365.32 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:46:45 PM PDT 24
Peak memory 201796 kb
Host smart-ffc668eb-658a-40b0-9a22-3c276bf2ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369721497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3369721497
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2337838475
Short name T543
Test name
Test status
Simulation time 48702034698 ps
CPU time 26.26 seconds
Started Jul 29 05:40:38 PM PDT 24
Finished Jul 29 05:41:04 PM PDT 24
Peak memory 201360 kb
Host smart-76efcdde-7a92-4b05-98d1-013de433741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337838475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2337838475
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.273062457
Short name T634
Test name
Test status
Simulation time 4064066285 ps
CPU time 3.26 seconds
Started Jul 29 05:40:39 PM PDT 24
Finished Jul 29 05:40:43 PM PDT 24
Peak memory 201324 kb
Host smart-72981e72-cdff-47b7-937f-7aa3aca3a6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273062457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.273062457
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3923022109
Short name T560
Test name
Test status
Simulation time 5848168085 ps
CPU time 4.88 seconds
Started Jul 29 05:40:37 PM PDT 24
Finished Jul 29 05:40:42 PM PDT 24
Peak memory 201304 kb
Host smart-fcdb907a-f345-447c-8ae9-5c715c4d6470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923022109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3923022109
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2072253189
Short name T100
Test name
Test status
Simulation time 496662356597 ps
CPU time 122.72 seconds
Started Jul 29 05:40:44 PM PDT 24
Finished Jul 29 05:42:47 PM PDT 24
Peak memory 201380 kb
Host smart-abdccacf-82cb-44e8-95c6-2663c8888a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072253189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2072253189
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1424009591
Short name T18
Test name
Test status
Simulation time 22044654364 ps
CPU time 52.55 seconds
Started Jul 29 05:40:43 PM PDT 24
Finished Jul 29 05:41:36 PM PDT 24
Peak memory 217952 kb
Host smart-341c41ec-88d4-4967-9256-5110c75de1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424009591 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1424009591
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3158618420
Short name T349
Test name
Test status
Simulation time 461197803 ps
CPU time 1.67 seconds
Started Jul 29 05:40:58 PM PDT 24
Finished Jul 29 05:41:00 PM PDT 24
Peak memory 201248 kb
Host smart-7b68cde3-5f77-4a59-bed4-e4fcaa1ae645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158618420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3158618420
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1122412666
Short name T296
Test name
Test status
Simulation time 497636772834 ps
CPU time 1163.23 seconds
Started Jul 29 05:40:57 PM PDT 24
Finished Jul 29 06:00:21 PM PDT 24
Peak memory 201392 kb
Host smart-c73d166b-e2ad-4ee2-9a78-1faaa3830729
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122412666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1122412666
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1720967336
Short name T265
Test name
Test status
Simulation time 477060820215 ps
CPU time 1153.64 seconds
Started Jul 29 05:40:49 PM PDT 24
Finished Jul 29 06:00:03 PM PDT 24
Peak memory 201400 kb
Host smart-8b842d40-0654-4fb3-8d95-e1d4250d87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720967336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1720967336
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2219584520
Short name T758
Test name
Test status
Simulation time 487754333027 ps
CPU time 1178.49 seconds
Started Jul 29 05:40:53 PM PDT 24
Finished Jul 29 06:00:32 PM PDT 24
Peak memory 201428 kb
Host smart-8d32fb50-2449-49d3-90ff-30a9b2a7727d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219584520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2219584520
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1271783299
Short name T733
Test name
Test status
Simulation time 166921662681 ps
CPU time 91.76 seconds
Started Jul 29 05:40:45 PM PDT 24
Finished Jul 29 05:42:16 PM PDT 24
Peak memory 201436 kb
Host smart-bf5ef208-4ea1-43e6-9ede-b0c295e75df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271783299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1271783299
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2163445409
Short name T678
Test name
Test status
Simulation time 164926040303 ps
CPU time 42.71 seconds
Started Jul 29 05:40:50 PM PDT 24
Finished Jul 29 05:41:33 PM PDT 24
Peak memory 201420 kb
Host smart-5ff4acf2-5804-4a90-9caf-5d79d195be38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163445409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2163445409
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2713209015
Short name T332
Test name
Test status
Simulation time 416884404961 ps
CPU time 582.84 seconds
Started Jul 29 05:40:53 PM PDT 24
Finished Jul 29 05:50:36 PM PDT 24
Peak memory 201452 kb
Host smart-0617fcba-03e4-40d3-a8be-c0a948967b6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713209015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2713209015
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3509164648
Short name T609
Test name
Test status
Simulation time 90772599599 ps
CPU time 482.22 seconds
Started Jul 29 05:40:56 PM PDT 24
Finished Jul 29 05:48:59 PM PDT 24
Peak memory 201896 kb
Host smart-4044ba1b-f4a3-4b58-b2be-029a2aedbfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509164648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3509164648
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3960350392
Short name T471
Test name
Test status
Simulation time 37245918038 ps
CPU time 85.45 seconds
Started Jul 29 05:40:55 PM PDT 24
Finished Jul 29 05:42:20 PM PDT 24
Peak memory 201380 kb
Host smart-d76c5db5-c977-4e48-8946-5dd509b0ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960350392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3960350392
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3409288168
Short name T721
Test name
Test status
Simulation time 3976240313 ps
CPU time 1.4 seconds
Started Jul 29 05:40:55 PM PDT 24
Finished Jul 29 05:40:56 PM PDT 24
Peak memory 201324 kb
Host smart-e431133b-3fa9-46a8-945a-661f4ac45eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409288168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3409288168
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.769319209
Short name T570
Test name
Test status
Simulation time 5626624642 ps
CPU time 4.15 seconds
Started Jul 29 05:40:43 PM PDT 24
Finished Jul 29 05:40:48 PM PDT 24
Peak memory 201348 kb
Host smart-b20fc497-14f4-4580-a12c-b84b9a6aa506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769319209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.769319209
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.363501559
Short name T101
Test name
Test status
Simulation time 247849050663 ps
CPU time 436.65 seconds
Started Jul 29 05:40:58 PM PDT 24
Finished Jul 29 05:48:15 PM PDT 24
Peak memory 201816 kb
Host smart-ced5104a-d6bb-40d7-a302-daa57b65c3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363501559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
363501559
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.147656783
Short name T402
Test name
Test status
Simulation time 34944307384 ps
CPU time 82.94 seconds
Started Jul 29 05:40:59 PM PDT 24
Finished Jul 29 05:42:22 PM PDT 24
Peak memory 201628 kb
Host smart-d27172e1-d14d-4445-8a64-0c3077ccca49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147656783 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.147656783
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1806620804
Short name T654
Test name
Test status
Simulation time 504208442 ps
CPU time 1.2 seconds
Started Jul 29 05:41:07 PM PDT 24
Finished Jul 29 05:41:08 PM PDT 24
Peak memory 201248 kb
Host smart-fcf3f446-b6d4-47f4-966e-85e86cde7004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806620804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1806620804
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.525413286
Short name T756
Test name
Test status
Simulation time 179995228684 ps
CPU time 436.94 seconds
Started Jul 29 05:41:01 PM PDT 24
Finished Jul 29 05:48:18 PM PDT 24
Peak memory 201452 kb
Host smart-0ec53d7d-d241-44f5-8a33-a4957eb46ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525413286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.525413286
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2975705373
Short name T267
Test name
Test status
Simulation time 335302981996 ps
CPU time 722.95 seconds
Started Jul 29 05:40:53 PM PDT 24
Finished Jul 29 05:52:56 PM PDT 24
Peak memory 201460 kb
Host smart-5dbb35b5-40fd-45b8-9fa0-fe72ff15efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975705373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2975705373
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2293264813
Short name T378
Test name
Test status
Simulation time 490705618410 ps
CPU time 1120.84 seconds
Started Jul 29 05:40:56 PM PDT 24
Finished Jul 29 05:59:37 PM PDT 24
Peak memory 201484 kb
Host smart-9e57801b-f8a3-45ed-b35f-01ab7c39d910
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293264813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2293264813
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.895365738
Short name T276
Test name
Test status
Simulation time 321155611501 ps
CPU time 354.72 seconds
Started Jul 29 05:40:55 PM PDT 24
Finished Jul 29 05:46:50 PM PDT 24
Peak memory 201592 kb
Host smart-664d5ec1-003f-4d7a-8646-93eccbdc31c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895365738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.895365738
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3949060607
Short name T501
Test name
Test status
Simulation time 479868171510 ps
CPU time 566.61 seconds
Started Jul 29 05:40:57 PM PDT 24
Finished Jul 29 05:50:23 PM PDT 24
Peak memory 201412 kb
Host smart-aa9b33cc-4c90-4f07-9bbe-254e2b5681c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949060607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3949060607
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2425337307
Short name T387
Test name
Test status
Simulation time 411633477886 ps
CPU time 1012.54 seconds
Started Jul 29 05:41:00 PM PDT 24
Finished Jul 29 05:57:53 PM PDT 24
Peak memory 201436 kb
Host smart-85bc15b4-ff3b-42b4-9d92-0fb698dba1f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425337307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2425337307
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3675417578
Short name T90
Test name
Test status
Simulation time 62442126455 ps
CPU time 247.18 seconds
Started Jul 29 05:41:03 PM PDT 24
Finished Jul 29 05:45:10 PM PDT 24
Peak memory 201800 kb
Host smart-1197d7cc-3854-4c5b-a327-0cbd0375e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675417578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3675417578
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3724516849
Short name T505
Test name
Test status
Simulation time 39549261302 ps
CPU time 22.65 seconds
Started Jul 29 05:41:04 PM PDT 24
Finished Jul 29 05:41:26 PM PDT 24
Peak memory 201300 kb
Host smart-1c529ed6-c030-4573-bc5c-bedaec9d763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724516849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3724516849
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2615030788
Short name T713
Test name
Test status
Simulation time 4052458939 ps
CPU time 3.3 seconds
Started Jul 29 05:41:00 PM PDT 24
Finished Jul 29 05:41:04 PM PDT 24
Peak memory 201308 kb
Host smart-219ea08e-e4ca-447f-8fc5-bc827345de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615030788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2615030788
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.575971482
Short name T781
Test name
Test status
Simulation time 5630313241 ps
CPU time 3.09 seconds
Started Jul 29 05:40:56 PM PDT 24
Finished Jul 29 05:40:59 PM PDT 24
Peak memory 201340 kb
Host smart-b8d5a9b9-0ee7-4da3-bcd6-44aa0fa22a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575971482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.575971482
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1673849989
Short name T772
Test name
Test status
Simulation time 191420020933 ps
CPU time 114.47 seconds
Started Jul 29 05:41:00 PM PDT 24
Finished Jul 29 05:42:55 PM PDT 24
Peak memory 201364 kb
Host smart-0cedc56a-06f4-4d82-82b9-94ab943eab94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673849989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1673849989
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4070860949
Short name T679
Test name
Test status
Simulation time 97248944678 ps
CPU time 101.71 seconds
Started Jul 29 05:41:00 PM PDT 24
Finished Jul 29 05:42:42 PM PDT 24
Peak memory 209772 kb
Host smart-0ed30edd-bd91-4ed8-8364-5d854614b01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070860949 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4070860949
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.103912125
Short name T346
Test name
Test status
Simulation time 487581458 ps
CPU time 1.14 seconds
Started Jul 29 05:41:10 PM PDT 24
Finished Jul 29 05:41:12 PM PDT 24
Peak memory 201176 kb
Host smart-3ba24bef-4f47-4e61-9546-c7b10f65b9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103912125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.103912125
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.865534591
Short name T416
Test name
Test status
Simulation time 163504099243 ps
CPU time 362.61 seconds
Started Jul 29 05:41:13 PM PDT 24
Finished Jul 29 05:47:16 PM PDT 24
Peak memory 201452 kb
Host smart-8daf9780-79f7-46a7-be3d-12b51d00fa2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865534591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.865534591
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3541197741
Short name T556
Test name
Test status
Simulation time 543185101768 ps
CPU time 1240.67 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 06:01:52 PM PDT 24
Peak memory 201464 kb
Host smart-b6a85be3-cd8e-49b3-9571-f367f025fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541197741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3541197741
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2335503360
Short name T412
Test name
Test status
Simulation time 338981210722 ps
CPU time 701.18 seconds
Started Jul 29 05:41:08 PM PDT 24
Finished Jul 29 05:52:49 PM PDT 24
Peak memory 201448 kb
Host smart-041ce370-2682-463c-a3c7-6573538618b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335503360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2335503360
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.964021860
Short name T1
Test name
Test status
Simulation time 328468000322 ps
CPU time 244.45 seconds
Started Jul 29 05:41:08 PM PDT 24
Finished Jul 29 05:45:13 PM PDT 24
Peak memory 201440 kb
Host smart-80e75983-1165-4a80-881e-6f8dffb1b149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964021860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.964021860
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3755471363
Short name T474
Test name
Test status
Simulation time 166307703033 ps
CPU time 92.54 seconds
Started Jul 29 05:41:07 PM PDT 24
Finished Jul 29 05:42:40 PM PDT 24
Peak memory 201316 kb
Host smart-e49811d1-4ed4-4c9c-8e40-348703cd09ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755471363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3755471363
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1347947194
Short name T489
Test name
Test status
Simulation time 375978362287 ps
CPU time 221.63 seconds
Started Jul 29 05:41:08 PM PDT 24
Finished Jul 29 05:44:50 PM PDT 24
Peak memory 201680 kb
Host smart-3880208d-2dd4-4adc-9e48-b2a51df79687
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347947194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1347947194
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.66510228
Short name T456
Test name
Test status
Simulation time 210535546859 ps
CPU time 118.27 seconds
Started Jul 29 05:41:08 PM PDT 24
Finished Jul 29 05:43:07 PM PDT 24
Peak memory 201436 kb
Host smart-b1744f5b-234d-486a-a665-7d58334ddb42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66510228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
dc_ctrl_filters_wakeup_fixed.66510228
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1565947683
Short name T720
Test name
Test status
Simulation time 117976030683 ps
CPU time 487.62 seconds
Started Jul 29 05:41:12 PM PDT 24
Finished Jul 29 05:49:20 PM PDT 24
Peak memory 201828 kb
Host smart-2057d290-0b55-47b2-9e12-c3cc31e46119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565947683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1565947683
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3413934045
Short name T762
Test name
Test status
Simulation time 41420215324 ps
CPU time 91.11 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:42:42 PM PDT 24
Peak memory 201356 kb
Host smart-3025c864-52a8-42d7-b6a8-aac0d2368b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413934045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3413934045
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2385696889
Short name T461
Test name
Test status
Simulation time 3977738627 ps
CPU time 10.09 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:41:21 PM PDT 24
Peak memory 201392 kb
Host smart-c5f111a4-f4a6-4007-b69a-7eee327ae523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385696889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2385696889
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3525506585
Short name T376
Test name
Test status
Simulation time 5785726697 ps
CPU time 7.3 seconds
Started Jul 29 05:41:09 PM PDT 24
Finished Jul 29 05:41:16 PM PDT 24
Peak memory 201372 kb
Host smart-fb0fa2ee-c013-4555-9874-70f3b211af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525506585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3525506585
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1095556663
Short name T404
Test name
Test status
Simulation time 366721878081 ps
CPU time 224.87 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:44:56 PM PDT 24
Peak memory 201460 kb
Host smart-1686f376-041e-41a4-a44b-1b73d9137581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095556663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1095556663
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2211279130
Short name T698
Test name
Test status
Simulation time 215459461376 ps
CPU time 404.82 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:47:56 PM PDT 24
Peak memory 210420 kb
Host smart-d86eab53-d8bc-4512-b0d8-f00e0b0c3c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211279130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2211279130
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1671114105
Short name T451
Test name
Test status
Simulation time 507295069 ps
CPU time 1.13 seconds
Started Jul 29 05:41:23 PM PDT 24
Finished Jul 29 05:41:25 PM PDT 24
Peak memory 201240 kb
Host smart-52f33282-8e4a-4b54-9eab-046bb44e74d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671114105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1671114105
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.449118525
Short name T305
Test name
Test status
Simulation time 357436578692 ps
CPU time 251.93 seconds
Started Jul 29 05:41:19 PM PDT 24
Finished Jul 29 05:45:31 PM PDT 24
Peak memory 201324 kb
Host smart-3d355b6f-7fa9-41a0-aa22-c352a56e846f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449118525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.449118525
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2503145654
Short name T176
Test name
Test status
Simulation time 385952844727 ps
CPU time 158.09 seconds
Started Jul 29 05:41:20 PM PDT 24
Finished Jul 29 05:43:58 PM PDT 24
Peak memory 201376 kb
Host smart-0fc3483c-4de6-4a93-bbb3-d8b82dbbe929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503145654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2503145654
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1678029849
Short name T259
Test name
Test status
Simulation time 163327195153 ps
CPU time 355.04 seconds
Started Jul 29 05:41:12 PM PDT 24
Finished Jul 29 05:47:08 PM PDT 24
Peak memory 201456 kb
Host smart-667c5461-13c9-48de-bd54-0a599bd69f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678029849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1678029849
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.464676872
Short name T341
Test name
Test status
Simulation time 331979429152 ps
CPU time 381.09 seconds
Started Jul 29 05:41:18 PM PDT 24
Finished Jul 29 05:47:39 PM PDT 24
Peak memory 201440 kb
Host smart-82d2e558-1334-4d7c-a870-eef1b1c23416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464676872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.464676872
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.453191612
Short name T759
Test name
Test status
Simulation time 325271325359 ps
CPU time 62.47 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:42:13 PM PDT 24
Peak memory 201444 kb
Host smart-099aa2da-a088-4adc-94c3-3d3c5b77f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453191612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.453191612
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.276563096
Short name T398
Test name
Test status
Simulation time 163660106120 ps
CPU time 103.2 seconds
Started Jul 29 05:41:12 PM PDT 24
Finished Jul 29 05:42:55 PM PDT 24
Peak memory 201396 kb
Host smart-b9a2815c-ac9b-44ea-b272-979efbea81eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276563096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.276563096
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.100160395
Short name T475
Test name
Test status
Simulation time 355635438901 ps
CPU time 787.6 seconds
Started Jul 29 05:41:17 PM PDT 24
Finished Jul 29 05:54:25 PM PDT 24
Peak memory 201420 kb
Host smart-61a038cf-1050-4d13-ae40-d95d6fbc0ab6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100160395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.100160395
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2975717474
Short name T397
Test name
Test status
Simulation time 603125224835 ps
CPU time 1381.56 seconds
Started Jul 29 05:41:19 PM PDT 24
Finished Jul 29 06:04:21 PM PDT 24
Peak memory 201400 kb
Host smart-220b3982-3563-478e-b1b1-0cd4117ba7f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975717474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2975717474
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3077149840
Short name T673
Test name
Test status
Simulation time 94947056967 ps
CPU time 439.46 seconds
Started Jul 29 05:41:19 PM PDT 24
Finished Jul 29 05:48:39 PM PDT 24
Peak memory 201776 kb
Host smart-cf6eb7dc-00ab-46d0-89f8-168e8513b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077149840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3077149840
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.224413866
Short name T714
Test name
Test status
Simulation time 39387056234 ps
CPU time 85.09 seconds
Started Jul 29 05:41:19 PM PDT 24
Finished Jul 29 05:42:44 PM PDT 24
Peak memory 201268 kb
Host smart-42443ee2-fda0-40e4-9d7d-dd0369600b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224413866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.224413866
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.470025597
Short name T400
Test name
Test status
Simulation time 5344705089 ps
CPU time 6.68 seconds
Started Jul 29 05:41:18 PM PDT 24
Finished Jul 29 05:41:25 PM PDT 24
Peak memory 201316 kb
Host smart-5f8a0a57-276a-4840-8bee-93cb6bb10d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470025597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.470025597
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.860889989
Short name T428
Test name
Test status
Simulation time 5735127774 ps
CPU time 4.24 seconds
Started Jul 29 05:41:11 PM PDT 24
Finished Jul 29 05:41:16 PM PDT 24
Peak memory 201304 kb
Host smart-d6f656d1-41c8-4328-a6c7-1702de93935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860889989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.860889989
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3535371933
Short name T506
Test name
Test status
Simulation time 9527914415 ps
CPU time 12.64 seconds
Started Jul 29 05:41:24 PM PDT 24
Finished Jul 29 05:41:37 PM PDT 24
Peak memory 201284 kb
Host smart-ff02cc2d-a629-41fc-bd8e-9980cfb2786f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535371933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3535371933
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1230362895
Short name T768
Test name
Test status
Simulation time 323603426147 ps
CPU time 155.33 seconds
Started Jul 29 05:41:22 PM PDT 24
Finished Jul 29 05:43:57 PM PDT 24
Peak memory 211096 kb
Host smart-72ad4d55-db0d-4ae9-88d8-acdc84a2a0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230362895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1230362895
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1103451972
Short name T61
Test name
Test status
Simulation time 326261497 ps
CPU time 0.77 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:41:28 PM PDT 24
Peak memory 201228 kb
Host smart-7bb88dbf-4753-4c44-9b20-ea75ddf4b99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103451972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1103451972
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4222344078
Short name T11
Test name
Test status
Simulation time 164045062855 ps
CPU time 293.52 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:46:21 PM PDT 24
Peak memory 201316 kb
Host smart-71b8c115-294b-43cb-9e74-0d24055ab719
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222344078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4222344078
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2036624403
Short name T747
Test name
Test status
Simulation time 486783929947 ps
CPU time 623.78 seconds
Started Jul 29 05:41:25 PM PDT 24
Finished Jul 29 05:51:49 PM PDT 24
Peak memory 201428 kb
Host smart-e5e829bd-6b8b-4ec2-bc11-1cb7c9b8be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036624403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2036624403
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1682278224
Short name T722
Test name
Test status
Simulation time 158457241897 ps
CPU time 176.25 seconds
Started Jul 29 05:41:22 PM PDT 24
Finished Jul 29 05:44:19 PM PDT 24
Peak memory 201432 kb
Host smart-9d400c4f-760e-404b-b0ac-430e202ed6b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682278224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1682278224
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3417515238
Short name T347
Test name
Test status
Simulation time 163027349190 ps
CPU time 95.78 seconds
Started Jul 29 05:41:24 PM PDT 24
Finished Jul 29 05:43:00 PM PDT 24
Peak memory 201312 kb
Host smart-82f0fcd2-8da2-4ea9-9d53-f045ebf35ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417515238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3417515238
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2887456367
Short name T529
Test name
Test status
Simulation time 494694248732 ps
CPU time 1214.27 seconds
Started Jul 29 05:41:23 PM PDT 24
Finished Jul 29 06:01:37 PM PDT 24
Peak memory 201416 kb
Host smart-73163215-c152-476f-95a6-1a54c1c2f998
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887456367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2887456367
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3780301933
Short name T368
Test name
Test status
Simulation time 392450189167 ps
CPU time 433.21 seconds
Started Jul 29 05:41:29 PM PDT 24
Finished Jul 29 05:48:42 PM PDT 24
Peak memory 201448 kb
Host smart-fe56bb0d-aad3-4b2b-a500-8c20749cb290
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780301933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3780301933
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1869892503
Short name T547
Test name
Test status
Simulation time 31319329776 ps
CPU time 17.76 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:41:45 PM PDT 24
Peak memory 201336 kb
Host smart-19eb8ef9-e677-4c7d-b26b-5735fb7961bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869892503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1869892503
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1359624232
Short name T632
Test name
Test status
Simulation time 3347238825 ps
CPU time 4.27 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:41:32 PM PDT 24
Peak memory 201348 kb
Host smart-0ac5bdda-25af-43d5-82fb-6c28b68b6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359624232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1359624232
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3233983996
Short name T613
Test name
Test status
Simulation time 5975010824 ps
CPU time 13.78 seconds
Started Jul 29 05:41:23 PM PDT 24
Finished Jul 29 05:41:37 PM PDT 24
Peak memory 201368 kb
Host smart-cbb8097e-7cbd-4c05-925a-2bb81f31847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233983996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3233983996
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2661803359
Short name T261
Test name
Test status
Simulation time 339275642125 ps
CPU time 200.37 seconds
Started Jul 29 05:41:26 PM PDT 24
Finished Jul 29 05:44:46 PM PDT 24
Peak memory 201388 kb
Host smart-b4f634e8-6d39-4642-8e17-05e044b40d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661803359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2661803359
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2156025025
Short name T616
Test name
Test status
Simulation time 76905071619 ps
CPU time 53.5 seconds
Started Jul 29 05:41:28 PM PDT 24
Finished Jul 29 05:42:22 PM PDT 24
Peak memory 210180 kb
Host smart-519a1b3b-295e-4cd8-b884-79eed07bedb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156025025 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2156025025
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2289083559
Short name T440
Test name
Test status
Simulation time 397135075 ps
CPU time 1.1 seconds
Started Jul 29 05:41:45 PM PDT 24
Finished Jul 29 05:41:46 PM PDT 24
Peak memory 201180 kb
Host smart-76c07f03-b048-4541-ae7f-d4ff4f9463db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289083559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2289083559
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2782453008
Short name T179
Test name
Test status
Simulation time 243150486064 ps
CPU time 381.84 seconds
Started Jul 29 05:41:37 PM PDT 24
Finished Jul 29 05:47:59 PM PDT 24
Peak memory 201400 kb
Host smart-7479a649-2518-4948-bf06-adcf9899ce74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782453008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2782453008
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1803467579
Short name T784
Test name
Test status
Simulation time 168933110897 ps
CPU time 387.06 seconds
Started Jul 29 05:41:45 PM PDT 24
Finished Jul 29 05:48:12 PM PDT 24
Peak memory 201400 kb
Host smart-53f42996-bf45-4b4b-b5aa-7e83cc390ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803467579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1803467579
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.4089480726
Short name T311
Test name
Test status
Simulation time 335423307866 ps
CPU time 214.72 seconds
Started Jul 29 05:41:33 PM PDT 24
Finished Jul 29 05:45:07 PM PDT 24
Peak memory 201376 kb
Host smart-78739eb6-1a71-4486-9ec9-e1347799181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089480726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.4089480726
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3548465798
Short name T561
Test name
Test status
Simulation time 166411576611 ps
CPU time 350.22 seconds
Started Jul 29 05:41:33 PM PDT 24
Finished Jul 29 05:47:23 PM PDT 24
Peak memory 201392 kb
Host smart-bd48b062-3ebc-4a1a-b64c-6f130b464ad0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548465798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3548465798
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3117210119
Short name T4
Test name
Test status
Simulation time 330304578901 ps
CPU time 378.75 seconds
Started Jul 29 05:41:32 PM PDT 24
Finished Jul 29 05:47:51 PM PDT 24
Peak memory 201432 kb
Host smart-028302bf-5e6f-40ef-a738-5696d516b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117210119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3117210119
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1292531088
Short name T96
Test name
Test status
Simulation time 324002688089 ps
CPU time 153.36 seconds
Started Jul 29 05:41:34 PM PDT 24
Finished Jul 29 05:44:07 PM PDT 24
Peak memory 201468 kb
Host smart-3bdc81d7-e151-4b9f-8016-6aac1bfd8875
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292531088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1292531088
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2127108696
Short name T525
Test name
Test status
Simulation time 392472896450 ps
CPU time 172.86 seconds
Started Jul 29 05:41:43 PM PDT 24
Finished Jul 29 05:44:36 PM PDT 24
Peak memory 201364 kb
Host smart-594b6f50-9245-4e31-b1e1-358301ed7bee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127108696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2127108696
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3836763381
Short name T760
Test name
Test status
Simulation time 143202996334 ps
CPU time 536.74 seconds
Started Jul 29 05:41:38 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 201840 kb
Host smart-4ab1260b-c211-4734-9988-a6083ba7b93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836763381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3836763381
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.592430368
Short name T636
Test name
Test status
Simulation time 36753933805 ps
CPU time 16.99 seconds
Started Jul 29 05:41:38 PM PDT 24
Finished Jul 29 05:41:55 PM PDT 24
Peak memory 201348 kb
Host smart-526b0bee-04b4-4648-8451-8f7c0b4edaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592430368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.592430368
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1736458102
Short name T739
Test name
Test status
Simulation time 5441975740 ps
CPU time 4.51 seconds
Started Jul 29 05:41:46 PM PDT 24
Finished Jul 29 05:41:50 PM PDT 24
Peak memory 201364 kb
Host smart-8c49a007-c9a2-4644-a6e8-b1ec235fadde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736458102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1736458102
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4062960873
Short name T369
Test name
Test status
Simulation time 5732279612 ps
CPU time 7.71 seconds
Started Jul 29 05:41:33 PM PDT 24
Finished Jul 29 05:41:41 PM PDT 24
Peak memory 201388 kb
Host smart-211b3695-a0d5-4bc2-89f1-355142feda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062960873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4062960873
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1882652626
Short name T228
Test name
Test status
Simulation time 232350830606 ps
CPU time 535.76 seconds
Started Jul 29 05:41:46 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 201428 kb
Host smart-9d3fd83c-a519-4759-875d-dc19f9c17c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882652626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1882652626
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3484907215
Short name T14
Test name
Test status
Simulation time 22500470047 ps
CPU time 46.06 seconds
Started Jul 29 05:41:44 PM PDT 24
Finished Jul 29 05:42:30 PM PDT 24
Peak memory 201716 kb
Host smart-787cd334-a8c4-4f62-8cda-c566c7f66f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484907215 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3484907215
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1985650480
Short name T91
Test name
Test status
Simulation time 441993984 ps
CPU time 1.19 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:40:04 PM PDT 24
Peak memory 201220 kb
Host smart-0c7540dd-419a-4c33-bd4d-cbd632ecf37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985650480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1985650480
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3835200518
Short name T250
Test name
Test status
Simulation time 517793597742 ps
CPU time 492.28 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:48:11 PM PDT 24
Peak memory 201440 kb
Host smart-f7221ffc-f8c4-47d3-9592-f2be1cb66933
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835200518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3835200518
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2457968512
Short name T285
Test name
Test status
Simulation time 488917483302 ps
CPU time 1222.09 seconds
Started Jul 29 05:40:00 PM PDT 24
Finished Jul 29 06:00:22 PM PDT 24
Peak memory 201436 kb
Host smart-8e686e41-e5d2-44b4-8e74-161f0b17734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457968512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2457968512
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4118830306
Short name T788
Test name
Test status
Simulation time 328360716525 ps
CPU time 760.83 seconds
Started Jul 29 05:39:57 PM PDT 24
Finished Jul 29 05:52:38 PM PDT 24
Peak memory 201468 kb
Host smart-1ebe8f82-3fff-4de4-a0bf-4a82df1df85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118830306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4118830306
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.408414728
Short name T703
Test name
Test status
Simulation time 494310765183 ps
CPU time 222.3 seconds
Started Jul 29 05:39:55 PM PDT 24
Finished Jul 29 05:43:37 PM PDT 24
Peak memory 201656 kb
Host smart-5029db58-e1b1-460b-b72d-eb4a24755d41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408414728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.408414728
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.726136271
Short name T318
Test name
Test status
Simulation time 327404370398 ps
CPU time 773.09 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:52:52 PM PDT 24
Peak memory 201452 kb
Host smart-1c4d544e-3313-48ba-8991-bee0aca7a27d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726136271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.726136271
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2057984705
Short name T253
Test name
Test status
Simulation time 360244802709 ps
CPU time 814.65 seconds
Started Jul 29 05:40:00 PM PDT 24
Finished Jul 29 05:53:35 PM PDT 24
Peak memory 201424 kb
Host smart-9dd649d7-5440-45aa-abc7-fa54d1f722fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057984705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2057984705
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3603970962
Short name T405
Test name
Test status
Simulation time 605695681173 ps
CPU time 736.14 seconds
Started Jul 29 05:39:58 PM PDT 24
Finished Jul 29 05:52:15 PM PDT 24
Peak memory 201444 kb
Host smart-cff870c6-bd43-4ef2-972d-2dd2f2ffd835
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603970962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3603970962
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2121608928
Short name T761
Test name
Test status
Simulation time 91005291573 ps
CPU time 436.72 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 05:47:20 PM PDT 24
Peak memory 201836 kb
Host smart-b67f54e0-811f-40c6-826a-431558c8acfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121608928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2121608928
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2250193396
Short name T730
Test name
Test status
Simulation time 39834418790 ps
CPU time 18.18 seconds
Started Jul 29 05:40:04 PM PDT 24
Finished Jul 29 05:40:22 PM PDT 24
Peak memory 201344 kb
Host smart-468ec552-d884-42d6-907a-2d3b6807eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250193396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2250193396
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1857581643
Short name T507
Test name
Test status
Simulation time 4278011924 ps
CPU time 4 seconds
Started Jul 29 05:39:57 PM PDT 24
Finished Jul 29 05:40:01 PM PDT 24
Peak memory 201332 kb
Host smart-1af5f274-b181-445d-b426-321c8f88b283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857581643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1857581643
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1628683545
Short name T57
Test name
Test status
Simulation time 4204018086 ps
CPU time 3 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 05:40:06 PM PDT 24
Peak memory 217128 kb
Host smart-449fcf14-d6c2-4b42-9a69-b8fc1d5956b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628683545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1628683545
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3825927770
Short name T503
Test name
Test status
Simulation time 5884566730 ps
CPU time 6.87 seconds
Started Jul 29 05:40:00 PM PDT 24
Finished Jul 29 05:40:07 PM PDT 24
Peak memory 201368 kb
Host smart-5afb22f1-e454-47e7-b8ee-44241b77f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825927770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3825927770
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1953180370
Short name T567
Test name
Test status
Simulation time 286882538301 ps
CPU time 162.08 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:42:44 PM PDT 24
Peak memory 201460 kb
Host smart-5176f60d-0655-4b61-bb91-e9e4af22c295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953180370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1953180370
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1227560050
Short name T19
Test name
Test status
Simulation time 11029591524 ps
CPU time 23.29 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 05:40:27 PM PDT 24
Peak memory 209848 kb
Host smart-10d93c0a-afa0-47f1-96e5-8e3b3d200785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227560050 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1227560050
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1336643669
Short name T603
Test name
Test status
Simulation time 533059935 ps
CPU time 0.93 seconds
Started Jul 29 05:42:02 PM PDT 24
Finished Jul 29 05:42:03 PM PDT 24
Peak memory 201184 kb
Host smart-3024b98d-73c4-45b8-889b-0721635da21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336643669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1336643669
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.587952411
Short name T769
Test name
Test status
Simulation time 337763194063 ps
CPU time 706.68 seconds
Started Jul 29 05:41:53 PM PDT 24
Finished Jul 29 05:53:40 PM PDT 24
Peak memory 201408 kb
Host smart-064ab2b2-3055-44f3-9885-66fae751de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587952411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.587952411
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1013448231
Short name T313
Test name
Test status
Simulation time 164298362272 ps
CPU time 105.38 seconds
Started Jul 29 05:41:47 PM PDT 24
Finished Jul 29 05:43:33 PM PDT 24
Peak memory 201428 kb
Host smart-3da010d1-3703-482c-9927-cd2d94b5ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013448231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1013448231
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.10958958
Short name T168
Test name
Test status
Simulation time 490920042027 ps
CPU time 330.13 seconds
Started Jul 29 05:41:50 PM PDT 24
Finished Jul 29 05:47:20 PM PDT 24
Peak memory 201412 kb
Host smart-270842f6-b2f8-47f2-b204-9b7273b0eb7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt
_fixed.10958958
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1212042052
Short name T541
Test name
Test status
Simulation time 330459132717 ps
CPU time 70.39 seconds
Started Jul 29 05:41:48 PM PDT 24
Finished Jul 29 05:42:58 PM PDT 24
Peak memory 201440 kb
Host smart-0976e422-58b5-408b-94b8-8583d6470d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212042052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1212042052
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1083150115
Short name T360
Test name
Test status
Simulation time 496008309914 ps
CPU time 274.31 seconds
Started Jul 29 05:41:50 PM PDT 24
Finished Jul 29 05:46:24 PM PDT 24
Peak memory 201400 kb
Host smart-f9e4920c-5bde-49b5-a373-711004901e90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083150115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1083150115
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2219495815
Short name T663
Test name
Test status
Simulation time 355309220032 ps
CPU time 802.57 seconds
Started Jul 29 05:41:47 PM PDT 24
Finished Jul 29 05:55:10 PM PDT 24
Peak memory 201468 kb
Host smart-c781801b-a046-4c6d-abd4-1a0ef0560317
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219495815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2219495815
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3204006806
Short name T92
Test name
Test status
Simulation time 405573211671 ps
CPU time 369.66 seconds
Started Jul 29 05:41:46 PM PDT 24
Finished Jul 29 05:47:55 PM PDT 24
Peak memory 201588 kb
Host smart-999e7de4-f3bf-453f-8846-bac2eb035297
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204006806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3204006806
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2616084193
Short name T599
Test name
Test status
Simulation time 158483911097 ps
CPU time 581.44 seconds
Started Jul 29 05:41:58 PM PDT 24
Finished Jul 29 05:51:39 PM PDT 24
Peak memory 201892 kb
Host smart-487c3cc3-21a2-45b3-9b0d-919ae3dd072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616084193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2616084193
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4058802802
Short name T778
Test name
Test status
Simulation time 35015799238 ps
CPU time 35.76 seconds
Started Jul 29 05:41:58 PM PDT 24
Finished Jul 29 05:42:34 PM PDT 24
Peak memory 201352 kb
Host smart-914f2269-6962-4dbc-a2b7-75cda4bed0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058802802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4058802802
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1820766869
Short name T415
Test name
Test status
Simulation time 4618078786 ps
CPU time 3.51 seconds
Started Jul 29 05:41:54 PM PDT 24
Finished Jul 29 05:41:57 PM PDT 24
Peak memory 201272 kb
Host smart-a89b443b-ef65-4c00-a264-77761270bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820766869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1820766869
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.298109618
Short name T574
Test name
Test status
Simulation time 5969340352 ps
CPU time 14.39 seconds
Started Jul 29 05:41:44 PM PDT 24
Finished Jul 29 05:41:58 PM PDT 24
Peak memory 201376 kb
Host smart-46dad142-2b90-4969-b9b8-26c2a10de552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298109618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.298109618
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1384418551
Short name T512
Test name
Test status
Simulation time 131439250693 ps
CPU time 368.96 seconds
Started Jul 29 05:41:57 PM PDT 24
Finished Jul 29 05:48:06 PM PDT 24
Peak memory 210108 kb
Host smart-5afe7497-5146-4ff3-a39b-bf5d09064bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384418551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1384418551
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.837270127
Short name T486
Test name
Test status
Simulation time 23445325451 ps
CPU time 53.24 seconds
Started Jul 29 05:41:59 PM PDT 24
Finished Jul 29 05:42:53 PM PDT 24
Peak memory 209772 kb
Host smart-b1893d80-8e1a-4b79-8c39-00e1f32b3030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837270127 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.837270127
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2728556802
Short name T674
Test name
Test status
Simulation time 419058312 ps
CPU time 1.57 seconds
Started Jul 29 05:42:13 PM PDT 24
Finished Jul 29 05:42:14 PM PDT 24
Peak memory 201248 kb
Host smart-6aa850f6-310e-40b3-95d0-a355223831c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728556802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2728556802
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3425555768
Short name T516
Test name
Test status
Simulation time 389546308608 ps
CPU time 920 seconds
Started Jul 29 05:42:09 PM PDT 24
Finished Jul 29 05:57:29 PM PDT 24
Peak memory 201368 kb
Host smart-5f1a38d3-e4d6-4e14-9869-ab0cbf48579e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425555768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3425555768
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.336111817
Short name T481
Test name
Test status
Simulation time 325353543417 ps
CPU time 135.81 seconds
Started Jul 29 05:42:09 PM PDT 24
Finished Jul 29 05:44:25 PM PDT 24
Peak memory 201460 kb
Host smart-212d6ee0-7389-473b-9c45-bd3706575203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336111817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.336111817
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4128660210
Short name T584
Test name
Test status
Simulation time 334915664780 ps
CPU time 193.46 seconds
Started Jul 29 05:42:03 PM PDT 24
Finished Jul 29 05:45:16 PM PDT 24
Peak memory 201424 kb
Host smart-5d76b3a0-496e-4745-8472-1b4a8651e097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128660210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4128660210
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1030249513
Short name T422
Test name
Test status
Simulation time 325735871087 ps
CPU time 365.8 seconds
Started Jul 29 05:42:04 PM PDT 24
Finished Jul 29 05:48:10 PM PDT 24
Peak memory 201412 kb
Host smart-589cd4a4-b959-455b-91ff-1d0225de3a6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030249513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1030249513
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2403319560
Short name T421
Test name
Test status
Simulation time 483556719523 ps
CPU time 546.42 seconds
Started Jul 29 05:42:03 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 201440 kb
Host smart-5b1e3e53-90db-4cf4-84c7-15d58316c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403319560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2403319560
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1526775176
Short name T356
Test name
Test status
Simulation time 161549948330 ps
CPU time 180.2 seconds
Started Jul 29 05:42:02 PM PDT 24
Finished Jul 29 05:45:03 PM PDT 24
Peak memory 201468 kb
Host smart-2a9eeafc-def6-4788-a94b-6b30092b3623
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526775176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1526775176
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3394450012
Short name T278
Test name
Test status
Simulation time 696248402091 ps
CPU time 1538.72 seconds
Started Jul 29 05:42:02 PM PDT 24
Finished Jul 29 06:07:41 PM PDT 24
Peak memory 201444 kb
Host smart-17ab49af-a39b-482c-b85e-46fa73b70e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394450012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3394450012
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2722258939
Short name T696
Test name
Test status
Simulation time 409234219659 ps
CPU time 159.46 seconds
Started Jul 29 05:42:08 PM PDT 24
Finished Jul 29 05:44:48 PM PDT 24
Peak memory 201436 kb
Host smart-d798290f-028c-4432-8eed-a3250331c19c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722258939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2722258939
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2183640350
Short name T573
Test name
Test status
Simulation time 132465090673 ps
CPU time 621.96 seconds
Started Jul 29 05:42:09 PM PDT 24
Finished Jul 29 05:52:31 PM PDT 24
Peak memory 201840 kb
Host smart-47546152-4df1-4a9a-afbe-d00e8a85f22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183640350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2183640350
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1774506099
Short name T390
Test name
Test status
Simulation time 28066090898 ps
CPU time 32.27 seconds
Started Jul 29 05:42:09 PM PDT 24
Finished Jul 29 05:42:41 PM PDT 24
Peak memory 201352 kb
Host smart-e4a29f61-b0b0-4be2-afb8-dad419eaea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774506099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1774506099
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3635325309
Short name T459
Test name
Test status
Simulation time 4737978026 ps
CPU time 3.06 seconds
Started Jul 29 05:42:07 PM PDT 24
Finished Jul 29 05:42:10 PM PDT 24
Peak memory 201344 kb
Host smart-0c478914-8bef-439d-8d98-d617c6b71613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635325309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3635325309
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2859213591
Short name T410
Test name
Test status
Simulation time 5989779416 ps
CPU time 4.29 seconds
Started Jul 29 05:42:01 PM PDT 24
Finished Jul 29 05:42:06 PM PDT 24
Peak memory 201304 kb
Host smart-41845c7f-147f-4f64-9294-246a8e6a5231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859213591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2859213591
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1343068223
Short name T209
Test name
Test status
Simulation time 123404662992 ps
CPU time 392.31 seconds
Started Jul 29 05:42:08 PM PDT 24
Finished Jul 29 05:48:41 PM PDT 24
Peak memory 210052 kb
Host smart-f75042b7-427a-42b3-a103-5c1d82bfa482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343068223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1343068223
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2199335976
Short name T622
Test name
Test status
Simulation time 10565018132 ps
CPU time 7.05 seconds
Started Jul 29 05:42:07 PM PDT 24
Finished Jul 29 05:42:14 PM PDT 24
Peak memory 209780 kb
Host smart-5ce0d47f-b5ab-429a-96e0-2a006596671c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199335976 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2199335976
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2901875528
Short name T545
Test name
Test status
Simulation time 348252062 ps
CPU time 1.34 seconds
Started Jul 29 05:42:22 PM PDT 24
Finished Jul 29 05:42:23 PM PDT 24
Peak memory 201228 kb
Host smart-a44753c8-3b41-4f87-a742-e11c4be53678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901875528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2901875528
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3079847939
Short name T282
Test name
Test status
Simulation time 162827368882 ps
CPU time 18.82 seconds
Started Jul 29 05:42:18 PM PDT 24
Finished Jul 29 05:42:37 PM PDT 24
Peak memory 201376 kb
Host smart-7ce6f2bb-139c-4769-baca-6f16475ed974
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079847939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3079847939
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1757788048
Short name T708
Test name
Test status
Simulation time 163243698251 ps
CPU time 181.47 seconds
Started Jul 29 05:42:18 PM PDT 24
Finished Jul 29 05:45:20 PM PDT 24
Peak memory 201484 kb
Host smart-13431900-bccc-445e-92ca-edb76650c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757788048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1757788048
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.867303742
Short name T686
Test name
Test status
Simulation time 329298351763 ps
CPU time 795.24 seconds
Started Jul 29 05:42:19 PM PDT 24
Finished Jul 29 05:55:34 PM PDT 24
Peak memory 201500 kb
Host smart-75af45c6-c7f6-4e65-951c-9bd3948d828c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=867303742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.867303742
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1741116444
Short name T502
Test name
Test status
Simulation time 323030015807 ps
CPU time 379.22 seconds
Started Jul 29 05:42:17 PM PDT 24
Finished Jul 29 05:48:36 PM PDT 24
Peak memory 201416 kb
Host smart-2ffd6e92-cd7a-4e9d-9d0d-906682bb9d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741116444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1741116444
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2943989711
Short name T136
Test name
Test status
Simulation time 494692235108 ps
CPU time 292.46 seconds
Started Jul 29 05:42:18 PM PDT 24
Finished Jul 29 05:47:11 PM PDT 24
Peak memory 201432 kb
Host smart-3ae3c586-8f72-4ca0-be01-af28d2a5a8b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943989711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2943989711
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.104117348
Short name T141
Test name
Test status
Simulation time 373753512202 ps
CPU time 809.19 seconds
Started Jul 29 05:42:19 PM PDT 24
Finished Jul 29 05:55:48 PM PDT 24
Peak memory 201420 kb
Host smart-eede91e1-6057-487f-bb1d-e34ae9d0acd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104117348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.104117348
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1840777200
Short name T569
Test name
Test status
Simulation time 406622479768 ps
CPU time 468.58 seconds
Started Jul 29 05:42:20 PM PDT 24
Finished Jul 29 05:50:09 PM PDT 24
Peak memory 201376 kb
Host smart-75f282be-7169-4241-8563-54b6ab952793
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840777200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1840777200
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2133026259
Short name T452
Test name
Test status
Simulation time 75231852831 ps
CPU time 301.4 seconds
Started Jul 29 05:42:22 PM PDT 24
Finished Jul 29 05:47:24 PM PDT 24
Peak memory 201964 kb
Host smart-ab64c660-3690-4ca5-8d02-5328c40ec856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133026259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2133026259
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3459819487
Short name T469
Test name
Test status
Simulation time 37043585093 ps
CPU time 42.77 seconds
Started Jul 29 05:42:18 PM PDT 24
Finished Jul 29 05:43:01 PM PDT 24
Peak memory 201380 kb
Host smart-9b327efb-1cfa-415f-b9c2-f7e485160c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459819487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3459819487
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1069955994
Short name T365
Test name
Test status
Simulation time 4999439522 ps
CPU time 11.69 seconds
Started Jul 29 05:42:20 PM PDT 24
Finished Jul 29 05:42:32 PM PDT 24
Peak memory 201272 kb
Host smart-1f38d40b-c22d-4ff9-9767-420c29d7fe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069955994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1069955994
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2755248559
Short name T326
Test name
Test status
Simulation time 5906599763 ps
CPU time 4.25 seconds
Started Jul 29 05:42:11 PM PDT 24
Finished Jul 29 05:42:15 PM PDT 24
Peak memory 201368 kb
Host smart-95727908-5e66-452d-a997-62ce71fd0dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755248559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2755248559
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1876284244
Short name T211
Test name
Test status
Simulation time 91163251820 ps
CPU time 465.67 seconds
Started Jul 29 05:42:22 PM PDT 24
Finished Jul 29 05:50:08 PM PDT 24
Peak memory 201792 kb
Host smart-48c75473-805e-417e-a5fc-a932a9fefc17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876284244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1876284244
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.199815928
Short name T460
Test name
Test status
Simulation time 37803126927 ps
CPU time 108.02 seconds
Started Jul 29 05:42:23 PM PDT 24
Finished Jul 29 05:44:11 PM PDT 24
Peak memory 210148 kb
Host smart-e2e04070-6624-4295-96dd-57b185fe65c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199815928 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.199815928
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1387718856
Short name T488
Test name
Test status
Simulation time 462222681 ps
CPU time 0.86 seconds
Started Jul 29 05:42:37 PM PDT 24
Finished Jul 29 05:42:38 PM PDT 24
Peak memory 201248 kb
Host smart-b8047b8a-047d-43a6-a146-6e6bded1ef7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387718856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1387718856
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.266956164
Short name T787
Test name
Test status
Simulation time 509262674183 ps
CPU time 1215.69 seconds
Started Jul 29 05:42:32 PM PDT 24
Finished Jul 29 06:02:48 PM PDT 24
Peak memory 201456 kb
Host smart-1434170a-722b-4948-9f60-0e17c8d331e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266956164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.266956164
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3501091707
Short name T291
Test name
Test status
Simulation time 492941131213 ps
CPU time 593.92 seconds
Started Jul 29 05:42:27 PM PDT 24
Finished Jul 29 05:52:21 PM PDT 24
Peak memory 201444 kb
Host smart-3ad24a69-83ec-4d41-80fd-b63ff57f2c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501091707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3501091707
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2662967222
Short name T601
Test name
Test status
Simulation time 322680682890 ps
CPU time 760.72 seconds
Started Jul 29 05:42:27 PM PDT 24
Finished Jul 29 05:55:08 PM PDT 24
Peak memory 201508 kb
Host smart-5765e2ac-671e-4cb7-a522-730e1b9b8d4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662967222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2662967222
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2586218415
Short name T129
Test name
Test status
Simulation time 166696460961 ps
CPU time 397.37 seconds
Started Jul 29 05:42:26 PM PDT 24
Finished Jul 29 05:49:03 PM PDT 24
Peak memory 201384 kb
Host smart-497a01f6-785a-4fb2-aaa6-eb8c446bc65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586218415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2586218415
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3771103220
Short name T618
Test name
Test status
Simulation time 489366564111 ps
CPU time 523.61 seconds
Started Jul 29 05:42:26 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 201468 kb
Host smart-15c4cb96-adc9-4bb3-81c9-5c18748dd972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771103220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3771103220
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3288240204
Short name T736
Test name
Test status
Simulation time 401767828130 ps
CPU time 910.69 seconds
Started Jul 29 05:42:32 PM PDT 24
Finished Jul 29 05:57:43 PM PDT 24
Peak memory 201444 kb
Host smart-500432db-9ee4-435d-a64a-a9e5a63047f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288240204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3288240204
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.519952961
Short name T205
Test name
Test status
Simulation time 136161608804 ps
CPU time 628.46 seconds
Started Jul 29 05:42:32 PM PDT 24
Finished Jul 29 05:53:01 PM PDT 24
Peak memory 201836 kb
Host smart-ec279831-5ecd-4872-bdf0-8c97fe1c4868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519952961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.519952961
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1035323405
Short name T650
Test name
Test status
Simulation time 22763866701 ps
CPU time 53.67 seconds
Started Jul 29 05:42:33 PM PDT 24
Finished Jul 29 05:43:27 PM PDT 24
Peak memory 201340 kb
Host smart-326a053e-357f-4e28-8826-b9a81d532a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035323405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1035323405
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.329702431
Short name T352
Test name
Test status
Simulation time 5351882323 ps
CPU time 3.94 seconds
Started Jul 29 05:42:32 PM PDT 24
Finished Jul 29 05:42:36 PM PDT 24
Peak memory 201352 kb
Host smart-56abf44f-e521-4050-a113-9c5fa2c22ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329702431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.329702431
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3536137742
Short name T361
Test name
Test status
Simulation time 5922674695 ps
CPU time 14.33 seconds
Started Jul 29 05:42:22 PM PDT 24
Finished Jul 29 05:42:36 PM PDT 24
Peak memory 201312 kb
Host smart-140be0ac-c522-4867-ab9a-0948c6f9c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536137742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3536137742
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2053957854
Short name T680
Test name
Test status
Simulation time 298531002062 ps
CPU time 418.08 seconds
Started Jul 29 05:42:38 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 209960 kb
Host smart-c0e68c8c-1648-4466-8476-dd8b0b8da7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053957854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2053957854
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.359808852
Short name T98
Test name
Test status
Simulation time 93606439574 ps
CPU time 58.65 seconds
Started Jul 29 05:42:32 PM PDT 24
Finished Jul 29 05:43:31 PM PDT 24
Peak memory 209780 kb
Host smart-b77a3018-569c-4853-a307-eac38d5f9979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359808852 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.359808852
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2569859710
Short name T62
Test name
Test status
Simulation time 482441854 ps
CPU time 0.89 seconds
Started Jul 29 05:42:48 PM PDT 24
Finished Jul 29 05:42:49 PM PDT 24
Peak memory 201184 kb
Host smart-cab435b7-218f-44bf-9c47-67d04e894d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569859710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2569859710
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.811301181
Short name T270
Test name
Test status
Simulation time 527197613074 ps
CPU time 295.59 seconds
Started Jul 29 05:42:43 PM PDT 24
Finished Jul 29 05:47:39 PM PDT 24
Peak memory 201404 kb
Host smart-6053b711-b297-4183-a435-1700f415727e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811301181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.811301181
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3407877796
Short name T302
Test name
Test status
Simulation time 341800173277 ps
CPU time 222.51 seconds
Started Jul 29 05:42:46 PM PDT 24
Finished Jul 29 05:46:29 PM PDT 24
Peak memory 201596 kb
Host smart-1134d41c-6570-4132-80ba-0b4757f5d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407877796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3407877796
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3279517836
Short name T775
Test name
Test status
Simulation time 327140848070 ps
CPU time 176.58 seconds
Started Jul 29 05:42:36 PM PDT 24
Finished Jul 29 05:45:33 PM PDT 24
Peak memory 201516 kb
Host smart-bee78408-de73-466f-8a78-fff1f987ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279517836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3279517836
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3776887235
Short name T433
Test name
Test status
Simulation time 163507291678 ps
CPU time 201.16 seconds
Started Jul 29 05:42:42 PM PDT 24
Finished Jul 29 05:46:04 PM PDT 24
Peak memory 201484 kb
Host smart-168688f5-f6ef-4b16-8f7c-fc1860e50230
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776887235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3776887235
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.528846787
Short name T557
Test name
Test status
Simulation time 164813157035 ps
CPU time 79.11 seconds
Started Jul 29 05:42:38 PM PDT 24
Finished Jul 29 05:43:57 PM PDT 24
Peak memory 201384 kb
Host smart-e52acfc3-0998-40b1-b4e4-048aa726879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528846787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.528846787
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2865680348
Short name T773
Test name
Test status
Simulation time 332907521234 ps
CPU time 768.21 seconds
Started Jul 29 05:42:38 PM PDT 24
Finished Jul 29 05:55:26 PM PDT 24
Peak memory 201436 kb
Host smart-006be343-a0ba-4333-8edf-53205111beb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865680348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2865680348
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3267557936
Short name T638
Test name
Test status
Simulation time 405792042183 ps
CPU time 221.71 seconds
Started Jul 29 05:42:44 PM PDT 24
Finished Jul 29 05:46:26 PM PDT 24
Peak memory 201364 kb
Host smart-c1a923c5-b7bb-4370-a945-c5faed59b5fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267557936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3267557936
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2054428152
Short name T748
Test name
Test status
Simulation time 103115986226 ps
CPU time 407.42 seconds
Started Jul 29 05:42:47 PM PDT 24
Finished Jul 29 05:49:35 PM PDT 24
Peak memory 201824 kb
Host smart-bcfb8478-1740-448f-b31f-968a66c7acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054428152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2054428152
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4064164424
Short name T780
Test name
Test status
Simulation time 32735532254 ps
CPU time 15.02 seconds
Started Jul 29 05:42:47 PM PDT 24
Finished Jul 29 05:43:03 PM PDT 24
Peak memory 201344 kb
Host smart-ecb661cf-9739-429c-af27-24a3b5284a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064164424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4064164424
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.690552639
Short name T742
Test name
Test status
Simulation time 4062035018 ps
CPU time 8.68 seconds
Started Jul 29 05:42:47 PM PDT 24
Finished Jul 29 05:42:56 PM PDT 24
Peak memory 201304 kb
Host smart-b85f8bfb-e753-4da2-b0d5-4e60d6aa2592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690552639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.690552639
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.210816472
Short name T97
Test name
Test status
Simulation time 5789021662 ps
CPU time 4.04 seconds
Started Jul 29 05:42:37 PM PDT 24
Finished Jul 29 05:42:41 PM PDT 24
Peak memory 201360 kb
Host smart-95b62022-9eb5-47ac-b1ac-a24f364b45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210816472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.210816472
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2118346540
Short name T262
Test name
Test status
Simulation time 857306695199 ps
CPU time 1436.49 seconds
Started Jul 29 05:42:46 PM PDT 24
Finished Jul 29 06:06:43 PM PDT 24
Peak memory 201428 kb
Host smart-20aa5563-b9fe-4235-ae6f-cd52dacf13d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118346540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2118346540
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3188939441
Short name T269
Test name
Test status
Simulation time 211478227098 ps
CPU time 122.52 seconds
Started Jul 29 05:42:47 PM PDT 24
Finished Jul 29 05:44:50 PM PDT 24
Peak memory 209792 kb
Host smart-1e243d6c-2f4e-44ae-94d5-d0a384ea5040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188939441 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3188939441
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.4197151391
Short name T442
Test name
Test status
Simulation time 545598371 ps
CPU time 0.78 seconds
Started Jul 29 05:43:03 PM PDT 24
Finished Jul 29 05:43:04 PM PDT 24
Peak memory 201240 kb
Host smart-7a028672-e764-4b44-ac92-79596a962826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197151391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.4197151391
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2159130497
Short name T308
Test name
Test status
Simulation time 349497576091 ps
CPU time 438.44 seconds
Started Jul 29 05:42:57 PM PDT 24
Finished Jul 29 05:50:15 PM PDT 24
Peak memory 201440 kb
Host smart-e154af5e-2cdc-4c5e-8ee2-7e02e8bf6755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159130497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2159130497
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1305524280
Short name T130
Test name
Test status
Simulation time 491492692477 ps
CPU time 565.13 seconds
Started Jul 29 05:42:54 PM PDT 24
Finished Jul 29 05:52:19 PM PDT 24
Peak memory 201484 kb
Host smart-10bbc268-d885-45d7-a012-d4c28d7e053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305524280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1305524280
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1738444332
Short name T166
Test name
Test status
Simulation time 501280777507 ps
CPU time 295.82 seconds
Started Jul 29 05:42:52 PM PDT 24
Finished Jul 29 05:47:48 PM PDT 24
Peak memory 201428 kb
Host smart-5a6f6811-8fd3-43e8-8bfa-98cf1de57671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738444332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1738444332
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1760952021
Short name T591
Test name
Test status
Simulation time 334868981138 ps
CPU time 178.78 seconds
Started Jul 29 05:42:50 PM PDT 24
Finished Jul 29 05:45:49 PM PDT 24
Peak memory 201364 kb
Host smart-5358fa31-7d01-4a1d-b41f-196f65023747
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760952021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1760952021
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3421063982
Short name T74
Test name
Test status
Simulation time 263754900786 ps
CPU time 274.8 seconds
Started Jul 29 05:42:56 PM PDT 24
Finished Jul 29 05:47:30 PM PDT 24
Peak memory 201456 kb
Host smart-2db24265-5964-45c5-b1bc-ca6f6830a6a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421063982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3421063982
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3666378955
Short name T617
Test name
Test status
Simulation time 419062626420 ps
CPU time 917.03 seconds
Started Jul 29 05:42:53 PM PDT 24
Finished Jul 29 05:58:10 PM PDT 24
Peak memory 201440 kb
Host smart-d7b00b71-1957-404f-ab91-949f5a3f79b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666378955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3666378955
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3405634928
Short name T191
Test name
Test status
Simulation time 69641856226 ps
CPU time 387.56 seconds
Started Jul 29 05:43:00 PM PDT 24
Finished Jul 29 05:49:27 PM PDT 24
Peak memory 201836 kb
Host smart-4e3fc8fd-26cb-47de-be44-33de0074da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405634928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3405634928
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2727296523
Short name T455
Test name
Test status
Simulation time 37492604021 ps
CPU time 82.57 seconds
Started Jul 29 05:43:03 PM PDT 24
Finished Jul 29 05:44:26 PM PDT 24
Peak memory 201372 kb
Host smart-3ec0edc6-cf75-4f57-bc62-30eb608562c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727296523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2727296523
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1376367048
Short name T770
Test name
Test status
Simulation time 2994552066 ps
CPU time 4.72 seconds
Started Jul 29 05:42:59 PM PDT 24
Finished Jul 29 05:43:04 PM PDT 24
Peak memory 201324 kb
Host smart-ea85af1a-4f9c-4e06-a84c-dfcbc3ff3093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376367048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1376367048
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1446554154
Short name T375
Test name
Test status
Simulation time 5661255161 ps
CPU time 7.22 seconds
Started Jul 29 05:42:47 PM PDT 24
Finished Jul 29 05:42:54 PM PDT 24
Peak memory 201388 kb
Host smart-0fa2499c-3bb0-4187-abb9-13de5c614100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446554154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1446554154
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1225742121
Short name T672
Test name
Test status
Simulation time 500212392676 ps
CPU time 188.68 seconds
Started Jul 29 05:43:03 PM PDT 24
Finished Jul 29 05:46:12 PM PDT 24
Peak memory 201516 kb
Host smart-6e1108f8-142a-4ddc-b60c-224a1a17687b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225742121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1225742121
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3984254412
Short name T682
Test name
Test status
Simulation time 58009099872 ps
CPU time 66.95 seconds
Started Jul 29 05:42:57 PM PDT 24
Finished Jul 29 05:44:04 PM PDT 24
Peak memory 209784 kb
Host smart-358a41e3-7dd7-4e52-bae7-7e4e6235fe5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984254412 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3984254412
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2763999290
Short name T339
Test name
Test status
Simulation time 329490717 ps
CPU time 1.01 seconds
Started Jul 29 05:43:07 PM PDT 24
Finished Jul 29 05:43:08 PM PDT 24
Peak memory 201240 kb
Host smart-c0785dde-2cfd-43c7-a87a-71133a39f1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763999290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2763999290
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1781750166
Short name T163
Test name
Test status
Simulation time 512591362876 ps
CPU time 1127.64 seconds
Started Jul 29 05:43:02 PM PDT 24
Finished Jul 29 06:01:50 PM PDT 24
Peak memory 201520 kb
Host smart-540f5e6c-11b3-42b4-b365-cd9c9da14f1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781750166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1781750166
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1484234645
Short name T181
Test name
Test status
Simulation time 509786228824 ps
CPU time 272.08 seconds
Started Jul 29 05:43:04 PM PDT 24
Finished Jul 29 05:47:37 PM PDT 24
Peak memory 201652 kb
Host smart-4113bde4-71ef-4c2d-b0ef-1026092b14e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484234645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1484234645
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2849830478
Short name T436
Test name
Test status
Simulation time 329220987859 ps
CPU time 186.81 seconds
Started Jul 29 05:43:02 PM PDT 24
Finished Jul 29 05:46:08 PM PDT 24
Peak memory 201516 kb
Host smart-002e7814-47a0-480f-b884-69d0cc0228ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849830478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2849830478
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3692564913
Short name T359
Test name
Test status
Simulation time 497802233314 ps
CPU time 1163.06 seconds
Started Jul 29 05:43:05 PM PDT 24
Finished Jul 29 06:02:29 PM PDT 24
Peak memory 201360 kb
Host smart-87995a45-f641-4dcb-89d5-640835f021bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692564913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3692564913
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3875294889
Short name T29
Test name
Test status
Simulation time 323403005143 ps
CPU time 191.4 seconds
Started Jul 29 05:42:58 PM PDT 24
Finished Jul 29 05:46:10 PM PDT 24
Peak memory 201476 kb
Host smart-2779ee8c-fa2f-4b18-bb46-365002b8b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875294889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3875294889
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2703727408
Short name T598
Test name
Test status
Simulation time 492942994584 ps
CPU time 279.59 seconds
Started Jul 29 05:43:01 PM PDT 24
Finished Jul 29 05:47:41 PM PDT 24
Peak memory 201376 kb
Host smart-2a4b5fd0-7f93-495d-a46a-16f3c05f84ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703727408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2703727408
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1807041585
Short name T231
Test name
Test status
Simulation time 366310912021 ps
CPU time 899.69 seconds
Started Jul 29 05:43:05 PM PDT 24
Finished Jul 29 05:58:04 PM PDT 24
Peak memory 201444 kb
Host smart-406a7148-8208-412a-b032-3813bec93d50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807041585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1807041585
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.731013289
Short name T406
Test name
Test status
Simulation time 198181628885 ps
CPU time 460.36 seconds
Started Jul 29 05:43:05 PM PDT 24
Finished Jul 29 05:50:45 PM PDT 24
Peak memory 201368 kb
Host smart-8d8d94c0-8e4b-408d-9242-6d0c9281515e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731013289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.731013289
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.74440095
Short name T194
Test name
Test status
Simulation time 74722848294 ps
CPU time 257.79 seconds
Started Jul 29 05:43:07 PM PDT 24
Finished Jul 29 05:47:25 PM PDT 24
Peak memory 201784 kb
Host smart-aab6cb2c-db69-46f4-a123-649960fc9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74440095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.74440095
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3417708008
Short name T544
Test name
Test status
Simulation time 44914875546 ps
CPU time 22.01 seconds
Started Jul 29 05:43:06 PM PDT 24
Finished Jul 29 05:43:29 PM PDT 24
Peak memory 201504 kb
Host smart-d2231aba-33e5-479d-8463-320a56167df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417708008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3417708008
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1712024
Short name T325
Test name
Test status
Simulation time 3646714596 ps
CPU time 2.99 seconds
Started Jul 29 05:43:05 PM PDT 24
Finished Jul 29 05:43:08 PM PDT 24
Peak memory 201500 kb
Host smart-8c7bac44-670d-4b76-9104-09de38f9e1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1712024
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1387375605
Short name T627
Test name
Test status
Simulation time 5677107445 ps
CPU time 2.88 seconds
Started Jul 29 05:43:03 PM PDT 24
Finished Jul 29 05:43:06 PM PDT 24
Peak memory 201376 kb
Host smart-056906be-23ca-4689-ae27-5275bf61dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387375605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1387375605
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1528458971
Short name T535
Test name
Test status
Simulation time 8460297826 ps
CPU time 20.41 seconds
Started Jul 29 05:43:09 PM PDT 24
Finished Jul 29 05:43:30 PM PDT 24
Peak memory 201300 kb
Host smart-be923ef3-5f71-46e0-b013-02a4b17ed697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528458971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1528458971
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3050858504
Short name T647
Test name
Test status
Simulation time 122192634147 ps
CPU time 301.33 seconds
Started Jul 29 05:43:09 PM PDT 24
Finished Jul 29 05:48:11 PM PDT 24
Peak memory 210060 kb
Host smart-1b284635-1092-4d14-88cc-11587e8e280f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050858504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3050858504
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1690382548
Short name T568
Test name
Test status
Simulation time 382046042 ps
CPU time 1.39 seconds
Started Jul 29 05:43:18 PM PDT 24
Finished Jul 29 05:43:20 PM PDT 24
Peak memory 201224 kb
Host smart-04b8a537-9b7f-4edf-bf52-3745c6baaaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690382548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1690382548
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4238572233
Short name T749
Test name
Test status
Simulation time 190829724203 ps
CPU time 221.72 seconds
Started Jul 29 05:43:16 PM PDT 24
Finished Jul 29 05:46:58 PM PDT 24
Peak memory 201372 kb
Host smart-25393859-4d53-4fe6-b911-9cc47d5b213e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238572233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4238572233
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1589707649
Short name T105
Test name
Test status
Simulation time 519998220875 ps
CPU time 195.38 seconds
Started Jul 29 05:43:12 PM PDT 24
Finished Jul 29 05:46:28 PM PDT 24
Peak memory 201400 kb
Host smart-95b5306a-6c28-449e-b101-46df1400408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589707649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1589707649
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1172795242
Short name T307
Test name
Test status
Simulation time 493119268940 ps
CPU time 284.91 seconds
Started Jul 29 05:43:12 PM PDT 24
Finished Jul 29 05:47:58 PM PDT 24
Peak memory 201456 kb
Host smart-9c4c5af9-8b7b-4901-9dc4-4f68f12c20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172795242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1172795242
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4162458654
Short name T409
Test name
Test status
Simulation time 325810144551 ps
CPU time 215.18 seconds
Started Jul 29 05:43:12 PM PDT 24
Finished Jul 29 05:46:48 PM PDT 24
Peak memory 201376 kb
Host smart-5a5ec3fc-4b22-4e45-b154-031026cc0e2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162458654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4162458654
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3026497358
Short name T711
Test name
Test status
Simulation time 165829378695 ps
CPU time 180.43 seconds
Started Jul 29 05:43:08 PM PDT 24
Finished Jul 29 05:46:09 PM PDT 24
Peak memory 201440 kb
Host smart-5f6cf07e-31f0-4a17-b78d-2f62b575f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026497358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3026497358
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2442652153
Short name T495
Test name
Test status
Simulation time 484443674937 ps
CPU time 1181.35 seconds
Started Jul 29 05:43:12 PM PDT 24
Finished Jul 29 06:02:54 PM PDT 24
Peak memory 201384 kb
Host smart-24ae1fb0-b7b9-431a-a665-96a18e08cbc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442652153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2442652153
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.846778884
Short name T342
Test name
Test status
Simulation time 208577553186 ps
CPU time 250.23 seconds
Started Jul 29 05:43:13 PM PDT 24
Finished Jul 29 05:47:23 PM PDT 24
Peak memory 201440 kb
Host smart-36c7b62c-7edf-4436-afc0-0e77f30ec187
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846778884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.846778884
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.982769551
Short name T462
Test name
Test status
Simulation time 123870441168 ps
CPU time 417.44 seconds
Started Jul 29 05:43:20 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 201832 kb
Host smart-0868ba57-018a-4508-8b7f-2646d1d38468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982769551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.982769551
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3584636985
Short name T319
Test name
Test status
Simulation time 30782061652 ps
CPU time 65.99 seconds
Started Jul 29 05:43:19 PM PDT 24
Finished Jul 29 05:44:25 PM PDT 24
Peak memory 201344 kb
Host smart-7c4120ac-6ec7-47b2-9eb0-223f42e5bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584636985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3584636985
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2695615182
Short name T362
Test name
Test status
Simulation time 5026336667 ps
CPU time 2.31 seconds
Started Jul 29 05:43:19 PM PDT 24
Finished Jul 29 05:43:21 PM PDT 24
Peak memory 201360 kb
Host smart-9d84c506-7406-4f4c-a2a3-912884ecc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695615182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2695615182
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1439943747
Short name T774
Test name
Test status
Simulation time 5868260241 ps
CPU time 8.09 seconds
Started Jul 29 05:43:08 PM PDT 24
Finished Jul 29 05:43:16 PM PDT 24
Peak memory 201308 kb
Host smart-3d388c38-0dcc-424b-aa76-f52b1ed9a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439943747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1439943747
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.4185000392
Short name T723
Test name
Test status
Simulation time 224823915685 ps
CPU time 128.25 seconds
Started Jul 29 05:43:20 PM PDT 24
Finished Jul 29 05:45:28 PM PDT 24
Peak memory 201616 kb
Host smart-92c3e49a-6d72-4a4f-9fe4-ca0086e8fd31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185000392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.4185000392
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3811239654
Short name T555
Test name
Test status
Simulation time 475724916 ps
CPU time 1.19 seconds
Started Jul 29 05:43:34 PM PDT 24
Finished Jul 29 05:43:36 PM PDT 24
Peak memory 201172 kb
Host smart-b4201bda-4573-4de4-a14c-a74de085ce9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811239654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3811239654
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1455024450
Short name T273
Test name
Test status
Simulation time 513912205107 ps
CPU time 959.22 seconds
Started Jul 29 05:43:29 PM PDT 24
Finished Jul 29 05:59:29 PM PDT 24
Peak memory 201392 kb
Host smart-5c219ae7-b370-41d3-b9b0-ee326a395a76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455024450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1455024450
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.79898716
Short name T605
Test name
Test status
Simulation time 176641754138 ps
CPU time 115.81 seconds
Started Jul 29 05:43:29 PM PDT 24
Finished Jul 29 05:45:25 PM PDT 24
Peak memory 201492 kb
Host smart-48730d5c-3357-47ad-90e2-c7d906d1100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79898716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.79898716
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2791120753
Short name T135
Test name
Test status
Simulation time 166071182075 ps
CPU time 96.92 seconds
Started Jul 29 05:43:23 PM PDT 24
Finished Jul 29 05:45:00 PM PDT 24
Peak memory 201376 kb
Host smart-095be276-b571-46cf-a96a-916fb5453892
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791120753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2791120753
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4153078293
Short name T582
Test name
Test status
Simulation time 322061918083 ps
CPU time 730.28 seconds
Started Jul 29 05:43:24 PM PDT 24
Finished Jul 29 05:55:34 PM PDT 24
Peak memory 201444 kb
Host smart-25f39f8b-9c65-4c13-b054-5847807b0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153078293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4153078293
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.51718147
Short name T3
Test name
Test status
Simulation time 165995461821 ps
CPU time 67.78 seconds
Started Jul 29 05:43:22 PM PDT 24
Finished Jul 29 05:44:30 PM PDT 24
Peak memory 201392 kb
Host smart-e5f460cd-180c-49d7-91d1-5465ac0ef8c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=51718147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed
.51718147
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2604814890
Short name T243
Test name
Test status
Simulation time 509453748805 ps
CPU time 611.75 seconds
Started Jul 29 05:43:24 PM PDT 24
Finished Jul 29 05:53:36 PM PDT 24
Peak memory 201444 kb
Host smart-8a4c5826-01ac-4b0d-b7cf-d432303425a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604814890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2604814890
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3670656382
Short name T518
Test name
Test status
Simulation time 194307300013 ps
CPU time 123.74 seconds
Started Jul 29 05:43:30 PM PDT 24
Finished Jul 29 05:45:35 PM PDT 24
Peak memory 201436 kb
Host smart-ca435e64-b316-4979-a55c-72aea6683aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670656382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3670656382
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3717653169
Short name T466
Test name
Test status
Simulation time 81112583272 ps
CPU time 314.19 seconds
Started Jul 29 05:43:32 PM PDT 24
Finished Jul 29 05:48:46 PM PDT 24
Peak memory 201820 kb
Host smart-ab839037-0f4e-4630-9157-d200a7ed837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717653169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3717653169
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2692162722
Short name T476
Test name
Test status
Simulation time 23163027277 ps
CPU time 12.97 seconds
Started Jul 29 05:43:27 PM PDT 24
Finished Jul 29 05:43:41 PM PDT 24
Peak memory 201280 kb
Host smart-7a0b5fe6-9cf5-4cdc-88d9-11b9e080f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692162722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2692162722
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1254984238
Short name T389
Test name
Test status
Simulation time 4318456535 ps
CPU time 2.19 seconds
Started Jul 29 05:43:28 PM PDT 24
Finished Jul 29 05:43:31 PM PDT 24
Peak memory 201304 kb
Host smart-f9f1a300-c9ab-4558-bbbd-c7533bdad716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254984238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1254984238
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1535263456
Short name T94
Test name
Test status
Simulation time 5778687602 ps
CPU time 4.76 seconds
Started Jul 29 05:43:24 PM PDT 24
Finished Jul 29 05:43:28 PM PDT 24
Peak memory 201288 kb
Host smart-31bb640b-730a-471d-8745-24e7dd57c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535263456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1535263456
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.366787898
Short name T195
Test name
Test status
Simulation time 97792662830 ps
CPU time 527.79 seconds
Started Jul 29 05:43:31 PM PDT 24
Finished Jul 29 05:52:19 PM PDT 24
Peak memory 201752 kb
Host smart-37a26176-c495-4e22-8c2c-2f5ba4ce73c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366787898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
366787898
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.462680105
Short name T728
Test name
Test status
Simulation time 54459974985 ps
CPU time 142.99 seconds
Started Jul 29 05:43:34 PM PDT 24
Finished Jul 29 05:45:57 PM PDT 24
Peak memory 210096 kb
Host smart-07e94b51-de8c-4e47-bc6e-2cb14e684d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462680105 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.462680105
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1339685356
Short name T372
Test name
Test status
Simulation time 435636694 ps
CPU time 0.72 seconds
Started Jul 29 05:43:46 PM PDT 24
Finished Jul 29 05:43:47 PM PDT 24
Peak memory 201184 kb
Host smart-4d42a2e2-7750-40a0-b5bc-9bebaed0a1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339685356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1339685356
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2758876275
Short name T288
Test name
Test status
Simulation time 534572162092 ps
CPU time 1144.89 seconds
Started Jul 29 05:43:37 PM PDT 24
Finished Jul 29 06:02:42 PM PDT 24
Peak memory 201380 kb
Host smart-0edc2c08-6249-4537-86d4-fd3966297854
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758876275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2758876275
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2068139574
Short name T651
Test name
Test status
Simulation time 160107907573 ps
CPU time 194.58 seconds
Started Jul 29 05:43:43 PM PDT 24
Finished Jul 29 05:46:57 PM PDT 24
Peak memory 201440 kb
Host smart-f4283e05-01c8-4376-be95-e8f6e5fcd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068139574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2068139574
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3164894135
Short name T247
Test name
Test status
Simulation time 322094588471 ps
CPU time 732.59 seconds
Started Jul 29 05:43:33 PM PDT 24
Finished Jul 29 05:55:46 PM PDT 24
Peak memory 201516 kb
Host smart-fbaa67c2-3fe7-4716-a108-57e8b75cbfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164894135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3164894135
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2947493460
Short name T381
Test name
Test status
Simulation time 494331593062 ps
CPU time 573.01 seconds
Started Jul 29 05:43:37 PM PDT 24
Finished Jul 29 05:53:10 PM PDT 24
Peak memory 201428 kb
Host smart-53760764-e98f-48bf-970c-27bd289dddc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947493460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2947493460
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3739729631
Short name T344
Test name
Test status
Simulation time 166267781441 ps
CPU time 98.43 seconds
Started Jul 29 05:43:32 PM PDT 24
Finished Jul 29 05:45:11 PM PDT 24
Peak memory 201320 kb
Host smart-ac071be4-c5a1-4dac-9a0e-ebce97e7a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739729631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3739729631
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1454454076
Short name T701
Test name
Test status
Simulation time 491318350128 ps
CPU time 274.55 seconds
Started Jul 29 05:43:34 PM PDT 24
Finished Jul 29 05:48:09 PM PDT 24
Peak memory 201444 kb
Host smart-76e824c6-8d61-4c7e-890b-42c0a8d406c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454454076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1454454076
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1000292941
Short name T172
Test name
Test status
Simulation time 522361255217 ps
CPU time 316.12 seconds
Started Jul 29 05:43:38 PM PDT 24
Finished Jul 29 05:48:54 PM PDT 24
Peak memory 201424 kb
Host smart-f4834e45-cf41-4b7b-ace2-0265e12ce861
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000292941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1000292941
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3945109205
Short name T643
Test name
Test status
Simulation time 391437440023 ps
CPU time 506.88 seconds
Started Jul 29 05:43:38 PM PDT 24
Finished Jul 29 05:52:05 PM PDT 24
Peak memory 201428 kb
Host smart-113f79be-5aca-45a3-9f25-857b6e0b6909
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945109205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3945109205
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1326793811
Short name T750
Test name
Test status
Simulation time 81644938860 ps
CPU time 294.93 seconds
Started Jul 29 05:43:41 PM PDT 24
Finished Jul 29 05:48:36 PM PDT 24
Peak memory 201892 kb
Host smart-b5bca3c8-3187-4686-ba58-cae8562886b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326793811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1326793811
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.855791349
Short name T509
Test name
Test status
Simulation time 47198091666 ps
CPU time 30.01 seconds
Started Jul 29 05:43:43 PM PDT 24
Finished Jul 29 05:44:13 PM PDT 24
Peak memory 201368 kb
Host smart-442c3984-726b-42fe-a060-82143a752d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855791349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.855791349
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1012127130
Short name T386
Test name
Test status
Simulation time 5088441746 ps
CPU time 11.63 seconds
Started Jul 29 05:43:42 PM PDT 24
Finished Jul 29 05:43:53 PM PDT 24
Peak memory 201348 kb
Host smart-630fe974-addf-432b-a22f-6bdd22e9213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012127130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1012127130
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1510533765
Short name T388
Test name
Test status
Simulation time 5576383568 ps
CPU time 14.1 seconds
Started Jul 29 05:43:34 PM PDT 24
Finished Jul 29 05:43:48 PM PDT 24
Peak memory 201372 kb
Host smart-5d6fafa2-6d0a-481f-bf31-2dbec989f4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510533765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1510533765
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1895115091
Short name T6
Test name
Test status
Simulation time 11460708380 ps
CPU time 13.38 seconds
Started Jul 29 05:43:46 PM PDT 24
Finished Jul 29 05:43:59 PM PDT 24
Peak memory 201512 kb
Host smart-9fe270c2-b9f4-4c0c-a856-e5aee504c0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895115091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1895115091
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.343630620
Short name T37
Test name
Test status
Simulation time 128469675754 ps
CPU time 150.95 seconds
Started Jul 29 05:43:42 PM PDT 24
Finished Jul 29 05:46:13 PM PDT 24
Peak memory 209736 kb
Host smart-143d4974-5145-45da-bed6-39ca63f4c781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343630620 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.343630620
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.728044959
Short name T641
Test name
Test status
Simulation time 413924139 ps
CPU time 1.54 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:40:09 PM PDT 24
Peak memory 201228 kb
Host smart-e0d06dfb-9e68-4385-8658-057996e69bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728044959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.728044959
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3381684907
Short name T133
Test name
Test status
Simulation time 562719072186 ps
CPU time 310.97 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:45:13 PM PDT 24
Peak memory 201448 kb
Host smart-603c0cdb-bf46-43c2-9d37-0052cd147dad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381684907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3381684907
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.787496480
Short name T752
Test name
Test status
Simulation time 346286546371 ps
CPU time 401.27 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 05:46:44 PM PDT 24
Peak memory 201396 kb
Host smart-678aeeec-8a4d-422c-8153-bbdfd250bbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787496480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.787496480
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3750682831
Short name T480
Test name
Test status
Simulation time 497651376305 ps
CPU time 612.86 seconds
Started Jul 29 05:40:01 PM PDT 24
Finished Jul 29 05:50:14 PM PDT 24
Peak memory 201444 kb
Host smart-4823c0b9-dd77-44ec-ac16-ee4c00ccf3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750682831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3750682831
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.76962881
Short name T426
Test name
Test status
Simulation time 167572981585 ps
CPU time 193.5 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:43:16 PM PDT 24
Peak memory 201452 kb
Host smart-09fbd4a8-7e4f-4e17-9721-7ff7d6827c6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=76962881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_
fixed.76962881
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1535089200
Short name T484
Test name
Test status
Simulation time 164321605701 ps
CPU time 91.38 seconds
Started Jul 29 05:40:04 PM PDT 24
Finished Jul 29 05:41:35 PM PDT 24
Peak memory 201440 kb
Host smart-31891eca-28c3-4f4b-9414-c8141dfc9512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535089200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1535089200
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3475938717
Short name T147
Test name
Test status
Simulation time 338329558918 ps
CPU time 107.1 seconds
Started Jul 29 05:40:04 PM PDT 24
Finished Jul 29 05:41:52 PM PDT 24
Peak memory 201436 kb
Host smart-01ba12ff-c22e-4fb9-b773-8483a6cf6e20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475938717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3475938717
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.557051455
Short name T84
Test name
Test status
Simulation time 589543247669 ps
CPU time 1416.72 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 06:03:40 PM PDT 24
Peak memory 201404 kb
Host smart-93dbb1a6-5e73-42ba-9360-061c61fa5a16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557051455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.557051455
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3847042982
Short name T430
Test name
Test status
Simulation time 201341015606 ps
CPU time 249.8 seconds
Started Jul 29 05:40:04 PM PDT 24
Finished Jul 29 05:44:14 PM PDT 24
Peak memory 201432 kb
Host smart-57b355c1-bd24-4e25-8b10-a397654f1bd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847042982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3847042982
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.172677670
Short name T102
Test name
Test status
Simulation time 96980974000 ps
CPU time 469.44 seconds
Started Jul 29 05:40:01 PM PDT 24
Finished Jul 29 05:47:50 PM PDT 24
Peak memory 201836 kb
Host smart-43234ec4-59a2-46dd-99f5-e5b101105324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172677670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.172677670
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2660510029
Short name T380
Test name
Test status
Simulation time 24896842068 ps
CPU time 28.73 seconds
Started Jul 29 05:40:03 PM PDT 24
Finished Jul 29 05:40:31 PM PDT 24
Peak memory 201508 kb
Host smart-e4dcb89b-e0f9-4307-b98c-eaafb85c5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660510029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2660510029
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4238939610
Short name T671
Test name
Test status
Simulation time 4949239295 ps
CPU time 2 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:40:04 PM PDT 24
Peak memory 201304 kb
Host smart-07eafe20-90dc-4e54-9767-9eb38eed8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238939610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4238939610
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3342952593
Short name T58
Test name
Test status
Simulation time 7848460972 ps
CPU time 9.72 seconds
Started Jul 29 05:40:09 PM PDT 24
Finished Jul 29 05:40:18 PM PDT 24
Peak memory 218360 kb
Host smart-1d7e2ad2-e8a1-4c39-90ea-b5ec63de4937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342952593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3342952593
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2245474845
Short name T443
Test name
Test status
Simulation time 5700710757 ps
CPU time 4.01 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:40:06 PM PDT 24
Peak memory 201316 kb
Host smart-d9987f81-3433-45c1-8d70-ba09c26ed352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245474845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2245474845
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3680142935
Short name T190
Test name
Test status
Simulation time 574902202885 ps
CPU time 641.52 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:50:51 PM PDT 24
Peak memory 210004 kb
Host smart-58681216-f492-4546-ac57-8b69501464ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680142935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3680142935
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.820882070
Short name T718
Test name
Test status
Simulation time 442999117074 ps
CPU time 665.55 seconds
Started Jul 29 05:40:02 PM PDT 24
Finished Jul 29 05:51:07 PM PDT 24
Peak memory 210176 kb
Host smart-6487f135-63f3-464f-9622-544d598286e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820882070 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.820882070
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3901711241
Short name T63
Test name
Test status
Simulation time 407715633 ps
CPU time 1.54 seconds
Started Jul 29 05:43:56 PM PDT 24
Finished Jul 29 05:43:57 PM PDT 24
Peak memory 201224 kb
Host smart-95963fdb-0cbf-42d0-9da9-301304846d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901711241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3901711241
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.955039059
Short name T333
Test name
Test status
Simulation time 327797299815 ps
CPU time 192.01 seconds
Started Jul 29 05:43:51 PM PDT 24
Finished Jul 29 05:47:03 PM PDT 24
Peak memory 201508 kb
Host smart-7545f9bc-3f8f-4535-9160-3d0245e4bb60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=955039059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.955039059
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3049891528
Short name T2
Test name
Test status
Simulation time 331618171332 ps
CPU time 514.26 seconds
Started Jul 29 05:43:48 PM PDT 24
Finished Jul 29 05:52:23 PM PDT 24
Peak memory 201432 kb
Host smart-98e25735-17c5-4c78-9fd0-626e8e097adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049891528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3049891528
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3180484004
Short name T8
Test name
Test status
Simulation time 161535845000 ps
CPU time 30.4 seconds
Started Jul 29 05:43:46 PM PDT 24
Finished Jul 29 05:44:16 PM PDT 24
Peak memory 201452 kb
Host smart-c9b2ef78-60a4-4962-9bca-7d9f846b1d1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180484004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3180484004
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3987813790
Short name T240
Test name
Test status
Simulation time 352289817566 ps
CPU time 424.94 seconds
Started Jul 29 05:43:51 PM PDT 24
Finished Jul 29 05:50:56 PM PDT 24
Peak memory 201456 kb
Host smart-2598ae90-80a3-461c-934e-c978d177b94d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987813790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3987813790
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2037368393
Short name T331
Test name
Test status
Simulation time 393799991212 ps
CPU time 167.76 seconds
Started Jul 29 05:43:49 PM PDT 24
Finished Jul 29 05:46:37 PM PDT 24
Peak memory 201452 kb
Host smart-569fc7ff-3759-4aa7-b7ac-b076d8806893
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037368393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2037368393
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3030171419
Short name T80
Test name
Test status
Simulation time 78822813530 ps
CPU time 437.54 seconds
Started Jul 29 05:43:56 PM PDT 24
Finished Jul 29 05:51:14 PM PDT 24
Peak memory 201776 kb
Host smart-145b0a24-7d28-43f1-adbc-d8f44e89a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030171419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3030171419
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.955857595
Short name T377
Test name
Test status
Simulation time 36908795131 ps
CPU time 23.18 seconds
Started Jul 29 05:43:56 PM PDT 24
Finished Jul 29 05:44:20 PM PDT 24
Peak memory 201360 kb
Host smart-0d4e4719-b5b6-4897-b371-9aac3f3e134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955857595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.955857595
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3828398875
Short name T107
Test name
Test status
Simulation time 4581334078 ps
CPU time 1.78 seconds
Started Jul 29 05:44:00 PM PDT 24
Finished Jul 29 05:44:01 PM PDT 24
Peak memory 201284 kb
Host smart-800211bc-31bf-4426-a236-6243623eab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828398875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3828398875
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3055721506
Short name T343
Test name
Test status
Simulation time 5885007596 ps
CPU time 4.03 seconds
Started Jul 29 05:43:47 PM PDT 24
Finished Jul 29 05:43:51 PM PDT 24
Peak memory 201356 kb
Host smart-808e1b40-b776-41a6-ba97-cc70398dad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055721506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3055721506
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1454969936
Short name T245
Test name
Test status
Simulation time 672339794257 ps
CPU time 1409.69 seconds
Started Jul 29 05:43:57 PM PDT 24
Finished Jul 29 06:07:26 PM PDT 24
Peak memory 201420 kb
Host smart-1f240ede-04c5-43fb-b30e-90b43693e1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454969936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1454969936
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.14550911
Short name T229
Test name
Test status
Simulation time 422399193042 ps
CPU time 170.82 seconds
Started Jul 29 05:43:58 PM PDT 24
Finished Jul 29 05:46:49 PM PDT 24
Peak memory 209708 kb
Host smart-65c1cfe0-4e22-4b3b-848f-afcc44bce356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550911 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.14550911
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.6778119
Short name T463
Test name
Test status
Simulation time 417166676 ps
CPU time 0.85 seconds
Started Jul 29 05:44:05 PM PDT 24
Finished Jul 29 05:44:06 PM PDT 24
Peak memory 201156 kb
Host smart-f1debbc0-44c9-4ebf-831d-04e985d87689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6778119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.6778119
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.29528027
Short name T482
Test name
Test status
Simulation time 325060902950 ps
CPU time 769.08 seconds
Started Jul 29 05:44:02 PM PDT 24
Finished Jul 29 05:56:52 PM PDT 24
Peak memory 201424 kb
Host smart-eeb5f019-260b-484f-bc58-14613db765e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29528027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.29528027
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3310984893
Short name T408
Test name
Test status
Simulation time 489698993865 ps
CPU time 252.32 seconds
Started Jul 29 05:44:03 PM PDT 24
Finished Jul 29 05:48:15 PM PDT 24
Peak memory 201412 kb
Host smart-bc6654af-966d-4717-af29-1674c489152b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310984893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3310984893
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2322865643
Short name T487
Test name
Test status
Simulation time 325727579505 ps
CPU time 661.15 seconds
Started Jul 29 05:44:02 PM PDT 24
Finished Jul 29 05:55:03 PM PDT 24
Peak memory 201424 kb
Host smart-c108ce4f-0a8d-4785-a404-6ad89774df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322865643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2322865643
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1753012291
Short name T485
Test name
Test status
Simulation time 325921914318 ps
CPU time 743.97 seconds
Started Jul 29 05:44:01 PM PDT 24
Finished Jul 29 05:56:25 PM PDT 24
Peak memory 201436 kb
Host smart-03f35e14-3fcc-47eb-92ac-77e05fdefae6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753012291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1753012291
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2618693751
Short name T242
Test name
Test status
Simulation time 162653922287 ps
CPU time 333.03 seconds
Started Jul 29 05:44:01 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 201324 kb
Host smart-9bc9ba25-cfb1-4acf-b3d8-23a71599a37c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618693751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2618693751
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2753608404
Short name T658
Test name
Test status
Simulation time 595132802527 ps
CPU time 1315.29 seconds
Started Jul 29 05:43:59 PM PDT 24
Finished Jul 29 06:05:55 PM PDT 24
Peak memory 201432 kb
Host smart-7e0ff6cb-1107-4b06-a49b-13a620b7792b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753608404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2753608404
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.819945117
Short name T776
Test name
Test status
Simulation time 92432457795 ps
CPU time 548.41 seconds
Started Jul 29 05:44:07 PM PDT 24
Finished Jul 29 05:53:15 PM PDT 24
Peak memory 201876 kb
Host smart-b103338a-af59-4ae4-9262-3f2f9a46a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819945117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.819945117
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4292579618
Short name T370
Test name
Test status
Simulation time 23424143443 ps
CPU time 56.57 seconds
Started Jul 29 05:44:01 PM PDT 24
Finished Jul 29 05:44:58 PM PDT 24
Peak memory 201284 kb
Host smart-9f2b2c99-e5d3-4a88-a511-ac9ca5c793c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292579618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4292579618
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3880910802
Short name T457
Test name
Test status
Simulation time 2919071028 ps
CPU time 2.38 seconds
Started Jul 29 05:44:01 PM PDT 24
Finished Jul 29 05:44:03 PM PDT 24
Peak memory 201376 kb
Host smart-302ace14-cee3-4f36-8484-15f9b624bba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880910802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3880910802
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2017408045
Short name T612
Test name
Test status
Simulation time 5969510034 ps
CPU time 4.32 seconds
Started Jul 29 05:43:58 PM PDT 24
Finished Jul 29 05:44:03 PM PDT 24
Peak memory 201308 kb
Host smart-74a01946-6d96-4e05-808b-bee0d934e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017408045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2017408045
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2566256122
Short name T203
Test name
Test status
Simulation time 382948710064 ps
CPU time 449.78 seconds
Started Jul 29 05:44:07 PM PDT 24
Finished Jul 29 05:51:37 PM PDT 24
Peak memory 218152 kb
Host smart-7214eba5-a2f7-4e9a-99fe-81d52231094a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566256122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2566256122
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4153787453
Short name T699
Test name
Test status
Simulation time 49049619808 ps
CPU time 56.11 seconds
Started Jul 29 05:44:07 PM PDT 24
Finished Jul 29 05:45:03 PM PDT 24
Peak memory 209932 kb
Host smart-6a348fca-b2da-4454-8b29-de3d09e15f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153787453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4153787453
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1547705167
Short name T743
Test name
Test status
Simulation time 361017702 ps
CPU time 0.81 seconds
Started Jul 29 05:44:21 PM PDT 24
Finished Jul 29 05:44:22 PM PDT 24
Peak memory 201184 kb
Host smart-f64ab0cc-91bb-4d43-a19e-15f2187ba304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547705167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1547705167
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1732721993
Short name T152
Test name
Test status
Simulation time 157490269489 ps
CPU time 90.54 seconds
Started Jul 29 05:44:11 PM PDT 24
Finished Jul 29 05:45:41 PM PDT 24
Peak memory 201404 kb
Host smart-c4c2f8a6-355d-484f-a3d9-3ef2922c35b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732721993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1732721993
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2685762065
Short name T619
Test name
Test status
Simulation time 167024240932 ps
CPU time 110.09 seconds
Started Jul 29 05:44:15 PM PDT 24
Finished Jul 29 05:46:05 PM PDT 24
Peak memory 201376 kb
Host smart-87aeaba3-9266-48f3-822a-561d4c7b7f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685762065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2685762065
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.771381728
Short name T637
Test name
Test status
Simulation time 161231584522 ps
CPU time 188.62 seconds
Started Jul 29 05:44:10 PM PDT 24
Finished Jul 29 05:47:18 PM PDT 24
Peak memory 201388 kb
Host smart-6b220e3a-4b38-489f-b808-baec4771e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771381728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.771381728
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2301870654
Short name T685
Test name
Test status
Simulation time 165156401622 ps
CPU time 368.4 seconds
Started Jul 29 05:44:10 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 201384 kb
Host smart-f85b1c08-51a6-4492-b8e4-956a260cb8da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301870654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2301870654
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.681702449
Short name T494
Test name
Test status
Simulation time 331549987363 ps
CPU time 598.7 seconds
Started Jul 29 05:44:05 PM PDT 24
Finished Jul 29 05:54:04 PM PDT 24
Peak memory 201376 kb
Host smart-cd49a80c-1bda-4009-9bb1-9f858d4de0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681702449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.681702449
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.4160123862
Short name T414
Test name
Test status
Simulation time 162118542009 ps
CPU time 164.22 seconds
Started Jul 29 05:44:05 PM PDT 24
Finished Jul 29 05:46:49 PM PDT 24
Peak memory 201384 kb
Host smart-f3bab919-ba0a-4e78-8e48-71123fc64950
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160123862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.4160123862
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1179666387
Short name T705
Test name
Test status
Simulation time 178648064678 ps
CPU time 257.25 seconds
Started Jul 29 05:44:08 PM PDT 24
Finished Jul 29 05:48:26 PM PDT 24
Peak memory 201420 kb
Host smart-e5afd460-6f07-4d6f-87e6-fc699f3b754e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179666387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1179666387
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2854288918
Short name T757
Test name
Test status
Simulation time 403941012417 ps
CPU time 171.66 seconds
Started Jul 29 05:44:11 PM PDT 24
Finished Jul 29 05:47:03 PM PDT 24
Peak memory 201600 kb
Host smart-2b92662c-3114-4bd2-b2f5-c1c29372a090
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854288918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2854288918
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.220293202
Short name T662
Test name
Test status
Simulation time 105808009310 ps
CPU time 568.45 seconds
Started Jul 29 05:44:20 PM PDT 24
Finished Jul 29 05:53:49 PM PDT 24
Peak memory 201892 kb
Host smart-cf18c5f4-f24d-4a9f-b6df-7fbe0d4785a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220293202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.220293202
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3547862484
Short name T366
Test name
Test status
Simulation time 26907581399 ps
CPU time 29.12 seconds
Started Jul 29 05:44:15 PM PDT 24
Finished Jul 29 05:44:44 PM PDT 24
Peak memory 201312 kb
Host smart-6c79ee8e-3a6e-4362-92fc-465f421b15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547862484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3547862484
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.380745750
Short name T508
Test name
Test status
Simulation time 2846886365 ps
CPU time 3.81 seconds
Started Jul 29 05:44:17 PM PDT 24
Finished Jul 29 05:44:21 PM PDT 24
Peak memory 201508 kb
Host smart-1cf0a7df-2cf7-4ae9-99e6-2215d6543dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380745750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.380745750
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3170406954
Short name T336
Test name
Test status
Simulation time 6105688794 ps
CPU time 2.25 seconds
Started Jul 29 05:44:06 PM PDT 24
Finished Jul 29 05:44:08 PM PDT 24
Peak memory 201352 kb
Host smart-8da4e469-b309-41b4-b8f5-21cc326227ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170406954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3170406954
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.549371146
Short name T458
Test name
Test status
Simulation time 51169425276 ps
CPU time 119.87 seconds
Started Jul 29 05:44:19 PM PDT 24
Finished Jul 29 05:46:19 PM PDT 24
Peak memory 201372 kb
Host smart-93951898-9202-4b1d-b47d-b5de77102cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549371146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
549371146
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2184627551
Short name T21
Test name
Test status
Simulation time 16930285621 ps
CPU time 55.3 seconds
Started Jul 29 05:44:21 PM PDT 24
Finished Jul 29 05:45:16 PM PDT 24
Peak memory 210124 kb
Host smart-0dde9fa8-47a5-4f7b-81d3-07b8e6daa0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184627551 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2184627551
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2203166709
Short name T554
Test name
Test status
Simulation time 286225739 ps
CPU time 1.33 seconds
Started Jul 29 05:44:28 PM PDT 24
Finished Jul 29 05:44:30 PM PDT 24
Peak memory 201220 kb
Host smart-4847aee5-649d-465d-a8a9-072c912b447c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203166709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2203166709
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3220105089
Short name T303
Test name
Test status
Simulation time 532088759653 ps
CPU time 276.68 seconds
Started Jul 29 05:44:25 PM PDT 24
Finished Jul 29 05:49:02 PM PDT 24
Peak memory 201428 kb
Host smart-16e164ea-f3c4-418c-8f7a-bd6a7f1a61c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220105089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3220105089
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1480757809
Short name T164
Test name
Test status
Simulation time 518601178523 ps
CPU time 573.45 seconds
Started Jul 29 05:44:30 PM PDT 24
Finished Jul 29 05:54:03 PM PDT 24
Peak memory 201456 kb
Host smart-aced231a-4f36-4e00-8e72-be8ec9d91e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480757809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1480757809
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.601050151
Short name T424
Test name
Test status
Simulation time 168926202206 ps
CPU time 332.21 seconds
Started Jul 29 05:44:27 PM PDT 24
Finished Jul 29 05:49:59 PM PDT 24
Peak memory 201348 kb
Host smart-6a3dbf74-5b08-436b-becd-14e6c1d6f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601050151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.601050151
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3547757553
Short name T358
Test name
Test status
Simulation time 160956610362 ps
CPU time 170.89 seconds
Started Jul 29 05:44:26 PM PDT 24
Finished Jul 29 05:47:17 PM PDT 24
Peak memory 201380 kb
Host smart-d99a9bb5-f450-459a-b39d-674732d0bcba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547757553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3547757553
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1190926866
Short name T633
Test name
Test status
Simulation time 160835402236 ps
CPU time 92.65 seconds
Started Jul 29 05:44:26 PM PDT 24
Finished Jul 29 05:45:58 PM PDT 24
Peak memory 201380 kb
Host smart-ff7a3cb4-e70f-4676-8968-99d091910ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190926866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1190926866
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3589173833
Short name T729
Test name
Test status
Simulation time 166159070833 ps
CPU time 324.4 seconds
Started Jul 29 05:44:25 PM PDT 24
Finished Jul 29 05:49:50 PM PDT 24
Peak memory 201448 kb
Host smart-82eddf7e-9f6e-4ceb-b533-9d6a28cec0b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589173833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3589173833
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4121824757
Short name T104
Test name
Test status
Simulation time 166077763003 ps
CPU time 374.35 seconds
Started Jul 29 05:44:25 PM PDT 24
Finished Jul 29 05:50:39 PM PDT 24
Peak memory 201460 kb
Host smart-479777e8-3043-4f5f-8b5d-d39562c1f97e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121824757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4121824757
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3092506536
Short name T450
Test name
Test status
Simulation time 209070399340 ps
CPU time 437.46 seconds
Started Jul 29 05:44:24 PM PDT 24
Finished Jul 29 05:51:42 PM PDT 24
Peak memory 201444 kb
Host smart-3370c4cd-690b-4278-9012-e50c1ad23e34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092506536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3092506536
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2833082269
Short name T199
Test name
Test status
Simulation time 75545888866 ps
CPU time 416.52 seconds
Started Jul 29 05:44:29 PM PDT 24
Finished Jul 29 05:51:26 PM PDT 24
Peak memory 201728 kb
Host smart-8cb29d76-7232-4a8a-ab7a-64b1ebbd72ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833082269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2833082269
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4094246001
Short name T579
Test name
Test status
Simulation time 26554051642 ps
CPU time 61.89 seconds
Started Jul 29 05:44:30 PM PDT 24
Finished Jul 29 05:45:32 PM PDT 24
Peak memory 201360 kb
Host smart-3be1db4d-7660-4c57-ac37-a62ed7956fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094246001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4094246001
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1298434381
Short name T530
Test name
Test status
Simulation time 3310017453 ps
CPU time 8.67 seconds
Started Jul 29 05:44:29 PM PDT 24
Finished Jul 29 05:44:38 PM PDT 24
Peak memory 201324 kb
Host smart-56458062-8e67-4544-8c51-205bafbae99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298434381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1298434381
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3590340230
Short name T614
Test name
Test status
Simulation time 5871711999 ps
CPU time 13.2 seconds
Started Jul 29 05:44:25 PM PDT 24
Finished Jul 29 05:44:39 PM PDT 24
Peak memory 201368 kb
Host smart-f32aee71-3bdc-425e-94c9-4a165e9ae102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590340230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3590340230
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1344654567
Short name T725
Test name
Test status
Simulation time 89716088556 ps
CPU time 468.54 seconds
Started Jul 29 05:44:30 PM PDT 24
Finished Jul 29 05:52:18 PM PDT 24
Peak memory 201824 kb
Host smart-31f4c28b-a077-4a1a-bf62-9826d15f6263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344654567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1344654567
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.290635326
Short name T602
Test name
Test status
Simulation time 184389520950 ps
CPU time 168.13 seconds
Started Jul 29 05:44:31 PM PDT 24
Finished Jul 29 05:47:19 PM PDT 24
Peak memory 210100 kb
Host smart-8e2abf37-a37a-4369-a89f-f657018e179d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290635326 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.290635326
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2553864939
Short name T763
Test name
Test status
Simulation time 514963509 ps
CPU time 1.75 seconds
Started Jul 29 05:44:43 PM PDT 24
Finished Jul 29 05:44:45 PM PDT 24
Peak memory 201232 kb
Host smart-3dea4768-9292-4940-ae74-ad8ee5800c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553864939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2553864939
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1199615642
Short name T731
Test name
Test status
Simulation time 517129332237 ps
CPU time 334.5 seconds
Started Jul 29 05:44:35 PM PDT 24
Finished Jul 29 05:50:09 PM PDT 24
Peak memory 201408 kb
Host smart-f079a982-71cc-45e6-a39f-2256645b0fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199615642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1199615642
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4277666970
Short name T236
Test name
Test status
Simulation time 493194202817 ps
CPU time 504.19 seconds
Started Jul 29 05:44:33 PM PDT 24
Finished Jul 29 05:52:57 PM PDT 24
Peak memory 201456 kb
Host smart-0439ffea-ea01-4882-8ffe-3d2376a0fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277666970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4277666970
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.124360599
Short name T514
Test name
Test status
Simulation time 328810812681 ps
CPU time 408.1 seconds
Started Jul 29 05:44:34 PM PDT 24
Finished Jul 29 05:51:23 PM PDT 24
Peak memory 201376 kb
Host smart-ea4f1cf7-eb24-4bbb-a7fd-fd2da1e879e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=124360599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.124360599
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3527707868
Short name T589
Test name
Test status
Simulation time 161422659750 ps
CPU time 389.44 seconds
Started Jul 29 05:44:31 PM PDT 24
Finished Jul 29 05:51:00 PM PDT 24
Peak memory 201452 kb
Host smart-6d4499e8-3216-471a-8561-e287bb26caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527707868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3527707868
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1751390348
Short name T657
Test name
Test status
Simulation time 492940097286 ps
CPU time 551.77 seconds
Started Jul 29 05:44:33 PM PDT 24
Finished Jul 29 05:53:45 PM PDT 24
Peak memory 201368 kb
Host smart-401fbf2e-c5a9-4c5c-8b5d-04eb91dbcb2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751390348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1751390348
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1053064492
Short name T235
Test name
Test status
Simulation time 173857071215 ps
CPU time 389.41 seconds
Started Jul 29 05:44:34 PM PDT 24
Finished Jul 29 05:51:03 PM PDT 24
Peak memory 201444 kb
Host smart-4df0f4ea-f2e4-41f1-9e7f-ffc56e198a56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053064492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1053064492
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.39487955
Short name T630
Test name
Test status
Simulation time 603356421903 ps
CPU time 1356.1 seconds
Started Jul 29 05:44:34 PM PDT 24
Finished Jul 29 06:07:10 PM PDT 24
Peak memory 201364 kb
Host smart-7a09e249-d897-4abf-a829-85255496124e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
dc_ctrl_filters_wakeup_fixed.39487955
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.989352836
Short name T40
Test name
Test status
Simulation time 127263414981 ps
CPU time 617.75 seconds
Started Jul 29 05:44:38 PM PDT 24
Finished Jul 29 05:54:56 PM PDT 24
Peak memory 201836 kb
Host smart-23cda6b8-3f95-4e0c-8b58-8b14c183f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989352836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.989352836
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.410135517
Short name T580
Test name
Test status
Simulation time 39697719248 ps
CPU time 46.38 seconds
Started Jul 29 05:44:37 PM PDT 24
Finished Jul 29 05:45:24 PM PDT 24
Peak memory 201380 kb
Host smart-9d9f769e-fa76-453f-8910-3178383961ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410135517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.410135517
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.977149263
Short name T639
Test name
Test status
Simulation time 3986715153 ps
CPU time 9.25 seconds
Started Jul 29 05:44:35 PM PDT 24
Finished Jul 29 05:44:44 PM PDT 24
Peak memory 201504 kb
Host smart-212191d0-2d94-486f-9243-cd32283b8438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977149263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.977149263
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3963687006
Short name T444
Test name
Test status
Simulation time 5614670923 ps
CPU time 4.24 seconds
Started Jul 29 05:44:33 PM PDT 24
Finished Jul 29 05:44:37 PM PDT 24
Peak memory 201308 kb
Host smart-3e09f10c-285d-4896-8b86-dd500faba7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963687006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3963687006
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.316904154
Short name T292
Test name
Test status
Simulation time 244051053059 ps
CPU time 139.11 seconds
Started Jul 29 05:44:39 PM PDT 24
Finished Jul 29 05:46:58 PM PDT 24
Peak memory 201380 kb
Host smart-21cbf3e9-8e40-4678-b3a3-f016bbd75458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316904154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
316904154
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3233078854
Short name T16
Test name
Test status
Simulation time 55658995996 ps
CPU time 110.32 seconds
Started Jul 29 05:44:39 PM PDT 24
Finished Jul 29 05:46:30 PM PDT 24
Peak memory 218304 kb
Host smart-46c9fb09-368b-4e15-848c-5ddd09604fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233078854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3233078854
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2064872470
Short name T403
Test name
Test status
Simulation time 438456870 ps
CPU time 1.69 seconds
Started Jul 29 05:44:56 PM PDT 24
Finished Jul 29 05:44:58 PM PDT 24
Peak memory 201240 kb
Host smart-a6672fae-1302-4463-9df1-2034fbd3ff35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064872470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2064872470
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2099241526
Short name T709
Test name
Test status
Simulation time 163682207802 ps
CPU time 398.55 seconds
Started Jul 29 05:44:52 PM PDT 24
Finished Jul 29 05:51:31 PM PDT 24
Peak memory 201444 kb
Host smart-6c82a824-0473-45c6-8e53-d8d1c22f6941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099241526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2099241526
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2997023469
Short name T492
Test name
Test status
Simulation time 348505479495 ps
CPU time 819.99 seconds
Started Jul 29 05:44:54 PM PDT 24
Finished Jul 29 05:58:34 PM PDT 24
Peak memory 201440 kb
Host smart-a44814c2-92cb-497e-b9c2-930bb21cd8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997023469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2997023469
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1444114
Short name T134
Test name
Test status
Simulation time 164521570395 ps
CPU time 399.2 seconds
Started Jul 29 05:44:48 PM PDT 24
Finished Jul 29 05:51:27 PM PDT 24
Peak memory 201440 kb
Host smart-749998a1-a276-435d-b750-174ac036c79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1444114
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.985177188
Short name T467
Test name
Test status
Simulation time 162081921773 ps
CPU time 172.16 seconds
Started Jul 29 05:44:47 PM PDT 24
Finished Jul 29 05:47:39 PM PDT 24
Peak memory 201496 kb
Host smart-c5cfb291-93e9-47d4-a2e5-786c24facd80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=985177188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.985177188
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3890325759
Short name T628
Test name
Test status
Simulation time 321424325546 ps
CPU time 381.95 seconds
Started Jul 29 05:44:43 PM PDT 24
Finished Jul 29 05:51:06 PM PDT 24
Peak memory 201372 kb
Host smart-5a4b39a1-ebb5-464a-99ad-49c51b4225ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890325759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3890325759
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.799768198
Short name T321
Test name
Test status
Simulation time 388691081863 ps
CPU time 473.21 seconds
Started Jul 29 05:44:52 PM PDT 24
Finished Jul 29 05:52:45 PM PDT 24
Peak memory 201504 kb
Host smart-3a1c8f87-2420-4684-a5a9-57dad51167b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799768198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.799768198
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2191551546
Short name T373
Test name
Test status
Simulation time 91666957053 ps
CPU time 457.74 seconds
Started Jul 29 05:44:57 PM PDT 24
Finished Jul 29 05:52:35 PM PDT 24
Peak memory 201880 kb
Host smart-01f09e74-8f44-4486-9809-b5230d42ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191551546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2191551546
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2393351107
Short name T73
Test name
Test status
Simulation time 41633942294 ps
CPU time 95.64 seconds
Started Jul 29 05:45:00 PM PDT 24
Finished Jul 29 05:46:36 PM PDT 24
Peak memory 201364 kb
Host smart-f70283f8-b496-4197-ac2b-e04530a69e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393351107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2393351107
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4244899014
Short name T559
Test name
Test status
Simulation time 4645545144 ps
CPU time 10.47 seconds
Started Jul 29 05:44:52 PM PDT 24
Finished Jul 29 05:45:03 PM PDT 24
Peak memory 201304 kb
Host smart-702d5e55-0178-48e7-b250-6506b998b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244899014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4244899014
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3916232138
Short name T646
Test name
Test status
Simulation time 6109410076 ps
CPU time 4.37 seconds
Started Jul 29 05:44:43 PM PDT 24
Finished Jul 29 05:44:48 PM PDT 24
Peak memory 201316 kb
Host smart-b44cac1f-438e-4d83-9bae-4bc4e5ddb136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916232138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3916232138
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2574043354
Short name T237
Test name
Test status
Simulation time 52128913857 ps
CPU time 106.09 seconds
Started Jul 29 05:44:56 PM PDT 24
Finished Jul 29 05:46:42 PM PDT 24
Peak memory 209840 kb
Host smart-d17b447e-5f86-47aa-a7a5-077194f1379a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574043354 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2574043354
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2602249117
Short name T596
Test name
Test status
Simulation time 485722449 ps
CPU time 1.64 seconds
Started Jul 29 05:45:16 PM PDT 24
Finished Jul 29 05:45:18 PM PDT 24
Peak memory 201164 kb
Host smart-12957ad2-ee67-47aa-922a-361fe85deca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602249117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2602249117
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2211047316
Short name T771
Test name
Test status
Simulation time 166845903792 ps
CPU time 207 seconds
Started Jul 29 05:45:09 PM PDT 24
Finished Jul 29 05:48:36 PM PDT 24
Peak memory 201368 kb
Host smart-461bfd95-cdfd-4173-9d7b-cfe2678ca9ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211047316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2211047316
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2594933276
Short name T604
Test name
Test status
Simulation time 180718865164 ps
CPU time 398.52 seconds
Started Jul 29 05:45:14 PM PDT 24
Finished Jul 29 05:51:53 PM PDT 24
Peak memory 201592 kb
Host smart-368dfd91-f452-481a-87d1-b588e6f22869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594933276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2594933276
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2866777013
Short name T587
Test name
Test status
Simulation time 485925347709 ps
CPU time 582.91 seconds
Started Jul 29 05:45:03 PM PDT 24
Finished Jul 29 05:54:47 PM PDT 24
Peak memory 201400 kb
Host smart-e71068c3-bdec-43b3-bf03-f03b29181c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866777013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2866777013
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2242202223
Short name T479
Test name
Test status
Simulation time 163563704146 ps
CPU time 87.19 seconds
Started Jul 29 05:45:08 PM PDT 24
Finished Jul 29 05:46:35 PM PDT 24
Peak memory 201432 kb
Host smart-b4551cf1-aa09-4a7a-a02c-9a7aad60f175
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242202223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2242202223
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.976499355
Short name T712
Test name
Test status
Simulation time 493405029830 ps
CPU time 188.74 seconds
Started Jul 29 05:44:59 PM PDT 24
Finished Jul 29 05:48:08 PM PDT 24
Peak memory 201460 kb
Host smart-7c155584-e31d-4eb3-9d68-c512e2202834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976499355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.976499355
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1899669194
Short name T401
Test name
Test status
Simulation time 157907881651 ps
CPU time 347.44 seconds
Started Jul 29 05:45:05 PM PDT 24
Finished Jul 29 05:50:53 PM PDT 24
Peak memory 201448 kb
Host smart-c2ed378b-8533-470d-970e-0d783629565d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899669194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1899669194
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.485991267
Short name T289
Test name
Test status
Simulation time 175358687462 ps
CPU time 164.9 seconds
Started Jul 29 05:45:07 PM PDT 24
Finished Jul 29 05:47:52 PM PDT 24
Peak memory 201456 kb
Host smart-b1fe3132-9a57-4a7a-9cf9-080188528a71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485991267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.485991267
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2017194565
Short name T656
Test name
Test status
Simulation time 199156630518 ps
CPU time 167.27 seconds
Started Jul 29 05:45:07 PM PDT 24
Finished Jul 29 05:47:55 PM PDT 24
Peak memory 201432 kb
Host smart-7e1b0151-c639-454c-aa02-5c2dc61896df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017194565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2017194565
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1958271840
Short name T204
Test name
Test status
Simulation time 95371657228 ps
CPU time 357.2 seconds
Started Jul 29 05:45:12 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 201892 kb
Host smart-16c1893d-c0da-4a3e-9dbe-6e4a9ba66921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958271840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1958271840
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1173579609
Short name T642
Test name
Test status
Simulation time 33539816808 ps
CPU time 74.84 seconds
Started Jul 29 05:45:14 PM PDT 24
Finished Jul 29 05:46:29 PM PDT 24
Peak memory 201324 kb
Host smart-8f75eaae-7799-45f4-b6ba-417eb3e939c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173579609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1173579609
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1181655393
Short name T354
Test name
Test status
Simulation time 4999631779 ps
CPU time 3.68 seconds
Started Jul 29 05:45:16 PM PDT 24
Finished Jul 29 05:45:19 PM PDT 24
Peak memory 201344 kb
Host smart-4b1689b3-5374-4220-aa4d-6608134f9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181655393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1181655393
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.671662828
Short name T126
Test name
Test status
Simulation time 5646162128 ps
CPU time 10.17 seconds
Started Jul 29 05:45:01 PM PDT 24
Finished Jul 29 05:45:12 PM PDT 24
Peak memory 201380 kb
Host smart-e0354695-58c3-4e76-9bba-70df1e800bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671662828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.671662828
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.969602957
Short name T683
Test name
Test status
Simulation time 209312936898 ps
CPU time 449.23 seconds
Started Jul 29 05:45:19 PM PDT 24
Finished Jul 29 05:52:49 PM PDT 24
Peak memory 201440 kb
Host smart-4088b916-1aab-4d8b-b0d3-79af7ad59638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969602957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
969602957
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1212579501
Short name T15
Test name
Test status
Simulation time 45517208372 ps
CPU time 105.36 seconds
Started Jul 29 05:45:17 PM PDT 24
Finished Jul 29 05:47:02 PM PDT 24
Peak memory 209784 kb
Host smart-c67be0d0-bc8e-474e-a83b-577d945fc11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212579501 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1212579501
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2321977687
Short name T374
Test name
Test status
Simulation time 482801959 ps
CPU time 1.11 seconds
Started Jul 29 05:45:27 PM PDT 24
Finished Jul 29 05:45:28 PM PDT 24
Peak memory 201168 kb
Host smart-beea8617-1dab-445c-adf1-24c734e8d289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321977687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2321977687
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3642780827
Short name T106
Test name
Test status
Simulation time 337957940914 ps
CPU time 777.31 seconds
Started Jul 29 05:45:24 PM PDT 24
Finished Jul 29 05:58:21 PM PDT 24
Peak memory 201652 kb
Host smart-06ad92fb-4b0a-4ac5-af9f-fd6258c3760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642780827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3642780827
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2603187696
Short name T581
Test name
Test status
Simulation time 163650083781 ps
CPU time 352.8 seconds
Started Jul 29 05:45:17 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 201400 kb
Host smart-937617c7-6077-4572-a9b1-95d04d11bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603187696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2603187696
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2773917830
Short name T71
Test name
Test status
Simulation time 326887535713 ps
CPU time 138.19 seconds
Started Jul 29 05:45:19 PM PDT 24
Finished Jul 29 05:47:37 PM PDT 24
Peak memory 201412 kb
Host smart-0ac0a624-d140-434d-98fe-2ec07cdfbfed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773917830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2773917830
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2881350674
Short name T417
Test name
Test status
Simulation time 495489235193 ps
CPU time 1114.48 seconds
Started Jul 29 05:45:19 PM PDT 24
Finished Jul 29 06:03:54 PM PDT 24
Peak memory 201624 kb
Host smart-9507af9c-4832-4f76-befc-52e60c544cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881350674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2881350674
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3405672769
Short name T564
Test name
Test status
Simulation time 327519298393 ps
CPU time 362.57 seconds
Started Jul 29 05:45:18 PM PDT 24
Finished Jul 29 05:51:21 PM PDT 24
Peak memory 201428 kb
Host smart-76b18f6d-58dc-4240-9a78-a543421ff8c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405672769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3405672769
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1577286411
Short name T173
Test name
Test status
Simulation time 549350533077 ps
CPU time 125.26 seconds
Started Jul 29 05:45:24 PM PDT 24
Finished Jul 29 05:47:29 PM PDT 24
Peak memory 201428 kb
Host smart-d09bd803-f98b-4c6e-9324-4b2ce0f71d45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577286411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1577286411
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1766853336
Short name T477
Test name
Test status
Simulation time 190640195152 ps
CPU time 103.06 seconds
Started Jul 29 05:45:23 PM PDT 24
Finished Jul 29 05:47:06 PM PDT 24
Peak memory 201496 kb
Host smart-0931a23b-a4fc-4b0a-8fb1-1f0e24f09852
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766853336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1766853336
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2862166790
Short name T186
Test name
Test status
Simulation time 94202746012 ps
CPU time 335.8 seconds
Started Jul 29 05:45:23 PM PDT 24
Finished Jul 29 05:50:59 PM PDT 24
Peak memory 201824 kb
Host smart-aca609d8-01f2-4758-bd43-4dc8a353fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862166790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2862166790
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2216104730
Short name T551
Test name
Test status
Simulation time 34770120530 ps
CPU time 76.41 seconds
Started Jul 29 05:45:23 PM PDT 24
Finished Jul 29 05:46:40 PM PDT 24
Peak memory 201304 kb
Host smart-87126e9f-7b4f-4380-9d0a-9790ef1e1caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216104730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2216104730
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4256542170
Short name T496
Test name
Test status
Simulation time 5080088149 ps
CPU time 11.36 seconds
Started Jul 29 05:45:27 PM PDT 24
Finished Jul 29 05:45:38 PM PDT 24
Peak memory 201360 kb
Host smart-c5ad1f7d-271b-47a5-92c4-4dc005c84b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256542170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4256542170
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4125762955
Short name T548
Test name
Test status
Simulation time 5684710210 ps
CPU time 12.89 seconds
Started Jul 29 05:45:16 PM PDT 24
Finished Jul 29 05:45:29 PM PDT 24
Peak memory 201392 kb
Host smart-fbeff1db-7df7-4351-b4fe-163b83adf288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125762955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4125762955
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1083225467
Short name T532
Test name
Test status
Simulation time 445444832669 ps
CPU time 1328.3 seconds
Started Jul 29 05:45:28 PM PDT 24
Finished Jul 29 06:07:37 PM PDT 24
Peak memory 210068 kb
Host smart-54a184de-62ad-43fe-ae84-da221a21046c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083225467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1083225467
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4119169873
Short name T255
Test name
Test status
Simulation time 41596776504 ps
CPU time 101.56 seconds
Started Jul 29 05:45:27 PM PDT 24
Finished Jul 29 05:47:08 PM PDT 24
Peak memory 210552 kb
Host smart-6aba51f3-bea1-490a-9060-0f09615e27ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119169873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4119169873
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2238094475
Short name T546
Test name
Test status
Simulation time 556132812 ps
CPU time 0.84 seconds
Started Jul 29 05:45:41 PM PDT 24
Finished Jul 29 05:45:42 PM PDT 24
Peak memory 201248 kb
Host smart-08a04ad9-7c7f-41f8-934a-9f7c8c48a806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238094475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2238094475
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3360399251
Short name T131
Test name
Test status
Simulation time 508239462418 ps
CPU time 1112.51 seconds
Started Jul 29 05:45:34 PM PDT 24
Finished Jul 29 06:04:07 PM PDT 24
Peak memory 201388 kb
Host smart-2cb6eee8-25e9-4d37-9572-b1724605d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360399251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3360399251
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4277479781
Short name T653
Test name
Test status
Simulation time 166584068719 ps
CPU time 358.74 seconds
Started Jul 29 05:45:35 PM PDT 24
Finished Jul 29 05:51:34 PM PDT 24
Peak memory 201400 kb
Host smart-449c62e8-31a0-49ac-b152-e98e48feea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277479781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4277479781
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4056314694
Short name T423
Test name
Test status
Simulation time 501505708284 ps
CPU time 123.57 seconds
Started Jul 29 05:45:31 PM PDT 24
Finished Jul 29 05:47:35 PM PDT 24
Peak memory 201368 kb
Host smart-a9dcb375-36e3-412f-8d87-104f39e379fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056314694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4056314694
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1907255849
Short name T779
Test name
Test status
Simulation time 165060329730 ps
CPU time 185.53 seconds
Started Jul 29 05:45:36 PM PDT 24
Finished Jul 29 05:48:42 PM PDT 24
Peak memory 201452 kb
Host smart-2eecfc27-81d4-435b-8ec8-e264766aa510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907255849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1907255849
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2564231408
Short name T652
Test name
Test status
Simulation time 486657544066 ps
CPU time 557.74 seconds
Started Jul 29 05:45:32 PM PDT 24
Finished Jul 29 05:54:49 PM PDT 24
Peak memory 201460 kb
Host smart-8052f62f-17ce-42c0-86f3-bc97ffba6a1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564231408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2564231408
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.212120814
Short name T745
Test name
Test status
Simulation time 348849443566 ps
CPU time 191.9 seconds
Started Jul 29 05:45:32 PM PDT 24
Finished Jul 29 05:48:44 PM PDT 24
Peak memory 201440 kb
Host smart-3ef5ec54-94f2-4891-998e-99556578d898
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212120814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.212120814
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.922189575
Short name T765
Test name
Test status
Simulation time 201681367745 ps
CPU time 118.89 seconds
Started Jul 29 05:45:37 PM PDT 24
Finished Jul 29 05:47:36 PM PDT 24
Peak memory 201452 kb
Host smart-383c44e2-83f7-44b2-a213-e1be86ffe0ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922189575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.922189575
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.73941878
Short name T586
Test name
Test status
Simulation time 30410259729 ps
CPU time 18.4 seconds
Started Jul 29 05:45:36 PM PDT 24
Finished Jul 29 05:45:54 PM PDT 24
Peak memory 201304 kb
Host smart-78364736-81ba-42f3-aa40-c70f78f417e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73941878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.73941878
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1415776361
Short name T434
Test name
Test status
Simulation time 3262525763 ps
CPU time 2.58 seconds
Started Jul 29 05:45:38 PM PDT 24
Finished Jul 29 05:45:41 PM PDT 24
Peak memory 201352 kb
Host smart-587f449a-b3ef-40f3-88b5-8d82333550c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415776361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1415776361
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1408452242
Short name T631
Test name
Test status
Simulation time 5902473601 ps
CPU time 13.73 seconds
Started Jul 29 05:45:29 PM PDT 24
Finished Jul 29 05:45:42 PM PDT 24
Peak memory 201360 kb
Host smart-56271f3a-cf0d-42bb-a41c-d8584ddbcb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408452242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1408452242
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.5482222
Short name T540
Test name
Test status
Simulation time 463137203216 ps
CPU time 1535.18 seconds
Started Jul 29 05:45:42 PM PDT 24
Finished Jul 29 06:11:18 PM PDT 24
Peak memory 210044 kb
Host smart-7776724f-47fa-4bd4-bf74-3ed05aefbf84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5482222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.5482222
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2351762242
Short name T357
Test name
Test status
Simulation time 419432902 ps
CPU time 1.07 seconds
Started Jul 29 05:45:52 PM PDT 24
Finished Jul 29 05:45:53 PM PDT 24
Peak memory 201164 kb
Host smart-6c470307-aa66-4ccb-b2fa-86493e6368b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351762242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2351762242
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3701203983
Short name T751
Test name
Test status
Simulation time 348177185426 ps
CPU time 283.23 seconds
Started Jul 29 05:45:49 PM PDT 24
Finished Jul 29 05:50:32 PM PDT 24
Peak memory 201392 kb
Host smart-957a095d-48b1-4033-8344-90c04f8364b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701203983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3701203983
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1664958094
Short name T258
Test name
Test status
Simulation time 175838112322 ps
CPU time 109.01 seconds
Started Jul 29 05:45:48 PM PDT 24
Finished Jul 29 05:47:37 PM PDT 24
Peak memory 201452 kb
Host smart-fc46f47e-b1d6-4e54-a8aa-f9ef932c149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664958094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1664958094
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2231010714
Short name T565
Test name
Test status
Simulation time 331123555628 ps
CPU time 695.28 seconds
Started Jul 29 05:45:46 PM PDT 24
Finished Jul 29 05:57:22 PM PDT 24
Peak memory 201444 kb
Host smart-49ee6055-b88c-4def-9e50-000d7f398488
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231010714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2231010714
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.455610680
Short name T445
Test name
Test status
Simulation time 325596200175 ps
CPU time 734.61 seconds
Started Jul 29 05:45:46 PM PDT 24
Finished Jul 29 05:58:00 PM PDT 24
Peak memory 201448 kb
Host smart-41db9ac3-1f98-43ef-ad72-525d0f1fad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455610680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.455610680
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2208728243
Short name T533
Test name
Test status
Simulation time 165004894674 ps
CPU time 272.07 seconds
Started Jul 29 05:45:45 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 201400 kb
Host smart-f7bc875b-d55a-453d-a2c6-e8257a1e48f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208728243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2208728243
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1610646224
Short name T281
Test name
Test status
Simulation time 178007298834 ps
CPU time 125.42 seconds
Started Jul 29 05:45:44 PM PDT 24
Finished Jul 29 05:47:50 PM PDT 24
Peak memory 201324 kb
Host smart-e69c878f-9786-44c6-8262-54cd00eaf7cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610646224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1610646224
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1678913515
Short name T734
Test name
Test status
Simulation time 202700513922 ps
CPU time 211.64 seconds
Started Jul 29 05:45:47 PM PDT 24
Finished Jul 29 05:49:18 PM PDT 24
Peak memory 201456 kb
Host smart-239e563e-7de8-48b5-99d6-2f6f1eba0ec4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678913515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1678913515
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3185954124
Short name T522
Test name
Test status
Simulation time 89561189674 ps
CPU time 279.71 seconds
Started Jul 29 05:45:47 PM PDT 24
Finished Jul 29 05:50:27 PM PDT 24
Peak memory 201772 kb
Host smart-57595e19-af13-48c9-944d-3954e08785e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185954124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3185954124
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1993688042
Short name T692
Test name
Test status
Simulation time 28993733323 ps
CPU time 15.59 seconds
Started Jul 29 05:45:50 PM PDT 24
Finished Jul 29 05:46:05 PM PDT 24
Peak memory 201356 kb
Host smart-8d1f0238-12a0-41df-b233-fe5decb4f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993688042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1993688042
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.933180764
Short name T645
Test name
Test status
Simulation time 3445300641 ps
CPU time 2.57 seconds
Started Jul 29 05:45:48 PM PDT 24
Finished Jul 29 05:45:50 PM PDT 24
Peak memory 201344 kb
Host smart-fc5fba63-775d-4235-a1ea-ba6523534f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933180764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.933180764
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1589024454
Short name T571
Test name
Test status
Simulation time 5835536957 ps
CPU time 14 seconds
Started Jul 29 05:45:45 PM PDT 24
Finished Jul 29 05:45:59 PM PDT 24
Peak memory 201340 kb
Host smart-6d0606f2-9f94-4085-bf7f-73c1718faa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589024454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1589024454
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2003823107
Short name T202
Test name
Test status
Simulation time 626807586206 ps
CPU time 815.05 seconds
Started Jul 29 05:45:53 PM PDT 24
Finished Jul 29 05:59:29 PM PDT 24
Peak memory 210080 kb
Host smart-d71e1b47-30e8-499b-b679-701d7cd57ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003823107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2003823107
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2136269993
Short name T20
Test name
Test status
Simulation time 103521825269 ps
CPU time 225.91 seconds
Started Jul 29 05:45:54 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 210176 kb
Host smart-56f2e587-4c48-48d6-ac19-7622c4033f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136269993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2136269993
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2174129636
Short name T691
Test name
Test status
Simulation time 423955892 ps
CPU time 1.51 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:40:09 PM PDT 24
Peak memory 201248 kb
Host smart-eef09d88-3955-4ffd-b09c-f68c7832fddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174129636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2174129636
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2940007905
Short name T309
Test name
Test status
Simulation time 330968186498 ps
CPU time 683.5 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:51:31 PM PDT 24
Peak memory 201388 kb
Host smart-bee6ad63-d853-4929-9a11-8307ca67e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940007905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2940007905
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3782099006
Short name T746
Test name
Test status
Simulation time 161975479570 ps
CPU time 135.87 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:42:23 PM PDT 24
Peak memory 201472 kb
Host smart-30075167-8096-4f16-ba7f-c87b11e66fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782099006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3782099006
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3304770135
Short name T676
Test name
Test status
Simulation time 323732806906 ps
CPU time 189.65 seconds
Started Jul 29 05:40:09 PM PDT 24
Finished Jul 29 05:43:19 PM PDT 24
Peak memory 201460 kb
Host smart-ccc6f0e3-f08a-45c1-a236-65c93a0ab84f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304770135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3304770135
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3808784143
Short name T182
Test name
Test status
Simulation time 491184749989 ps
CPU time 295.13 seconds
Started Jul 29 05:40:11 PM PDT 24
Finished Jul 29 05:45:07 PM PDT 24
Peak memory 201448 kb
Host smart-bf9dc37c-c3ff-43f3-9741-b516b4ed1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808784143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3808784143
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2567808947
Short name T766
Test name
Test status
Simulation time 327082732604 ps
CPU time 535.69 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:49:03 PM PDT 24
Peak memory 201424 kb
Host smart-cafa575d-ac8e-4803-9169-790c38d8ba90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567808947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2567808947
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2551616859
Short name T175
Test name
Test status
Simulation time 192363389679 ps
CPU time 111.7 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:42:02 PM PDT 24
Peak memory 201424 kb
Host smart-c19e34b9-b63a-4dd0-a501-c28e2228c7c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551616859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2551616859
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2039536826
Short name T189
Test name
Test status
Simulation time 90143441375 ps
CPU time 406.56 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:46:54 PM PDT 24
Peak memory 201832 kb
Host smart-641a1257-765c-43c4-83b5-9b43443bec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039536826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2039536826
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4016928659
Short name T138
Test name
Test status
Simulation time 35467988486 ps
CPU time 40.58 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:40:47 PM PDT 24
Peak memory 201328 kb
Host smart-47c64b2c-53d7-4829-8a90-97e0fd56262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016928659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4016928659
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1061821095
Short name T578
Test name
Test status
Simulation time 4817869858 ps
CPU time 11.85 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:40:19 PM PDT 24
Peak memory 201248 kb
Host smart-3a6516fb-b50f-436f-967b-134eb03f21e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061821095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1061821095
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.228844172
Short name T67
Test name
Test status
Simulation time 8071838542 ps
CPU time 9.79 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:40:18 PM PDT 24
Peak memory 218256 kb
Host smart-69328bdb-3d22-481c-a819-96eaaa472e2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228844172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.228844172
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4069903056
Short name T536
Test name
Test status
Simulation time 5851475163 ps
CPU time 7.09 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:40:15 PM PDT 24
Peak memory 201380 kb
Host smart-d65f1f8f-e7a0-4be5-bf49-1ecb5c749fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069903056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4069903056
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1801487854
Short name T198
Test name
Test status
Simulation time 140278199126 ps
CPU time 723.75 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:52:12 PM PDT 24
Peak memory 201876 kb
Host smart-b44ef966-0773-401e-ae10-bb9485170658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801487854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1801487854
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2108057179
Short name T465
Test name
Test status
Simulation time 321370562 ps
CPU time 0.79 seconds
Started Jul 29 05:46:07 PM PDT 24
Finished Jul 29 05:46:08 PM PDT 24
Peak memory 201248 kb
Host smart-ea9c8402-49fb-4653-b7f4-aacc982a2c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108057179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2108057179
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2697450758
Short name T290
Test name
Test status
Simulation time 172700255136 ps
CPU time 98.24 seconds
Started Jul 29 05:46:02 PM PDT 24
Finished Jul 29 05:47:40 PM PDT 24
Peak memory 201488 kb
Host smart-c008aa07-f647-48c5-ac88-b12474098aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697450758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2697450758
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.465984034
Short name T572
Test name
Test status
Simulation time 166281413454 ps
CPU time 371.5 seconds
Started Jul 29 05:45:59 PM PDT 24
Finished Jul 29 05:52:10 PM PDT 24
Peak memory 201444 kb
Host smart-baea4627-a85d-4d3b-91f4-86b551d01d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465984034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.465984034
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1839703035
Short name T670
Test name
Test status
Simulation time 164042906229 ps
CPU time 373.34 seconds
Started Jul 29 05:46:02 PM PDT 24
Finished Jul 29 05:52:15 PM PDT 24
Peak memory 201360 kb
Host smart-e87b7fb2-7096-4f45-8535-e0da5ddaae92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839703035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1839703035
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1449381353
Short name T284
Test name
Test status
Simulation time 486596353312 ps
CPU time 1096.35 seconds
Started Jul 29 05:45:58 PM PDT 24
Finished Jul 29 06:04:14 PM PDT 24
Peak memory 201668 kb
Host smart-aefed04f-4735-49fb-918f-71fd55a3b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449381353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1449381353
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2226234059
Short name T159
Test name
Test status
Simulation time 163926142619 ps
CPU time 94.8 seconds
Started Jul 29 05:45:59 PM PDT 24
Finished Jul 29 05:47:34 PM PDT 24
Peak memory 201588 kb
Host smart-02880d41-b0f0-4be7-8b92-12abd77c5891
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226234059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2226234059
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.892105968
Short name T407
Test name
Test status
Simulation time 191749270078 ps
CPU time 405.34 seconds
Started Jul 29 05:46:03 PM PDT 24
Finished Jul 29 05:52:48 PM PDT 24
Peak memory 201436 kb
Host smart-7a8429d9-d312-4c96-937d-1701bee31f0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892105968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.892105968
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1873054288
Short name T648
Test name
Test status
Simulation time 102040958381 ps
CPU time 365.1 seconds
Started Jul 29 05:46:09 PM PDT 24
Finished Jul 29 05:52:14 PM PDT 24
Peak memory 201864 kb
Host smart-3d683f74-af02-42e7-975f-a931df6286ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873054288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1873054288
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1796233699
Short name T5
Test name
Test status
Simulation time 29245077799 ps
CPU time 6 seconds
Started Jul 29 05:46:07 PM PDT 24
Finished Jul 29 05:46:13 PM PDT 24
Peak memory 201244 kb
Host smart-3c8e356a-a757-4a90-8d94-0abfe5e6bc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796233699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1796233699
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.547444245
Short name T490
Test name
Test status
Simulation time 5366843086 ps
CPU time 6.36 seconds
Started Jul 29 05:46:07 PM PDT 24
Finished Jul 29 05:46:13 PM PDT 24
Peak memory 201316 kb
Host smart-2a0c0b51-3d57-47a6-b296-a132eecd8dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547444245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.547444245
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2286575823
Short name T667
Test name
Test status
Simulation time 6023526802 ps
CPU time 13.7 seconds
Started Jul 29 05:45:55 PM PDT 24
Finished Jul 29 05:46:09 PM PDT 24
Peak memory 201340 kb
Host smart-90ce7819-71b6-4daa-8b62-0665cb9f0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286575823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2286575823
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2237919042
Short name T719
Test name
Test status
Simulation time 365338940 ps
CPU time 0.81 seconds
Started Jul 29 05:46:25 PM PDT 24
Finished Jul 29 05:46:26 PM PDT 24
Peak memory 201204 kb
Host smart-3cb5ac9b-c96b-4f2f-8fd1-bfc8697d0d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237919042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2237919042
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2310730632
Short name T600
Test name
Test status
Simulation time 337752304964 ps
CPU time 208.05 seconds
Started Jul 29 05:46:16 PM PDT 24
Finished Jul 29 05:49:44 PM PDT 24
Peak memory 201396 kb
Host smart-75e6ddbc-4793-4a8e-b2d2-42269738b4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310730632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2310730632
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3248745653
Short name T140
Test name
Test status
Simulation time 324116673420 ps
CPU time 698.03 seconds
Started Jul 29 05:46:12 PM PDT 24
Finished Jul 29 05:57:50 PM PDT 24
Peak memory 201484 kb
Host smart-4a3daab7-1454-48dd-8b86-ec5cc63378c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248745653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3248745653
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3160115049
Short name T524
Test name
Test status
Simulation time 488549040269 ps
CPU time 1196.45 seconds
Started Jul 29 05:46:12 PM PDT 24
Finished Jul 29 06:06:09 PM PDT 24
Peak memory 201376 kb
Host smart-9cc8b456-d5be-4565-bcd4-cfe65e8ee123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160115049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3160115049
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3506615381
Short name T590
Test name
Test status
Simulation time 160789828497 ps
CPU time 386.47 seconds
Started Jul 29 05:46:11 PM PDT 24
Finished Jul 29 05:52:37 PM PDT 24
Peak memory 201496 kb
Host smart-5b80ef6a-11f2-4552-9365-18d446f89dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506615381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3506615381
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2735007855
Short name T441
Test name
Test status
Simulation time 162133583793 ps
CPU time 197.24 seconds
Started Jul 29 05:46:11 PM PDT 24
Finished Jul 29 05:49:28 PM PDT 24
Peak memory 201460 kb
Host smart-ea5cf394-5e7c-4646-b40b-ced0ca88eb10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735007855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2735007855
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2084356063
Short name T610
Test name
Test status
Simulation time 340608231294 ps
CPU time 200.26 seconds
Started Jul 29 05:46:11 PM PDT 24
Finished Jul 29 05:49:31 PM PDT 24
Peak memory 201444 kb
Host smart-ee34bef5-1074-474f-9de6-38da929f9705
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084356063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2084356063
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1020883123
Short name T754
Test name
Test status
Simulation time 615868383190 ps
CPU time 349.14 seconds
Started Jul 29 05:46:15 PM PDT 24
Finished Jul 29 05:52:05 PM PDT 24
Peak memory 201432 kb
Host smart-f2c04b1d-46b7-44f8-8d7c-95cb832198f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020883123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1020883123
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1050795533
Short name T764
Test name
Test status
Simulation time 22481392250 ps
CPU time 25.07 seconds
Started Jul 29 05:46:20 PM PDT 24
Finished Jul 29 05:46:45 PM PDT 24
Peak memory 201284 kb
Host smart-33e67500-4084-4af1-9049-885c3791df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050795533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1050795533
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3717408604
Short name T396
Test name
Test status
Simulation time 3749470424 ps
CPU time 2.97 seconds
Started Jul 29 05:46:15 PM PDT 24
Finished Jul 29 05:46:18 PM PDT 24
Peak memory 201344 kb
Host smart-b22837d6-e8b6-4bcb-9d40-7caf7d525295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717408604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3717408604
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.581849789
Short name T702
Test name
Test status
Simulation time 5989029350 ps
CPU time 7.53 seconds
Started Jul 29 05:46:11 PM PDT 24
Finished Jul 29 05:46:18 PM PDT 24
Peak memory 201316 kb
Host smart-cb98a94e-bfad-4eea-ade1-f1b454363a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581849789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.581849789
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2223980449
Short name T196
Test name
Test status
Simulation time 85504023057 ps
CPU time 328.03 seconds
Started Jul 29 05:46:23 PM PDT 24
Finished Jul 29 05:51:51 PM PDT 24
Peak memory 201752 kb
Host smart-08b56384-f6eb-43b0-b093-5560ace2ce47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223980449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2223980449
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2042576862
Short name T230
Test name
Test status
Simulation time 46907651833 ps
CPU time 107.5 seconds
Started Jul 29 05:46:20 PM PDT 24
Finished Jul 29 05:48:07 PM PDT 24
Peak memory 209772 kb
Host smart-c098a7b5-8be2-4eac-b6e5-2da71f604bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042576862 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2042576862
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3533925197
Short name T420
Test name
Test status
Simulation time 360109405 ps
CPU time 1.49 seconds
Started Jul 29 05:46:37 PM PDT 24
Finished Jul 29 05:46:39 PM PDT 24
Peak memory 201248 kb
Host smart-a4f82cf6-8685-4409-91a4-12b2abfc6d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533925197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3533925197
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2532091642
Short name T394
Test name
Test status
Simulation time 161901406255 ps
CPU time 188.24 seconds
Started Jul 29 05:46:35 PM PDT 24
Finished Jul 29 05:49:43 PM PDT 24
Peak memory 201496 kb
Host smart-9ea523d6-b438-43e2-9736-ab921ea58c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532091642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2532091642
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1187060779
Short name T246
Test name
Test status
Simulation time 485777191891 ps
CPU time 1054.62 seconds
Started Jul 29 05:46:29 PM PDT 24
Finished Jul 29 06:04:04 PM PDT 24
Peak memory 201460 kb
Host smart-f92dc3ab-4d01-49da-ab0a-af41c4d9dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187060779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1187060779
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4032962725
Short name T393
Test name
Test status
Simulation time 323913670810 ps
CPU time 78.31 seconds
Started Jul 29 05:46:28 PM PDT 24
Finished Jul 29 05:47:47 PM PDT 24
Peak memory 201416 kb
Host smart-6b1bf60b-6d9f-4fb7-93b7-ee51579e6ee3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032962725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4032962725
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2868738007
Short name T264
Test name
Test status
Simulation time 327233199362 ps
CPU time 783.26 seconds
Started Jul 29 05:46:25 PM PDT 24
Finished Jul 29 05:59:28 PM PDT 24
Peak memory 201472 kb
Host smart-dd663bec-ded7-4499-be15-948d8382df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868738007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2868738007
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3274209881
Short name T694
Test name
Test status
Simulation time 318470540889 ps
CPU time 196.18 seconds
Started Jul 29 05:46:26 PM PDT 24
Finished Jul 29 05:49:42 PM PDT 24
Peak memory 201420 kb
Host smart-7290dd0c-5dbf-4e63-9196-7c39ea114956
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274209881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3274209881
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4233290215
Short name T493
Test name
Test status
Simulation time 192678675666 ps
CPU time 327.57 seconds
Started Jul 29 05:46:33 PM PDT 24
Finished Jul 29 05:52:01 PM PDT 24
Peak memory 201396 kb
Host smart-c20e0c44-ea08-4c92-b64a-a5e7dcb599ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233290215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4233290215
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.404050622
Short name T208
Test name
Test status
Simulation time 124900828181 ps
CPU time 450.22 seconds
Started Jul 29 05:46:32 PM PDT 24
Finished Jul 29 05:54:02 PM PDT 24
Peak memory 201832 kb
Host smart-6e9d1eeb-98a4-4189-b696-c7c133999048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404050622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.404050622
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1657780957
Short name T607
Test name
Test status
Simulation time 23460029799 ps
CPU time 48.51 seconds
Started Jul 29 05:46:33 PM PDT 24
Finished Jul 29 05:47:22 PM PDT 24
Peak memory 201324 kb
Host smart-afeff5f3-8a31-48c9-bfbe-dff62d607ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657780957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1657780957
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3678399367
Short name T655
Test name
Test status
Simulation time 3965422134 ps
CPU time 9.49 seconds
Started Jul 29 05:46:32 PM PDT 24
Finished Jul 29 05:46:42 PM PDT 24
Peak memory 201352 kb
Host smart-8b035e9f-7bd1-4932-863a-67381433a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678399367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3678399367
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.786978545
Short name T575
Test name
Test status
Simulation time 6114788938 ps
CPU time 14.63 seconds
Started Jul 29 05:46:26 PM PDT 24
Finished Jul 29 05:46:41 PM PDT 24
Peak memory 201380 kb
Host smart-63c9f378-f2c0-41df-9c0a-6368544a3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786978545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.786978545
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.451371832
Short name T566
Test name
Test status
Simulation time 344648036786 ps
CPU time 831.44 seconds
Started Jul 29 05:46:37 PM PDT 24
Finished Jul 29 06:00:29 PM PDT 24
Peak memory 201412 kb
Host smart-6c4218df-aad5-4c2e-8f19-65cb855a5958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451371832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
451371832
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4178791414
Short name T337
Test name
Test status
Simulation time 377119755 ps
CPU time 0.99 seconds
Started Jul 29 05:46:50 PM PDT 24
Finished Jul 29 05:46:51 PM PDT 24
Peak memory 201124 kb
Host smart-eb5d93b0-f2a5-475d-89ed-c06a031191d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178791414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4178791414
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2634557817
Short name T161
Test name
Test status
Simulation time 344880953010 ps
CPU time 211.73 seconds
Started Jul 29 05:46:41 PM PDT 24
Finished Jul 29 05:50:13 PM PDT 24
Peak memory 201440 kb
Host smart-93191d07-a0e5-4cb1-a93a-d2befa67a81e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634557817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2634557817
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2875317219
Short name T717
Test name
Test status
Simulation time 170164098361 ps
CPU time 80.96 seconds
Started Jul 29 05:46:45 PM PDT 24
Finished Jul 29 05:48:06 PM PDT 24
Peak memory 201404 kb
Host smart-452f7c47-42ff-48b3-bdfd-8fb4f6e0b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875317219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2875317219
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2444747759
Short name T785
Test name
Test status
Simulation time 165737792027 ps
CPU time 368.35 seconds
Started Jul 29 05:46:44 PM PDT 24
Finished Jul 29 05:52:52 PM PDT 24
Peak memory 201452 kb
Host smart-1d21c258-323e-425d-ba01-0002dbe8942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444747759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2444747759
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2936692101
Short name T611
Test name
Test status
Simulation time 163816675468 ps
CPU time 171.78 seconds
Started Jul 29 05:46:42 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 201388 kb
Host smart-f0f8848c-7235-4664-8969-12980ec4afdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936692101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2936692101
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4274599821
Short name T148
Test name
Test status
Simulation time 325187760327 ps
CPU time 190.37 seconds
Started Jul 29 05:46:36 PM PDT 24
Finished Jul 29 05:49:46 PM PDT 24
Peak memory 201452 kb
Host smart-7a7c7dbc-930a-4f05-9a70-9282dd27b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274599821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4274599821
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3652216453
Short name T624
Test name
Test status
Simulation time 322068548315 ps
CPU time 201.34 seconds
Started Jul 29 05:46:45 PM PDT 24
Finished Jul 29 05:50:07 PM PDT 24
Peak memory 201468 kb
Host smart-e3765d65-b9a0-4bbe-aacd-e34bf8773411
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652216453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3652216453
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.660287550
Short name T429
Test name
Test status
Simulation time 193016029311 ps
CPU time 389.07 seconds
Started Jul 29 05:46:43 PM PDT 24
Finished Jul 29 05:53:13 PM PDT 24
Peak memory 201468 kb
Host smart-13496620-3890-4f13-b763-009255a5d9eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660287550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.660287550
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3560901176
Short name T621
Test name
Test status
Simulation time 66128893607 ps
CPU time 251.4 seconds
Started Jul 29 05:46:48 PM PDT 24
Finished Jul 29 05:50:59 PM PDT 24
Peak memory 201816 kb
Host smart-703de3b3-ef4f-46a8-97ae-90ab450ebd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560901176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3560901176
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1615809084
Short name T411
Test name
Test status
Simulation time 41359407880 ps
CPU time 21.89 seconds
Started Jul 29 05:46:45 PM PDT 24
Finished Jul 29 05:47:07 PM PDT 24
Peak memory 201372 kb
Host smart-3e638d2c-ab35-45e3-9c21-95f36b9e59b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615809084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1615809084
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.435449131
Short name T537
Test name
Test status
Simulation time 5368047874 ps
CPU time 3.67 seconds
Started Jul 29 05:46:45 PM PDT 24
Finished Jul 29 05:46:49 PM PDT 24
Peak memory 201328 kb
Host smart-73390d3f-bf80-45ca-9956-3346ca17ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435449131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.435449131
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2492518554
Short name T470
Test name
Test status
Simulation time 5795080796 ps
CPU time 4.18 seconds
Started Jul 29 05:46:36 PM PDT 24
Finished Jul 29 05:46:40 PM PDT 24
Peak memory 201372 kb
Host smart-4f63ecb2-60e0-4be8-b76e-a829074b4190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492518554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2492518554
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1741796511
Short name T777
Test name
Test status
Simulation time 418152686 ps
CPU time 1.37 seconds
Started Jul 29 05:47:03 PM PDT 24
Finished Jul 29 05:47:04 PM PDT 24
Peak memory 201248 kb
Host smart-6c6566aa-373d-46bb-a2a5-90ea5ec1678e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741796511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1741796511
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4103796121
Short name T299
Test name
Test status
Simulation time 165411856186 ps
CPU time 139.68 seconds
Started Jul 29 05:46:49 PM PDT 24
Finished Jul 29 05:49:09 PM PDT 24
Peak memory 201464 kb
Host smart-c8bede56-cbbd-4da5-b3cd-755bd4cd981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103796121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4103796121
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2494709979
Short name T99
Test name
Test status
Simulation time 325552174418 ps
CPU time 184.66 seconds
Started Jul 29 05:46:54 PM PDT 24
Finished Jul 29 05:49:59 PM PDT 24
Peak memory 201392 kb
Host smart-cd3d9ff9-473f-4fef-9f21-a7d6942c756f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494709979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2494709979
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3091149589
Short name T226
Test name
Test status
Simulation time 327036231006 ps
CPU time 173.13 seconds
Started Jul 29 05:46:49 PM PDT 24
Finished Jul 29 05:49:42 PM PDT 24
Peak memory 201432 kb
Host smart-ad771f1a-e925-4aae-a0d9-7d727687e96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091149589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3091149589
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2376993762
Short name T320
Test name
Test status
Simulation time 484329429307 ps
CPU time 291.9 seconds
Started Jul 29 05:46:48 PM PDT 24
Finished Jul 29 05:51:40 PM PDT 24
Peak memory 201416 kb
Host smart-7901b723-76d8-4c22-a257-69588301c640
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376993762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2376993762
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1524394794
Short name T266
Test name
Test status
Simulation time 172266472813 ps
CPU time 98.49 seconds
Started Jul 29 05:46:54 PM PDT 24
Finished Jul 29 05:48:33 PM PDT 24
Peak memory 201464 kb
Host smart-8cd49d15-53ad-4717-9d27-e41ea82955d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524394794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1524394794
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3523276543
Short name T472
Test name
Test status
Simulation time 611415163350 ps
CPU time 461.75 seconds
Started Jul 29 05:46:53 PM PDT 24
Finished Jul 29 05:54:35 PM PDT 24
Peak memory 201392 kb
Host smart-e9333b87-8876-4e51-a35b-819253eacabb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523276543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3523276543
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2152733066
Short name T449
Test name
Test status
Simulation time 90910073425 ps
CPU time 276.29 seconds
Started Jul 29 05:46:58 PM PDT 24
Finished Jul 29 05:51:34 PM PDT 24
Peak memory 201764 kb
Host smart-f4093f5b-a0cb-4c6e-bd6a-b0ab981a4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152733066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2152733066
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3171566198
Short name T789
Test name
Test status
Simulation time 29127542941 ps
CPU time 34.67 seconds
Started Jul 29 05:46:59 PM PDT 24
Finished Jul 29 05:47:34 PM PDT 24
Peak memory 201348 kb
Host smart-cd2a98ab-6382-466f-9834-05f350076af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171566198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3171566198
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3059172681
Short name T595
Test name
Test status
Simulation time 3518293993 ps
CPU time 1.95 seconds
Started Jul 29 05:46:54 PM PDT 24
Finished Jul 29 05:46:56 PM PDT 24
Peak memory 201344 kb
Host smart-a270738b-478e-4306-aabd-2ef54ed7e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059172681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3059172681
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2698756261
Short name T383
Test name
Test status
Simulation time 5783741294 ps
CPU time 7.21 seconds
Started Jul 29 05:46:49 PM PDT 24
Finished Jul 29 05:46:56 PM PDT 24
Peak memory 201308 kb
Host smart-0afd3ea0-5f74-4ea6-a290-887039d2e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698756261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2698756261
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2451845664
Short name T661
Test name
Test status
Simulation time 331822412447 ps
CPU time 599.44 seconds
Started Jul 29 05:47:03 PM PDT 24
Finished Jul 29 05:57:03 PM PDT 24
Peak memory 201764 kb
Host smart-a6857d0c-350d-4124-984f-1824e63a0efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451845664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2451845664
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1214347386
Short name T184
Test name
Test status
Simulation time 78719263256 ps
CPU time 101.03 seconds
Started Jul 29 05:46:59 PM PDT 24
Finished Jul 29 05:48:40 PM PDT 24
Peak memory 210104 kb
Host smart-9c53c3cb-4956-4053-9ae0-75da0a278b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214347386 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1214347386
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2953199104
Short name T432
Test name
Test status
Simulation time 565940705 ps
CPU time 0.73 seconds
Started Jul 29 05:47:13 PM PDT 24
Finished Jul 29 05:47:14 PM PDT 24
Peak memory 201248 kb
Host smart-73bb92d6-ba2e-4812-8be5-7276ba0a8289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953199104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2953199104
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1024048267
Short name T142
Test name
Test status
Simulation time 177866064122 ps
CPU time 387.55 seconds
Started Jul 29 05:47:07 PM PDT 24
Finished Jul 29 05:53:35 PM PDT 24
Peak memory 201396 kb
Host smart-5aae78e1-da2a-4a0f-920f-67409ef3fce5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024048267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1024048267
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1339190992
Short name T224
Test name
Test status
Simulation time 332097138536 ps
CPU time 716.73 seconds
Started Jul 29 05:47:05 PM PDT 24
Finished Jul 29 05:59:02 PM PDT 24
Peak memory 201428 kb
Host smart-71e2c5bb-421d-4a7d-bfbf-07449c2e77dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339190992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1339190992
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1959070953
Short name T137
Test name
Test status
Simulation time 166964116298 ps
CPU time 355.5 seconds
Started Jul 29 05:47:07 PM PDT 24
Finished Jul 29 05:53:02 PM PDT 24
Peak memory 201340 kb
Host smart-3b467fb5-d46f-4d21-bcb2-a8836e7f93c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959070953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1959070953
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3193793853
Short name T223
Test name
Test status
Simulation time 489744568212 ps
CPU time 298.39 seconds
Started Jul 29 05:47:07 PM PDT 24
Finished Jul 29 05:52:06 PM PDT 24
Peak memory 201664 kb
Host smart-d839b74e-3838-442f-a964-57aa489eea6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193793853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3193793853
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.194413780
Short name T277
Test name
Test status
Simulation time 491332935012 ps
CPU time 599.73 seconds
Started Jul 29 05:47:03 PM PDT 24
Finished Jul 29 05:57:03 PM PDT 24
Peak memory 201416 kb
Host smart-963e00d4-6194-4191-8aa9-b7e5ae94790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194413780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.194413780
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1174957495
Short name T791
Test name
Test status
Simulation time 333881904183 ps
CPU time 398.21 seconds
Started Jul 29 05:47:02 PM PDT 24
Finished Jul 29 05:53:40 PM PDT 24
Peak memory 201388 kb
Host smart-6fbfb283-58ed-4c83-9d8c-89e9ad173a62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174957495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1174957495
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3104167995
Short name T286
Test name
Test status
Simulation time 597834630839 ps
CPU time 1346.47 seconds
Started Jul 29 05:47:09 PM PDT 24
Finished Jul 29 06:09:36 PM PDT 24
Peak memory 201472 kb
Host smart-c0b3faa6-5497-42d1-b5b4-b9abe8fed981
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104167995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3104167995
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.954057439
Short name T588
Test name
Test status
Simulation time 595977459502 ps
CPU time 1338.96 seconds
Started Jul 29 05:47:07 PM PDT 24
Finished Jul 29 06:09:26 PM PDT 24
Peak memory 201364 kb
Host smart-20c43f30-bc16-4374-8227-e954479e65e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954057439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.954057439
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1909557528
Short name T558
Test name
Test status
Simulation time 94569071038 ps
CPU time 502.17 seconds
Started Jul 29 05:47:12 PM PDT 24
Finished Jul 29 05:55:34 PM PDT 24
Peak memory 201840 kb
Host smart-af5c5f74-82c8-415f-bee6-2b97adf64b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909557528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1909557528
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3171687291
Short name T355
Test name
Test status
Simulation time 35739573962 ps
CPU time 40.53 seconds
Started Jul 29 05:47:14 PM PDT 24
Finished Jul 29 05:47:55 PM PDT 24
Peak memory 201312 kb
Host smart-876c52e3-6431-4ec5-ba02-6c4d27b312a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171687291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3171687291
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3558696391
Short name T707
Test name
Test status
Simulation time 3368302999 ps
CPU time 8.96 seconds
Started Jul 29 05:47:12 PM PDT 24
Finished Jul 29 05:47:21 PM PDT 24
Peak memory 201360 kb
Host smart-f35f5cf1-37f0-4560-9d54-1cbd0e954307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558696391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3558696391
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2483094054
Short name T552
Test name
Test status
Simulation time 5972861497 ps
CPU time 15.48 seconds
Started Jul 29 05:47:02 PM PDT 24
Finished Jul 29 05:47:18 PM PDT 24
Peak memory 201380 kb
Host smart-82a6ee16-9206-4cdc-85fa-f7e6ec298579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483094054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2483094054
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1952434835
Short name T454
Test name
Test status
Simulation time 935607986422 ps
CPU time 97.18 seconds
Started Jul 29 05:47:15 PM PDT 24
Finished Jul 29 05:48:52 PM PDT 24
Peak memory 201512 kb
Host smart-2e5f50a5-b791-4d54-bcb2-27703bdce771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952434835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1952434835
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1806381146
Short name T562
Test name
Test status
Simulation time 490664725 ps
CPU time 0.89 seconds
Started Jul 29 05:47:21 PM PDT 24
Finished Jul 29 05:47:22 PM PDT 24
Peak memory 201240 kb
Host smart-6d76901b-4d1b-46b9-9b3a-17ca0736fd72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806381146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1806381146
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2557821927
Short name T447
Test name
Test status
Simulation time 325652188717 ps
CPU time 218.99 seconds
Started Jul 29 05:47:16 PM PDT 24
Finished Jul 29 05:50:55 PM PDT 24
Peak memory 201388 kb
Host smart-2ad15eab-a6bb-4512-b98f-ae7fc2a446b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557821927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2557821927
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3157170414
Short name T77
Test name
Test status
Simulation time 162047862400 ps
CPU time 85.11 seconds
Started Jul 29 05:47:16 PM PDT 24
Finished Jul 29 05:48:41 PM PDT 24
Peak memory 201444 kb
Host smart-d6b9d0ed-be75-471d-a192-1e0fcafc9586
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157170414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3157170414
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.301112067
Short name T216
Test name
Test status
Simulation time 477794442902 ps
CPU time 285.55 seconds
Started Jul 29 05:47:14 PM PDT 24
Finished Jul 29 05:52:00 PM PDT 24
Peak memory 201520 kb
Host smart-c73e72bf-b825-4672-9087-bab54f11c2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301112067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.301112067
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1198242427
Short name T693
Test name
Test status
Simulation time 487409425590 ps
CPU time 307.46 seconds
Started Jul 29 05:47:16 PM PDT 24
Finished Jul 29 05:52:23 PM PDT 24
Peak memory 201412 kb
Host smart-a289527d-4f58-419a-baf2-7e8dcb0136d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198242427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1198242427
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3237140663
Short name T324
Test name
Test status
Simulation time 391721161222 ps
CPU time 486.96 seconds
Started Jul 29 05:47:23 PM PDT 24
Finished Jul 29 05:55:30 PM PDT 24
Peak memory 201336 kb
Host smart-27da5a1a-8178-4925-bf8b-9398a7df886d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237140663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3237140663
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1354517389
Short name T526
Test name
Test status
Simulation time 88633724653 ps
CPU time 471.59 seconds
Started Jul 29 05:47:23 PM PDT 24
Finished Jul 29 05:55:14 PM PDT 24
Peak memory 201800 kb
Host smart-6d875565-fd91-4fb1-b337-39bd74327216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354517389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1354517389
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.483345704
Short name T483
Test name
Test status
Simulation time 27906727302 ps
CPU time 19.33 seconds
Started Jul 29 05:47:19 PM PDT 24
Finished Jul 29 05:47:39 PM PDT 24
Peak memory 201308 kb
Host smart-33003032-3522-4e9a-ae2f-a41abff68556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483345704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.483345704
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.72166671
Short name T715
Test name
Test status
Simulation time 5173667353 ps
CPU time 12.35 seconds
Started Jul 29 05:47:20 PM PDT 24
Finished Jul 29 05:47:32 PM PDT 24
Peak memory 201360 kb
Host smart-0fd61e8f-52a8-4903-8fbe-3ebdd2c864c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72166671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.72166671
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3584232089
Short name T576
Test name
Test status
Simulation time 5928832590 ps
CPU time 4.38 seconds
Started Jul 29 05:47:12 PM PDT 24
Finished Jul 29 05:47:16 PM PDT 24
Peak memory 201356 kb
Host smart-769a3839-2079-4b30-b749-ea4674f24433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584232089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3584232089
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.674638158
Short name T695
Test name
Test status
Simulation time 255811086182 ps
CPU time 347.31 seconds
Started Jul 29 05:47:20 PM PDT 24
Finished Jul 29 05:53:08 PM PDT 24
Peak memory 212220 kb
Host smart-c4475613-def6-4263-a256-c817719d448a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674638158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
674638158
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2283986093
Short name T689
Test name
Test status
Simulation time 395510287485 ps
CPU time 403.53 seconds
Started Jul 29 05:47:21 PM PDT 24
Finished Jul 29 05:54:04 PM PDT 24
Peak memory 217896 kb
Host smart-2ee67040-245e-4b6f-8355-4e49c3e8d3fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283986093 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2283986093
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3851431390
Short name T350
Test name
Test status
Simulation time 521198373 ps
CPU time 1.16 seconds
Started Jul 29 05:47:31 PM PDT 24
Finished Jul 29 05:47:32 PM PDT 24
Peak memory 201204 kb
Host smart-ea9add21-5ae4-4ffa-90b0-8b2892e4c20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851431390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3851431390
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2345417003
Short name T706
Test name
Test status
Simulation time 327154620428 ps
CPU time 452.44 seconds
Started Jul 29 05:47:29 PM PDT 24
Finished Jul 29 05:55:02 PM PDT 24
Peak memory 201324 kb
Host smart-013db35c-d7ee-49af-8cab-f655e91b778b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345417003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2345417003
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3457921650
Short name T86
Test name
Test status
Simulation time 168469379539 ps
CPU time 398.86 seconds
Started Jul 29 05:47:31 PM PDT 24
Finished Jul 29 05:54:10 PM PDT 24
Peak memory 201456 kb
Host smart-37e89584-f56e-4588-a977-75050ab7de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457921650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3457921650
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2895697802
Short name T363
Test name
Test status
Simulation time 326859694607 ps
CPU time 206.08 seconds
Started Jul 29 05:47:24 PM PDT 24
Finished Jul 29 05:50:50 PM PDT 24
Peak memory 201660 kb
Host smart-420a19c5-a104-468b-80a5-60d6298b57cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895697802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2895697802
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2181580174
Short name T668
Test name
Test status
Simulation time 329850458399 ps
CPU time 519.11 seconds
Started Jul 29 05:47:24 PM PDT 24
Finished Jul 29 05:56:04 PM PDT 24
Peak memory 201372 kb
Host smart-9ab531c5-7663-44fe-81ff-dea1101b0b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181580174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2181580174
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2194998707
Short name T149
Test name
Test status
Simulation time 163774163215 ps
CPU time 93.09 seconds
Started Jul 29 05:47:25 PM PDT 24
Finished Jul 29 05:48:58 PM PDT 24
Peak memory 201332 kb
Host smart-48fe0969-3496-4f07-9f80-f9961da351d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194998707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2194998707
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.568105635
Short name T89
Test name
Test status
Simulation time 201118055684 ps
CPU time 422.23 seconds
Started Jul 29 05:47:33 PM PDT 24
Finished Jul 29 05:54:35 PM PDT 24
Peak memory 201336 kb
Host smart-454a4a36-94ec-443d-9962-5c9cee166492
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568105635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.568105635
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1509011093
Short name T197
Test name
Test status
Simulation time 131490437325 ps
CPU time 543.66 seconds
Started Jul 29 05:47:31 PM PDT 24
Finished Jul 29 05:56:35 PM PDT 24
Peak memory 201820 kb
Host smart-2bcb173c-d2c2-4788-9035-2ac6ad182197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509011093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1509011093
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3229433574
Short name T491
Test name
Test status
Simulation time 44402670783 ps
CPU time 22.68 seconds
Started Jul 29 05:47:31 PM PDT 24
Finished Jul 29 05:47:54 PM PDT 24
Peak memory 201288 kb
Host smart-30905474-c3f5-40dc-ad53-baff23f6e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229433574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3229433574
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3949233644
Short name T664
Test name
Test status
Simulation time 5141639860 ps
CPU time 6.81 seconds
Started Jul 29 05:47:31 PM PDT 24
Finished Jul 29 05:47:38 PM PDT 24
Peak memory 201316 kb
Host smart-fdfe092a-26f7-47a3-9e3d-f62c72160b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949233644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3949233644
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4096087521
Short name T391
Test name
Test status
Simulation time 6190756274 ps
CPU time 2.94 seconds
Started Jul 29 05:47:23 PM PDT 24
Finished Jul 29 05:47:26 PM PDT 24
Peak memory 201272 kb
Host smart-6e425f81-31df-4c68-9dce-7289fe294722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096087521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4096087521
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.136759721
Short name T510
Test name
Test status
Simulation time 10284714131 ps
CPU time 13.23 seconds
Started Jul 29 05:47:30 PM PDT 24
Finished Jul 29 05:47:44 PM PDT 24
Peak memory 201340 kb
Host smart-9c476206-e3fa-4454-9cb0-7b1e2d6a8b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136759721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
136759721
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4220858475
Short name T22
Test name
Test status
Simulation time 38212095054 ps
CPU time 103.76 seconds
Started Jul 29 05:47:30 PM PDT 24
Finished Jul 29 05:49:14 PM PDT 24
Peak memory 211104 kb
Host smart-2da07199-3854-4a37-b80a-b517b01021ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220858475 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4220858475
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1383028809
Short name T677
Test name
Test status
Simulation time 412038987 ps
CPU time 0.74 seconds
Started Jul 29 05:47:47 PM PDT 24
Finished Jul 29 05:47:48 PM PDT 24
Peak memory 201248 kb
Host smart-7589c508-269b-47b6-94d8-15f4b3211d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383028809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1383028809
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1181498146
Short name T669
Test name
Test status
Simulation time 164655671727 ps
CPU time 72.08 seconds
Started Jul 29 05:47:37 PM PDT 24
Finished Jul 29 05:48:50 PM PDT 24
Peak memory 201416 kb
Host smart-8ee5ebc5-fe5d-412f-8bff-7928062294e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181498146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1181498146
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.604526307
Short name T511
Test name
Test status
Simulation time 490991810237 ps
CPU time 1098.99 seconds
Started Jul 29 05:47:38 PM PDT 24
Finished Jul 29 06:05:57 PM PDT 24
Peak memory 201432 kb
Host smart-b47fe571-b0fa-4d0e-9b80-4a9df6e43e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604526307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.604526307
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1229009699
Short name T25
Test name
Test status
Simulation time 502909525551 ps
CPU time 278.79 seconds
Started Jul 29 05:47:34 PM PDT 24
Finished Jul 29 05:52:13 PM PDT 24
Peak memory 201464 kb
Host smart-290574a5-7fd3-4493-a2dc-2d7e872f15a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229009699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1229009699
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3054787746
Short name T550
Test name
Test status
Simulation time 331778529676 ps
CPU time 366.09 seconds
Started Jul 29 05:47:36 PM PDT 24
Finished Jul 29 05:53:42 PM PDT 24
Peak memory 201484 kb
Host smart-3730efba-fe6d-4655-ad4b-8e7686238a0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054787746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3054787746
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1653692274
Short name T498
Test name
Test status
Simulation time 161970520904 ps
CPU time 394.17 seconds
Started Jul 29 05:47:35 PM PDT 24
Finished Jul 29 05:54:09 PM PDT 24
Peak memory 201372 kb
Host smart-cbc78527-0296-48e6-9d84-3fc926f6af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653692274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1653692274
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1137729926
Short name T563
Test name
Test status
Simulation time 169867172723 ps
CPU time 409.21 seconds
Started Jul 29 05:47:33 PM PDT 24
Finished Jul 29 05:54:23 PM PDT 24
Peak memory 201364 kb
Host smart-79647646-36ac-4937-89bc-463e7006de59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137729926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1137729926
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2404083693
Short name T753
Test name
Test status
Simulation time 400010448593 ps
CPU time 881.65 seconds
Started Jul 29 05:47:37 PM PDT 24
Finished Jul 29 06:02:18 PM PDT 24
Peak memory 201364 kb
Host smart-0481c6af-274d-485b-aaf1-0e54213c6a4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404083693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2404083693
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.224541793
Short name T585
Test name
Test status
Simulation time 116259702124 ps
CPU time 573.08 seconds
Started Jul 29 05:47:42 PM PDT 24
Finished Jul 29 05:57:15 PM PDT 24
Peak memory 201884 kb
Host smart-b85e9c3e-81ba-42d8-8ef1-8fe41b00b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224541793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.224541793
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1746323638
Short name T392
Test name
Test status
Simulation time 27886780274 ps
CPU time 60.42 seconds
Started Jul 29 05:47:37 PM PDT 24
Finished Jul 29 05:48:38 PM PDT 24
Peak memory 201360 kb
Host smart-31346af1-0ae0-4ee3-ac4f-1ef22370d8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746323638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1746323638
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.310011476
Short name T684
Test name
Test status
Simulation time 3536734907 ps
CPU time 5.25 seconds
Started Jul 29 05:47:38 PM PDT 24
Finished Jul 29 05:47:44 PM PDT 24
Peak memory 201348 kb
Host smart-78a0a0b3-e6ff-40ca-a9a1-ae4902cbfc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310011476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.310011476
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3346217436
Short name T367
Test name
Test status
Simulation time 5871753322 ps
CPU time 10.03 seconds
Started Jul 29 05:47:29 PM PDT 24
Finished Jul 29 05:47:39 PM PDT 24
Peak memory 201304 kb
Host smart-a10c4cf0-cbe1-4bc5-89f9-6505c1d2b787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346217436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3346217436
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2625389183
Short name T323
Test name
Test status
Simulation time 391573010 ps
CPU time 1.06 seconds
Started Jul 29 05:47:56 PM PDT 24
Finished Jul 29 05:47:58 PM PDT 24
Peak memory 201248 kb
Host smart-583162fc-5ef1-42fb-a654-c6303e3303d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625389183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2625389183
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1045078557
Short name T710
Test name
Test status
Simulation time 339613004712 ps
CPU time 169.33 seconds
Started Jul 29 05:47:52 PM PDT 24
Finished Jul 29 05:50:41 PM PDT 24
Peak memory 201440 kb
Host smart-a5ba206b-a896-47cd-a318-b83b601acb74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045078557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1045078557
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2470555158
Short name T170
Test name
Test status
Simulation time 503320321112 ps
CPU time 889.7 seconds
Started Jul 29 05:47:49 PM PDT 24
Finished Jul 29 06:02:39 PM PDT 24
Peak memory 201408 kb
Host smart-da4e323a-8009-4959-9e3c-2078906a85f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470555158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2470555158
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3203530171
Short name T225
Test name
Test status
Simulation time 329590192069 ps
CPU time 392.42 seconds
Started Jul 29 05:47:47 PM PDT 24
Finished Jul 29 05:54:19 PM PDT 24
Peak memory 201408 kb
Host smart-912d89a6-5ed3-44c7-99ac-25a86b67d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203530171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3203530171
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3814642330
Short name T626
Test name
Test status
Simulation time 167177784021 ps
CPU time 102.94 seconds
Started Jul 29 05:47:51 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 201440 kb
Host smart-0c722cca-ddba-4f50-9ee5-6974fee18a77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814642330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3814642330
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2493182153
Short name T446
Test name
Test status
Simulation time 490654541097 ps
CPU time 570.63 seconds
Started Jul 29 05:47:47 PM PDT 24
Finished Jul 29 05:57:17 PM PDT 24
Peak memory 201436 kb
Host smart-e9bbb78a-c14d-4f5f-88d4-548871f49f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493182153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2493182153
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.42534295
Short name T329
Test name
Test status
Simulation time 164817759510 ps
CPU time 76.98 seconds
Started Jul 29 05:47:48 PM PDT 24
Finished Jul 29 05:49:05 PM PDT 24
Peak memory 201400 kb
Host smart-cf174f19-2a09-4df5-a594-62d0628f06d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed
.42534295
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1118409356
Short name T665
Test name
Test status
Simulation time 192956571612 ps
CPU time 427.31 seconds
Started Jul 29 05:47:51 PM PDT 24
Finished Jul 29 05:54:59 PM PDT 24
Peak memory 201428 kb
Host smart-49297b07-6277-443e-a605-0be2719cb7a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118409356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1118409356
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.899334604
Short name T649
Test name
Test status
Simulation time 200005077253 ps
CPU time 125.47 seconds
Started Jul 29 05:47:51 PM PDT 24
Finished Jul 29 05:49:56 PM PDT 24
Peak memory 201484 kb
Host smart-ae64529f-3db0-453a-a2c0-1c709fdec5fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899334604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.899334604
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3374495316
Short name T200
Test name
Test status
Simulation time 97277562560 ps
CPU time 585.7 seconds
Started Jul 29 05:47:50 PM PDT 24
Finished Jul 29 05:57:36 PM PDT 24
Peak memory 201832 kb
Host smart-edf5ee65-5e12-4182-a389-e1f4937c7eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374495316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3374495316
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.629895268
Short name T103
Test name
Test status
Simulation time 46347131212 ps
CPU time 102.85 seconds
Started Jul 29 05:47:52 PM PDT 24
Finished Jul 29 05:49:35 PM PDT 24
Peak memory 201320 kb
Host smart-260e0598-b66c-4318-9182-b83546bfbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629895268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.629895268
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3457683561
Short name T128
Test name
Test status
Simulation time 3669814716 ps
CPU time 2.77 seconds
Started Jul 29 05:47:50 PM PDT 24
Finished Jul 29 05:47:53 PM PDT 24
Peak memory 201348 kb
Host smart-7dbb0a68-df4c-4376-b4d9-70685dceab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457683561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3457683561
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3399783942
Short name T737
Test name
Test status
Simulation time 5890565514 ps
CPU time 13 seconds
Started Jul 29 05:47:49 PM PDT 24
Finished Jul 29 05:48:02 PM PDT 24
Peak memory 201368 kb
Host smart-2d5ab2cf-4af4-4815-b180-daff627f1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399783942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3399783942
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.736495782
Short name T687
Test name
Test status
Simulation time 161619776668 ps
CPU time 53.9 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 05:48:49 PM PDT 24
Peak memory 201444 kb
Host smart-34bae126-bf86-4131-9aca-dd017bc4b489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736495782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
736495782
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2940698248
Short name T36
Test name
Test status
Simulation time 370863499662 ps
CPU time 124.04 seconds
Started Jul 29 05:47:52 PM PDT 24
Finished Jul 29 05:49:56 PM PDT 24
Peak memory 209756 kb
Host smart-b2e3281f-14fb-46a5-922d-80b8a8297944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940698248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2940698248
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3497263097
Short name T521
Test name
Test status
Simulation time 295860563 ps
CPU time 1.27 seconds
Started Jul 29 05:40:15 PM PDT 24
Finished Jul 29 05:40:17 PM PDT 24
Peak memory 201220 kb
Host smart-458cffad-82e5-4287-9076-4a6141063608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497263097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3497263097
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3260717817
Short name T280
Test name
Test status
Simulation time 495203658671 ps
CPU time 281.61 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:44:49 PM PDT 24
Peak memory 201376 kb
Host smart-416dfd89-daef-4639-9f72-00966d2fffdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260717817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3260717817
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.298663718
Short name T132
Test name
Test status
Simulation time 166090754318 ps
CPU time 38.38 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:40:45 PM PDT 24
Peak memory 201428 kb
Host smart-578d4128-ccac-46f1-95e3-1cd6db4f222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298663718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.298663718
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3412541879
Short name T38
Test name
Test status
Simulation time 497275349579 ps
CPU time 593.86 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:50:01 PM PDT 24
Peak memory 201448 kb
Host smart-8a72eaf7-c787-4e71-9fed-780d63d3d9b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412541879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3412541879
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1563363005
Short name T93
Test name
Test status
Simulation time 492244773533 ps
CPU time 1118.2 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:58:48 PM PDT 24
Peak memory 201460 kb
Host smart-407b47b4-27e8-498e-a28b-6a1404f9575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563363005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1563363005
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2665128056
Short name T504
Test name
Test status
Simulation time 332369143560 ps
CPU time 722.98 seconds
Started Jul 29 05:40:07 PM PDT 24
Finished Jul 29 05:52:11 PM PDT 24
Peak memory 201372 kb
Host smart-1c1ae5e0-7c0b-458f-9f3b-c9b31273d7fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665128056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2665128056
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4267298459
Short name T85
Test name
Test status
Simulation time 383115417148 ps
CPU time 875.04 seconds
Started Jul 29 05:40:10 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 201444 kb
Host smart-46917f43-e622-4476-8b07-183af2758682
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267298459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4267298459
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.231498231
Short name T513
Test name
Test status
Simulation time 205206834090 ps
CPU time 448.1 seconds
Started Jul 29 05:40:08 PM PDT 24
Finished Jul 29 05:47:36 PM PDT 24
Peak memory 201440 kb
Host smart-2ea4b7d4-d7fd-4599-8eb6-18aa5b15f8b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231498231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.231498231
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2610209123
Short name T615
Test name
Test status
Simulation time 113476865189 ps
CPU time 456.49 seconds
Started Jul 29 05:40:16 PM PDT 24
Finished Jul 29 05:47:52 PM PDT 24
Peak memory 201852 kb
Host smart-37130647-404c-4309-8047-4799613d2cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610209123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2610209123
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1213266987
Short name T744
Test name
Test status
Simulation time 31085860110 ps
CPU time 34.76 seconds
Started Jul 29 05:40:12 PM PDT 24
Finished Jul 29 05:40:47 PM PDT 24
Peak memory 201360 kb
Host smart-a524f7c1-3f51-478a-918e-92906662de40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213266987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1213266987
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1986243578
Short name T464
Test name
Test status
Simulation time 3101825001 ps
CPU time 4.56 seconds
Started Jul 29 05:40:13 PM PDT 24
Finished Jul 29 05:40:18 PM PDT 24
Peak memory 201352 kb
Host smart-60299296-3aa1-4a98-94a4-c81441af846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986243578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1986243578
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2225337397
Short name T435
Test name
Test status
Simulation time 5974548044 ps
CPU time 8.11 seconds
Started Jul 29 05:40:11 PM PDT 24
Finished Jul 29 05:40:19 PM PDT 24
Peak memory 201388 kb
Host smart-d104b2d3-0081-492b-aeae-ed0816adb06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225337397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2225337397
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2257073917
Short name T301
Test name
Test status
Simulation time 345171027354 ps
CPU time 209.35 seconds
Started Jul 29 05:40:12 PM PDT 24
Finished Jul 29 05:43:42 PM PDT 24
Peak memory 201444 kb
Host smart-9e3f6c1e-fc0e-4215-9812-81f0cbb75ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257073917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2257073917
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3863779971
Short name T78
Test name
Test status
Simulation time 75307407642 ps
CPU time 131.89 seconds
Started Jul 29 05:40:13 PM PDT 24
Finished Jul 29 05:42:25 PM PDT 24
Peak memory 210452 kb
Host smart-66dc01bf-b25f-49fb-8ff4-06b4489a67be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863779971 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3863779971
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3005395738
Short name T439
Test name
Test status
Simulation time 322915076 ps
CPU time 1.01 seconds
Started Jul 29 05:40:19 PM PDT 24
Finished Jul 29 05:40:20 PM PDT 24
Peak memory 201228 kb
Host smart-e71fd079-65ed-48d7-b3fd-4ec5fcb4dbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005395738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3005395738
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4266680374
Short name T783
Test name
Test status
Simulation time 338449642418 ps
CPU time 744.48 seconds
Started Jul 29 05:40:15 PM PDT 24
Finished Jul 29 05:52:40 PM PDT 24
Peak memory 201384 kb
Host smart-77d3395e-6ab3-4ca5-9c8e-60986ebbd6ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266680374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4266680374
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2680013297
Short name T310
Test name
Test status
Simulation time 511083157244 ps
CPU time 283.41 seconds
Started Jul 29 05:40:14 PM PDT 24
Finished Jul 29 05:44:58 PM PDT 24
Peak memory 201416 kb
Host smart-41cea2a6-8b7f-4de0-b87c-7b3dc89c2017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680013297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2680013297
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.537896568
Short name T154
Test name
Test status
Simulation time 484902331288 ps
CPU time 275.79 seconds
Started Jul 29 05:40:15 PM PDT 24
Finished Jul 29 05:44:51 PM PDT 24
Peak memory 201392 kb
Host smart-8a4a0086-8fb8-418f-888b-a5abd7d82bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537896568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.537896568
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1411564556
Short name T453
Test name
Test status
Simulation time 317498235621 ps
CPU time 188.85 seconds
Started Jul 29 05:40:14 PM PDT 24
Finished Jul 29 05:43:23 PM PDT 24
Peak memory 201452 kb
Host smart-20da0f0a-a4b6-4fe7-84c9-ea1bf49186ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411564556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1411564556
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.568705374
Short name T597
Test name
Test status
Simulation time 338804038145 ps
CPU time 742.96 seconds
Started Jul 29 05:40:13 PM PDT 24
Finished Jul 29 05:52:36 PM PDT 24
Peak memory 201448 kb
Host smart-c01c8d15-6da4-4f07-9ebe-951df905708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568705374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.568705374
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3495616225
Short name T382
Test name
Test status
Simulation time 334600019796 ps
CPU time 190.61 seconds
Started Jul 29 05:40:13 PM PDT 24
Finished Jul 29 05:43:24 PM PDT 24
Peak memory 201392 kb
Host smart-b43d111d-7c00-4b45-a263-537b501220c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495616225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3495616225
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4125185150
Short name T539
Test name
Test status
Simulation time 627502275414 ps
CPU time 752.83 seconds
Started Jul 29 05:40:16 PM PDT 24
Finished Jul 29 05:52:49 PM PDT 24
Peak memory 201456 kb
Host smart-cc4f8438-9b49-44cc-a603-065a1f089e02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125185150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4125185150
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3649611524
Short name T201
Test name
Test status
Simulation time 90736554930 ps
CPU time 392.93 seconds
Started Jul 29 05:40:17 PM PDT 24
Finished Jul 29 05:46:50 PM PDT 24
Peak memory 201820 kb
Host smart-9831817a-7b0a-41ff-8c6a-85a3c7864851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649611524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3649611524
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.524591467
Short name T385
Test name
Test status
Simulation time 34335024879 ps
CPU time 34.05 seconds
Started Jul 29 05:40:21 PM PDT 24
Finished Jul 29 05:40:56 PM PDT 24
Peak memory 201348 kb
Host smart-5768a37e-ce80-41b0-9572-36b764b5ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524591467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.524591467
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3040781937
Short name T786
Test name
Test status
Simulation time 3853942398 ps
CPU time 9.28 seconds
Started Jul 29 05:40:15 PM PDT 24
Finished Jul 29 05:40:25 PM PDT 24
Peak memory 201288 kb
Host smart-11266581-a0cb-4bed-9e2c-6d3485c14db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040781937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3040781937
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.318902284
Short name T395
Test name
Test status
Simulation time 5872571666 ps
CPU time 1.67 seconds
Started Jul 29 05:40:16 PM PDT 24
Finished Jul 29 05:40:17 PM PDT 24
Peak memory 201356 kb
Host smart-d16644b0-664b-4aa4-9781-13ddfac69b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318902284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.318902284
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4237874614
Short name T306
Test name
Test status
Simulation time 554448234988 ps
CPU time 455.99 seconds
Started Jul 29 05:40:18 PM PDT 24
Finished Jul 29 05:47:54 PM PDT 24
Peak memory 201464 kb
Host smart-0a8adca3-d8ee-455b-ba21-7155c45c71c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237874614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4237874614
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1377295424
Short name T219
Test name
Test status
Simulation time 76213996904 ps
CPU time 85.41 seconds
Started Jul 29 05:40:19 PM PDT 24
Finished Jul 29 05:41:45 PM PDT 24
Peak memory 213228 kb
Host smart-7060f745-8d01-4081-bf23-0d79c157cc20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377295424 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1377295424
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3031532628
Short name T635
Test name
Test status
Simulation time 383234182 ps
CPU time 0.81 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:40:24 PM PDT 24
Peak memory 201248 kb
Host smart-fd66248a-b142-4fb7-919c-ce0508ed6790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031532628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3031532628
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1465243783
Short name T82
Test name
Test status
Simulation time 504341896281 ps
CPU time 421.26 seconds
Started Jul 29 05:40:16 PM PDT 24
Finished Jul 29 05:47:18 PM PDT 24
Peak memory 201440 kb
Host smart-0ca9f59d-c43d-41b0-8036-19373e866cab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465243783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1465243783
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3866618745
Short name T180
Test name
Test status
Simulation time 490007579782 ps
CPU time 283.71 seconds
Started Jul 29 05:40:19 PM PDT 24
Finished Jul 29 05:45:03 PM PDT 24
Peak memory 201388 kb
Host smart-a2c8ea5d-5acf-4aa6-8ec5-f929133ad0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866618745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3866618745
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4113134113
Short name T527
Test name
Test status
Simulation time 164799132750 ps
CPU time 386.8 seconds
Started Jul 29 05:40:18 PM PDT 24
Finished Jul 29 05:46:45 PM PDT 24
Peak memory 201444 kb
Host smart-01af6ad5-8d13-429c-882f-ede2952b7d80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113134113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4113134113
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3226158731
Short name T515
Test name
Test status
Simulation time 331131628734 ps
CPU time 223.18 seconds
Started Jul 29 05:40:19 PM PDT 24
Finished Jul 29 05:44:02 PM PDT 24
Peak memory 201420 kb
Host smart-cc73b271-56a6-4e09-b025-87b2c4b3ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226158731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3226158731
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1663895429
Short name T317
Test name
Test status
Simulation time 167620928957 ps
CPU time 186.76 seconds
Started Jul 29 05:40:18 PM PDT 24
Finished Jul 29 05:43:25 PM PDT 24
Peak memory 201448 kb
Host smart-9d820169-f887-48df-b24b-8bf064494ea2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663895429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1663895429
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1096012010
Short name T293
Test name
Test status
Simulation time 175444626090 ps
CPU time 116.97 seconds
Started Jul 29 05:40:22 PM PDT 24
Finished Jul 29 05:42:19 PM PDT 24
Peak memory 201476 kb
Host smart-2d39dda2-5d6c-4fa9-97a3-04c9db8838e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096012010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1096012010
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.102079769
Short name T418
Test name
Test status
Simulation time 415666325663 ps
CPU time 451.6 seconds
Started Jul 29 05:40:18 PM PDT 24
Finished Jul 29 05:47:50 PM PDT 24
Peak memory 201368 kb
Host smart-b49c43c4-6af1-4657-92a9-a2bf14f4e959
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102079769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.102079769
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1331901948
Short name T593
Test name
Test status
Simulation time 106005911402 ps
CPU time 389.05 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:46:56 PM PDT 24
Peak memory 201760 kb
Host smart-cbb69b7c-9905-4680-b004-46ea25a8fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331901948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1331901948
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1615419525
Short name T335
Test name
Test status
Simulation time 40962467954 ps
CPU time 23.91 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:40:49 PM PDT 24
Peak memory 201376 kb
Host smart-d23908bb-fb7b-4f50-9f53-84cc593caba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615419525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1615419525
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3573586718
Short name T594
Test name
Test status
Simulation time 4705290241 ps
CPU time 1.93 seconds
Started Jul 29 05:40:24 PM PDT 24
Finished Jul 29 05:40:27 PM PDT 24
Peak memory 201352 kb
Host smart-d588f4c9-b345-4801-bd3e-74647cfdd53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573586718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3573586718
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2949895418
Short name T127
Test name
Test status
Simulation time 6004947841 ps
CPU time 6.23 seconds
Started Jul 29 05:40:19 PM PDT 24
Finished Jul 29 05:40:25 PM PDT 24
Peak memory 201368 kb
Host smart-53cfb80a-a438-4453-83ae-d8f60c25b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949895418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2949895418
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3911903566
Short name T553
Test name
Test status
Simulation time 40105646022 ps
CPU time 24.56 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:40:48 PM PDT 24
Peak memory 201376 kb
Host smart-556dbf61-4dc7-4fe9-82ea-f71827440c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911903566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3911903566
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4263116858
Short name T183
Test name
Test status
Simulation time 49133172130 ps
CPU time 96.03 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:42:01 PM PDT 24
Peak memory 209840 kb
Host smart-126649e7-260f-4613-ac59-1643d321c86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263116858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4263116858
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.314374091
Short name T81
Test name
Test status
Simulation time 415474225 ps
CPU time 0.84 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:40:37 PM PDT 24
Peak memory 201172 kb
Host smart-7394093c-3890-4976-9d2f-b0d87da173c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314374091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.314374091
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3056753213
Short name T735
Test name
Test status
Simulation time 500823237427 ps
CPU time 255.62 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:44:39 PM PDT 24
Peak memory 201412 kb
Host smart-05962783-f972-42e2-8aa6-467142b31f5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056753213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3056753213
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2623200385
Short name T500
Test name
Test status
Simulation time 325644413407 ps
CPU time 720.79 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:52:26 PM PDT 24
Peak memory 201440 kb
Host smart-1014a4b4-91ed-4722-98c0-fb51a6e79517
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623200385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2623200385
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3631662463
Short name T174
Test name
Test status
Simulation time 319791444913 ps
CPU time 112.07 seconds
Started Jul 29 05:40:22 PM PDT 24
Finished Jul 29 05:42:14 PM PDT 24
Peak memory 201428 kb
Host smart-2ffd1a7b-b8fb-467f-84e5-9c43aa503ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631662463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3631662463
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2749726339
Short name T741
Test name
Test status
Simulation time 322501689362 ps
CPU time 225.72 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:44:11 PM PDT 24
Peak memory 201436 kb
Host smart-2accb15d-4480-4846-ae73-da7bd25707ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749726339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2749726339
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2888137584
Short name T304
Test name
Test status
Simulation time 558590351301 ps
CPU time 307.83 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:45:33 PM PDT 24
Peak memory 201392 kb
Host smart-026b1472-329e-40c6-b308-e1f525cb28cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888137584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2888137584
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.534129639
Short name T528
Test name
Test status
Simulation time 201294269585 ps
CPU time 123.51 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:42:27 PM PDT 24
Peak memory 201452 kb
Host smart-dd05b6c7-ac7f-4950-bc8a-c986052c3fd5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534129639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.534129639
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.539641776
Short name T623
Test name
Test status
Simulation time 83898539807 ps
CPU time 461.24 seconds
Started Jul 29 05:40:23 PM PDT 24
Finished Jul 29 05:48:04 PM PDT 24
Peak memory 201828 kb
Host smart-5f5f44de-33fe-4f72-9f2e-f0db11cc9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539641776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.539641776
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.276429745
Short name T338
Test name
Test status
Simulation time 22482660433 ps
CPU time 7.07 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:40:32 PM PDT 24
Peak memory 201300 kb
Host smart-9593646f-43a2-4216-b663-e0a5c93a3dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276429745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.276429745
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3855188675
Short name T767
Test name
Test status
Simulation time 5055074231 ps
CPU time 2.09 seconds
Started Jul 29 05:40:25 PM PDT 24
Finished Jul 29 05:40:27 PM PDT 24
Peak memory 201360 kb
Host smart-84ec096e-accc-46d7-b4df-9707aebd8a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855188675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3855188675
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2703455532
Short name T690
Test name
Test status
Simulation time 5706446980 ps
CPU time 14.73 seconds
Started Jul 29 05:40:24 PM PDT 24
Finished Jul 29 05:40:40 PM PDT 24
Peak memory 201288 kb
Host smart-13cab58f-9ec0-43c6-94bf-19112b2826fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703455532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2703455532
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.284368320
Short name T384
Test name
Test status
Simulation time 6457657908 ps
CPU time 14.62 seconds
Started Jul 29 05:40:28 PM PDT 24
Finished Jul 29 05:40:43 PM PDT 24
Peak memory 201380 kb
Host smart-b32467bc-a93e-42cc-bbc8-1dbc02df3d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284368320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.284368320
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1238152805
Short name T549
Test name
Test status
Simulation time 77535724418 ps
CPU time 203.01 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:43:51 PM PDT 24
Peak memory 210212 kb
Host smart-dffde1a0-5de4-4c49-beb5-7d97e5a0d6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238152805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1238152805
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3080385716
Short name T660
Test name
Test status
Simulation time 440361087 ps
CPU time 0.88 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:40:28 PM PDT 24
Peak memory 201216 kb
Host smart-1ac06412-f711-473a-9269-f73e79ecbefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080385716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3080385716
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.885285803
Short name T437
Test name
Test status
Simulation time 160610103106 ps
CPU time 37.57 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:41:05 PM PDT 24
Peak memory 201380 kb
Host smart-bb66948b-ba2d-4529-8069-f9a776ae30ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885285803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.885285803
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1237489716
Short name T146
Test name
Test status
Simulation time 495645942182 ps
CPU time 301.09 seconds
Started Jul 29 05:40:30 PM PDT 24
Finished Jul 29 05:45:31 PM PDT 24
Peak memory 201432 kb
Host smart-dc78c465-e06a-41a9-9c94-9bc08400647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237489716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1237489716
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3340758955
Short name T144
Test name
Test status
Simulation time 335215826837 ps
CPU time 207.05 seconds
Started Jul 29 05:40:29 PM PDT 24
Finished Jul 29 05:43:56 PM PDT 24
Peak memory 201420 kb
Host smart-2105c2e3-9f45-4587-988a-f2249eaf1853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340758955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3340758955
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2750711292
Short name T327
Test name
Test status
Simulation time 487004290944 ps
CPU time 358.71 seconds
Started Jul 29 05:40:28 PM PDT 24
Finished Jul 29 05:46:27 PM PDT 24
Peak memory 201464 kb
Host smart-fbd4688a-45e5-4f0a-bbc7-eda52f5424e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750711292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2750711292
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3652755347
Short name T666
Test name
Test status
Simulation time 166599932064 ps
CPU time 336.62 seconds
Started Jul 29 05:40:28 PM PDT 24
Finished Jul 29 05:46:05 PM PDT 24
Peak memory 201324 kb
Host smart-d2032892-599f-42df-89d3-75f1f4fda854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652755347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3652755347
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1699664072
Short name T353
Test name
Test status
Simulation time 492312980124 ps
CPU time 1122.14 seconds
Started Jul 29 05:40:30 PM PDT 24
Finished Jul 29 05:59:12 PM PDT 24
Peak memory 201356 kb
Host smart-bd6db8aa-bc9b-4681-a39b-5895650e3f79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699664072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1699664072
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3200670589
Short name T165
Test name
Test status
Simulation time 356853458906 ps
CPU time 194.13 seconds
Started Jul 29 05:40:30 PM PDT 24
Finished Jul 29 05:43:44 PM PDT 24
Peak memory 201440 kb
Host smart-cd585eeb-e5fd-4c79-b988-69798c248d28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200670589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3200670589
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.35902548
Short name T538
Test name
Test status
Simulation time 198094798250 ps
CPU time 435.2 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:47:42 PM PDT 24
Peak memory 201396 kb
Host smart-9e0a72fa-6fe8-4d5c-a906-a327d2b7ab00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.35902548
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3834329723
Short name T468
Test name
Test status
Simulation time 80078049907 ps
CPU time 264.97 seconds
Started Jul 29 05:40:26 PM PDT 24
Finished Jul 29 05:44:51 PM PDT 24
Peak memory 201884 kb
Host smart-53402466-1b6c-406c-83e7-4bcf881be468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834329723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3834329723
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2584278780
Short name T371
Test name
Test status
Simulation time 29581761231 ps
CPU time 36.76 seconds
Started Jul 29 05:40:28 PM PDT 24
Finished Jul 29 05:41:05 PM PDT 24
Peak memory 201284 kb
Host smart-e2868c1a-799d-41ae-8a92-b339d65af946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584278780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2584278780
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2012234545
Short name T675
Test name
Test status
Simulation time 3864032651 ps
CPU time 2.16 seconds
Started Jul 29 05:40:28 PM PDT 24
Finished Jul 29 05:40:31 PM PDT 24
Peak memory 201348 kb
Host smart-3b0bec69-fabe-4432-aef6-1f86799dc6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012234545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2012234545
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.528435952
Short name T608
Test name
Test status
Simulation time 5760285997 ps
CPU time 12.14 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:40:48 PM PDT 24
Peak memory 201292 kb
Host smart-6efdff20-1378-48be-a111-ba154a3c73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528435952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.528435952
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1920853753
Short name T95
Test name
Test status
Simulation time 167772019145 ps
CPU time 105.81 seconds
Started Jul 29 05:40:27 PM PDT 24
Finished Jul 29 05:42:13 PM PDT 24
Peak memory 201596 kb
Host smart-51230434-bc54-4749-b031-2d48a9fbaaf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920853753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1920853753
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1654251732
Short name T33
Test name
Test status
Simulation time 28808721333 ps
CPU time 65.6 seconds
Started Jul 29 05:40:36 PM PDT 24
Finished Jul 29 05:41:42 PM PDT 24
Peak memory 209488 kb
Host smart-fbc0ec15-9d74-4301-ade2-9b9c8528eb4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654251732 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1654251732
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%