Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7455	1			T3	20		T4	20		T7	7
testmodes[AdcCtrlTestmodeNormal]	5448	1			T1	2		T6	2		T7	5
testmodes[AdcCtrlTestmodeLowpower]	5942	1			T2	10		T5	1		T6	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4216	1			T3	19		T4	19		T7	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1729	1			T7	2		T9	36		T60	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1397	1			T9	27		T60	15		T61	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1730	1			T7	3		T9	45		T60	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1948	1			T1	1		T6	1		T7	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1430	1			T9	20		T15	1		T60	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1390	1			T9	18		T60	14		T61	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1450	1			T6	1		T9	28		T60	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2857	1			T2	9		T9	21		T11	2