Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23387

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3717

1

T1

1

T14

35

T15

51

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20825

1

T1

2

T2

10

T3

20

auto[1]

6279

1

T6

27

T8

1

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T212	1		-	-		-	-
values[0]	46	1			T151	16		T122	1		T216	23
values[1]	699	1			T6	35		T97	21		T185	1
values[2]	570	1			T8	1		T12	11		T14	11
values[3]	482	1			T44	1		T149	3		T142	1
values[4]	3021	1			T10	2		T11	19		T13	15
values[5]	816	1			T46	22		T98	9		T99	18
values[6]	733	1			T1	1		T14	9		T15	36
values[7]	763	1			T6	22		T98	26		T70	2
values[8]	766	1			T1	1		T5	18		T14	15
values[9]	1286	1			T146	3		T58	16		T39	4
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	919	1			T6	35		T8	1		T146	11
values[1]	512	1			T12	11		T14	11		T156	14
values[2]	484	1			T13	15		T15	15		T44	1
values[3]	3073	1			T10	2		T11	19		T59	40
values[4]	794	1			T39	5		T46	22		T98	9
values[5]	670	1			T1	1		T6	22		T14	9
values[6]	797	1			T46	17		T98	26		T149	4
values[7]	841	1			T5	18		T14	15		T52	17
values[8]	894	1			T1	1		T146	3		T58	16
values[9]	199	1			T39	4		T147	14		T70	36
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	19		T8	1		T46	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T146	1		T95	13		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T156	14		T113	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	11		T142	1		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	15		T143	1		T113	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	8		T44	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T10	2		T11	19		T59	40
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T47	13		T149	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	4		T46	10		T98	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T99	9		T147	12		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	12		T143	1		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T14	9		T15	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T98	15		T149	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	9		T40	1		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	11		T217	1		T218	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	15		T52	1		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T146	1		T58	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T58	3		T44	11		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T40	1		T144	13		T219	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T39	3		T147	14		T70	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	16		T46	10		T97	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T146	10		T95	9		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	10		T113	10		T145	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T220	8		T155	1		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T143	7		T113	13		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	7		T149	2		T184	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T141	5		T96	22		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T149	9		T17	1		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	1		T46	12		T98	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T99	9		T145	13		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	10		T143	13		T195	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	17		T69	12		T70	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T98	11		T149	3		T195	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	8		T40	1		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	7		T218	12		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T52	16		T31	18		T224	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	2		T52	4		T70	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T58	4		T143	2		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T40	1		T144	8		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T39	1		T70	17		T113	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T212	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T122	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	7		T216	13		T225	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	19		T97	11		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T226	23		T157	13		T227	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	1		T12	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	11		T146	1		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	1		T113	12		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T44	1		T149	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T10	2		T11	19		T13	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	8		T47	13		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	10		T98	7		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T99	9		T147	12		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	4		T143	1		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T1	1		T14	9		T15	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	12		T98	15		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T70	1		T40	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T5	11		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	15		T52	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T146	1		T58	9		T44	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	422	1			T58	3		T39	3		T44	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T151	9		T216	10		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	16		T97	10		T159	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T226	15		T157	10		T227	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	10		T46	10		T98	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	10		T95	9		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	7		T113	23		T222	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T149	2		T184	3		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T141	5		T96	22		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	7		T149	9		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	12		T98	2		T107	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T99	9		T145	13		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	1		T143	13		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	17		T46	8		T69	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	10		T98	11		T195	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T70	1		T40	1		T112	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	7		T52	4		T149	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T52	16		T143	2		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T146	2		T70	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T58	4		T39	1		T70	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	18		T8	1		T46	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T146	11		T95	10		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	11		T156	1		T113	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T142	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	1		T143	8		T113	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	8		T44	1		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T10	2		T11	3		T59	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	1		T149	10		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	3		T46	13		T98	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T99	10		T147	1		T145	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	11		T143	14		T195	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	1		T14	1		T15	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T98	12		T149	4		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	9		T40	2		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	8		T217	1		T218	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T52	17		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T146	3		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T58	5		T44	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T40	2		T144	9		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T39	4		T147	1		T70	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	17		T97	10		T98	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T95	12		T156	13		T226	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T156	13		T113	8		T184	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T14	10		T144	12		T33	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	14		T113	2		T53	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	7		T184	3		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T11	16		T59	37		T51	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	12		T17	1		T160	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T39	2		T46	9		T98	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T99	8		T147	11		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	11		T152	3		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	8		T15	18		T69	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T98	14		T43	3		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	8		T109	14		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	10		T218	12		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	14		T144	6		T31	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T58	8		T44	10		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T58	2		T44	10		T47	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T144	12		T219	8		T220	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T147	13		T70	18		T113	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T212	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T122	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	10		T216	11		T225	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	18		T97	11		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T226	17		T157	11		T227	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	1		T12	11		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T146	11		T95	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T143	8		T113	25		T222	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T44	1		T149	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T10	2		T11	3		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	8		T47	1		T149	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T46	13		T98	3		T107	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T99	10		T147	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	3		T143	14		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T14	1		T15	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	11		T98	12		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T70	2		T40	2		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T5	8		T52	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	1		T52	17		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T146	3		T58	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T58	5		T39	4		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T151	6		T216	12		T225	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	17		T97	10		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T226	21		T157	12		T227	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T98	12		T156	24		T184	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	10		T95	12		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T113	10		T229	9		T53	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T144	12		T184	3		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T11	16		T13	14		T59	37
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	7		T47	12		T160	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	9		T98	6		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T99	8		T147	11		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	2		T40	2		T29	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	8		T15	18		T46	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	11		T98	14		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T184	10		T31	19		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	10		T42	3		T43	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	14		T109	14		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T58	8		T44	10		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T58	2		T44	10		T47	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23785

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3319

1

T1

1

T5

18

T6

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20892

1

T1

2

T2

10

T3

20

auto[1]

6212

1

T6

22

T9

3

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	408	1			T9	3		T60	4		T61	12
values[0]	105	1			T110	1		T227	31		T231	9
values[1]	707	1			T52	5		T97	21		T110	1
values[2]	3099	1			T10	2		T11	19		T13	15
values[3]	583	1			T6	22		T146	3		T44	1
values[4]	573	1			T12	11		T14	11		T44	11
values[5]	752	1			T58	7		T95	22		T98	9
values[6]	793	1			T8	1		T146	11		T39	5
values[7]	739	1			T98	26		T156	12		T143	14
values[8]	692	1			T14	15		T46	33		T149	3
values[9]	1140	1			T1	2		T5	18		T6	35
minimum	17513	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	957	1			T13	15		T15	36		T39	4
values[1]	3087	1			T10	2		T11	19		T15	15
values[2]	643	1			T6	22		T146	3		T156	14
values[3]	621	1			T12	11		T14	11		T44	11
values[4]	786	1			T44	11		T95	22		T98	9
values[5]	794	1			T8	1		T146	11		T58	7
values[6]	713	1			T142	1		T112	5		T113	35
values[7]	624	1			T5	18		T14	24		T46	33
values[8]	749	1			T6	8		T52	17		T98	26
values[9]	209	1			T1	2		T6	27		T143	8
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T13	15		T15	19		T97	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	3		T52	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T10	2		T11	19		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	7		T224	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	12		T146	1		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	3		T108	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T44	11		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	11		T46	9		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T70	20		T41	3		T43	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T44	11		T95	13		T98	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	1		T146	1		T98	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T58	3		T39	4		T143	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T113	9		T42	5		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T142	1		T112	1		T113	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	9		T46	10		T47	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	11		T14	15		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T52	1		T147	14		T69	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	6		T98	13		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T1	1		T6	13		T184	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T1	1		T143	1		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T15	17		T97	10		T145	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	1		T52	4		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T15	7		T141	5		T96	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T224	4		T223	14		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	10		T146	2		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	2		T108	1		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	10		T149	9		T195	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T46	8		T149	3		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T70	18		T43	2		T194	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T95	9		T98	2		T99	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T146	10		T98	11		T70	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T58	4		T39	1		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T113	10		T42	2		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T112	4		T113	13		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T46	12		T171	4		T56	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	7		T46	10		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T52	16		T69	12		T112	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	2		T98	13		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T6	14		T184	15		T233	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T143	7		T18	10		T234	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T9	3		T60	4		T61	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T110	1		T227	15		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T235	1		T236	7		T237	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T97	11		T110	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	1		T31	1		T152	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T10	2		T11	19		T13	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	3		T144	7		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	12		T146	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T46	9		T40	3		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T44	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	11		T149	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T70	20		T41	3		T194	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T58	3		T95	13		T98	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T146	1		T70	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T39	4		T44	11		T99	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T98	15		T156	12		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T143	1		T112	1		T113	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	10		T142	1		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	15		T46	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T1	1		T6	13		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T1	1		T5	11		T6	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17369	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T227	16		T231	8		T238	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T236	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T97	10		T145	13		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T52	4		T31	1		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1106	1			T15	24		T141	5		T96	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	1		T224	4		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	10		T146	2		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T46	8		T40	2		T108	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	10		T149	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	3		T239	4		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T70	18		T194	9		T226	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T58	4		T95	9		T98	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T146	10		T70	12		T107	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	1		T99	9		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T98	11		T109	14		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T143	13		T112	4		T113	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	12		T113	10		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	10		T149	2		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	14		T52	16		T69	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	7		T6	2		T98	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1