Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21090

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

6014

1

T1

1

T6

27

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21240

1

T1

2

T2

10

T3

20

auto[1]

5864

1

T6

35

T8

1

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	166	1			T40	2		T184	25		T54	8
values[0]	21	1			T113	19		T290	1		T291	1
values[1]	713	1			T15	36		T146	3		T47	5
values[2]	763	1			T14	9		T98	26		T70	25
values[3]	994	1			T1	1		T6	27		T15	15
values[4]	723	1			T1	1		T146	11		T44	11
values[5]	709	1			T6	22		T95	22		T99	18
values[6]	718	1			T12	11		T14	11		T39	5
values[7]	676	1			T39	4		T47	13		T107	18
values[8]	578	1			T5	18		T8	1		T58	9
values[9]	3122	1			T6	8		T10	2		T11	19
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	694	1			T14	9		T47	5		T147	12
values[1]	3163	1			T10	2		T11	19		T15	15
values[2]	947	1			T1	2		T6	27		T44	11
values[3]	638	1			T146	11		T98	26		T185	1
values[4]	736	1			T6	22		T95	22		T99	18
values[5]	709	1			T12	11		T14	11		T39	5
values[6]	630	1			T39	4		T47	13		T70	2
values[7]	634	1			T5	18		T8	1		T58	9
values[8]	741	1			T13	15		T14	15		T46	17
values[9]	60	1			T6	8		T46	11		T40	2
minimum	18152	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	5		T147	12		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	9		T69	13		T156	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T58	3		T185	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1699	1			T10	2		T11	19		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T98	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T1	1		T6	13		T44	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T146	1		T98	13		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T113	12		T170	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	12		T95	13		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T99	9		T147	14		T70	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T39	4		T46	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	11		T44	11		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	3		T47	13		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T70	1		T167	1		T29	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	11		T52	1		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	1		T58	9		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	9		T52	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	15		T14	15		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T6	6		T231	1		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T46	1		T40	1		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17836	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T113	9		T43	7		T227	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T149	3		T40	2		T108	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T69	12		T109	14		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T58	4		T145	1		T167	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1126	1			T15	7		T141	5		T96	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T98	2		T149	9		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	14		T97	10		T112	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T146	10		T98	13		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T113	11		T170	1		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	10		T95	9		T170	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T99	9		T70	17		T195	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	10		T39	1		T46	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T107	17		T31	1		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	1		T34	15		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T70	1		T167	1		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	7		T52	4		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T43	1		T17	3		T254	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	8		T52	16		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	2		T195	2		T184	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T6	2		T231	7		T264	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T46	10		T40	1		T238	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T15	17		T146	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T113	10		T43	2		T227	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T40	1		T54	4		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T184	11		T265	1		T261	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T113	9		T290	1		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	19		T146	1		T47	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T69	13		T156	12		T109	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	3		T108	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	9		T98	15		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T58	3		T98	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T6	13		T15	8		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	1		T98	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T44	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	12		T95	13		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T99	9		T147	14		T70	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T39	4		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	11		T44	11		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	3		T47	13		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T107	1		T29	14		T33	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	11		T147	12		T156	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	1		T58	9		T70	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	6		T46	9		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1688	1			T10	2		T11	19		T13	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T40	1		T54	4		T161	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T184	14		T261	9		T103	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T113	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	17		T146	2		T149	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T69	12		T109	14		T184	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	2		T108	1		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T98	11		T70	12		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T58	4		T98	2		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	14		T15	7		T97	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	10		T98	13		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T113	11		T17	1		T227	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T6	10		T95	9		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T99	9		T70	17		T195	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	10		T39	1		T46	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	1		T150	14		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	1		T34	15		T226	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T107	17		T29	10		T253	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T5	7		T157	10		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T70	1		T167	1		T222	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T46	8		T52	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1074	1			T141	5		T46	10		T96	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T47	1		T147	1		T149	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T69	13		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T58	5		T185	1		T145	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1479	1			T10	2		T11	3		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T98	3		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	1		T6	15		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	11		T98	14		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T113	12		T170	2		T167	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	11		T95	10		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T99	10		T147	1		T70	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	11		T39	3		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	1		T44	1		T107	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	4		T47	1		T34	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T70	2		T167	2		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	8		T52	5		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	1		T58	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	9		T52	17		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T14	1		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T6	3		T231	8		T264	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T46	11		T40	2		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17996	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T113	11		T43	6		T227	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	4		T147	11		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	8		T69	12		T156	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T58	2		T167	10		T194	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T11	16		T15	7		T59	37
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T98	6		T43	2		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	12		T44	10		T97	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T98	12		T144	12		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T113	11		T33	14		T53	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	11		T95	12		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T99	8		T147	13		T70	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	2		T46	9		T19	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	10		T44	10		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T47	12		T34	11		T226	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	13		T33	7		T253	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	10		T147	11		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	8		T17	2		T254	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	8		T113	2		T204	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	14		T14	14		T184	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T6	5		T292	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T15	18		T293	12		T294	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T113	8		T43	3		T227	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T40	2		T54	8		T161	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T184	15		T265	1		T261	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T113	11		T290	1		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T15	18		T146	3		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T69	13		T156	1		T109	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T40	3		T108	2		T145	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T98	12		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	1		T58	5		T98	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	15		T15	8		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	11		T98	14		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T44	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	11		T95	10		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T99	10		T147	1		T70	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	11		T39	3		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T44	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	4		T47	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T107	18		T29	11		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	8		T147	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T58	1		T70	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	3		T46	9		T52	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1426	1			T10	2		T11	3		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T266	18		T292	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T184	10		T261	7		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T113	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	18		T47	4		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T69	12		T156	11		T109	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	2		T194	10		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	8		T98	14		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T58	2		T98	6		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	12		T15	7		T97	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T98	12		T144	12		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	10		T113	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	11		T95	12		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T99	8		T147	13		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	2		T46	9		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	10		T44	10		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	12		T34	11		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	13		T33	7		T253	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	10		T147	11		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T58	8		T254	17		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	5		T46	8		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1336	1			T11	16		T13	14		T14	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16