Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23534

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3570

1

T1

1

T6

57

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21056

1

T1

1

T2

10

T3

20

auto[1]

6048

1

T1

1

T6

49

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	187	1			T5	18		T156	14		T184	25
values[0]	2	1			T110	1		T298	1		-	-
values[1]	682	1			T1	2		T47	13		T110	1
values[2]	442	1			T47	5		T149	3		T143	3
values[3]	616	1			T14	24		T39	4		T95	22
values[4]	664	1			T6	8		T146	3		T44	1
values[5]	3148	1			T6	27		T8	1		T10	2
values[6]	909	1			T6	22		T58	9		T44	22
values[7]	766	1			T99	18		T149	4		T108	22
values[8]	574	1			T12	11		T146	11		T46	11
values[9]	1193	1			T13	15		T14	11		T15	36
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T1	2		T47	13		T110	1
values[1]	488	1			T39	4		T47	5		T95	22
values[2]	611	1			T14	24		T44	1		T98	26
values[3]	3098	1			T6	35		T10	2		T11	19
values[4]	815	1			T8	1		T15	15		T97	21
values[5]	832	1			T6	22		T58	9		T44	22
values[6]	728	1			T149	4		T156	14		T108	22
values[7]	694	1			T12	11		T13	15		T146	11
values[8]	1070	1			T5	18		T14	11		T15	36
values[9]	43	1			T157	1		T276	6		T236	11
minimum	18060	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T47	13		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T167	1		T226	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	3		T47	5		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T95	13		T70	19		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	24		T98	13		T42	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T44	1		T147	12		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T10	2		T11	19		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	19		T58	3		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	8		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T143	1		T113	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T44	11		T46	9		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	12		T58	9		T44	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T108	12		T195	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T149	1		T156	14		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	1		T70	1		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T13	15		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T5	11		T15	19		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	11		T52	1		T98	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T157	1		T299	3		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T276	6		T236	7		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17820	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T152	4		T223	4		T301	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	1		T253	16		T226	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T167	17		T226	8		T53	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T39	1		T149	2		T107	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T95	9		T70	17		T143	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T98	13		T42	2		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	3		T31	17		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T146	2		T141	5		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	16		T58	4		T155	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	7		T97	10		T113	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	7		T113	10		T195	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	8		T170	1		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	10		T52	16		T99	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T108	10		T195	5		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T149	3		T109	14		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T146	10		T70	1		T108	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	10		T46	10		T167	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	7		T15	17		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T52	4		T98	11		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T299	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T236	4		T300	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T152	5		T301	7		T181	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T5	11		T194	11		T157	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T156	14		T184	11		T227	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T110	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	1		T47	13		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T226	10		T53	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	5		T149	1		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T143	1		T144	7		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	24		T39	3		T98	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T95	13		T147	12		T70	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T146	1		T70	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	6		T44	1		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T10	2		T11	19		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	13		T8	1		T58	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T44	11		T46	9		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	12		T58	9		T44	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T108	12		T195	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T99	9		T149	1		T109	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T146	1		T70	1		T156	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T46	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T15	19		T46	10		T98	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T13	15		T14	11		T52	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T5	7		T194	9		T302	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T184	14		T227	10		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	1		T253	16		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T226	8		T53	5		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T149	2		T107	17		T151	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T143	2		T167	17		T56	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T39	1		T98	13		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T95	9		T70	17		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	2		T70	12		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	2		T152	13		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T15	7		T141	5		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	14		T58	4		T195	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	8		T97	10		T170	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	10		T52	16		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T108	10		T195	5		T247	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T99	9		T149	3		T109	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	10		T70	1		T108	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	10		T46	10		T144	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T15	17		T46	12		T98	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T52	4		T98	11		T149	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T47	1		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T167	18		T226	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	4		T47	1		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T95	10		T70	18		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	2		T98	14		T42	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	1		T147	1		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T10	2		T11	3		T146	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	18		T58	5		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	8		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	1		T143	8		T113	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	1		T46	9		T170	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	11		T58	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T108	11		T195	6		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T149	4		T156	1		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T146	11		T70	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	11		T13	1		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T5	8		T15	18		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T14	1		T52	5		T98	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T157	1		T299	6		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T276	1		T236	6		T300	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17962	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T152	6		T223	1		T301	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	12		T144	12		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T226	9		T53	5		T263	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T47	4		T151	14		T219	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T95	12		T70	18		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T14	22		T98	12		T42	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T147	11		T17	2		T31	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T11	16		T59	37		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	17		T58	2		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	7		T97	10		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T113	8		T184	3		T33	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	10		T46	8		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	11		T58	8		T44	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T108	11		T247	19		T56	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	13		T109	14		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T156	11		T113	11		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	14		T43	3		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	10		T15	18		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	10		T98	14		T156	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T299	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T276	5		T236	5		T260	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T178	2		T193	14		T303	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T152	3		T223	3		T301	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T5	8		T194	10		T157	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T156	1		T184	15		T227	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T110	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T47	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T226	9		T53	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	1		T149	3		T107	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T143	3		T144	1		T167	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	2		T39	4		T98	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T95	10		T147	1		T70	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T146	3		T70	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	3		T44	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T10	2		T11	3		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	15		T8	1		T58	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T44	1		T46	9		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	11		T58	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T108	11		T195	6		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T99	10		T149	4		T109	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T146	11		T70	2		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	11		T46	11		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T15	18		T46	13		T98	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T13	1		T14	1		T52	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T5	10		T194	10		T243	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T156	13		T184	10		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	12		T144	12		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T226	9		T53	5		T152	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T47	4		T151	14		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T144	6		T204	10		T263	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	22		T98	12		T42	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T95	12		T147	11		T70	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T70	12		T31	13		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	5		T147	11		T152	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T11	16		T15	7		T59	37
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	12		T58	2		T184	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	10		T46	8		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	11		T58	8		T44	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T108	11		T247	19		T56	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T99	8		T109	14		T184	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T156	11		T113	11		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T156	13		T144	12		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T15	18		T46	9		T98	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	14		T14	10		T98	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16